| ixgbe_phy.h (205720) | ixgbe_phy.h (215911) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 205720 2010-03-27 00:21:40Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 215911 2010-11-26 22:46:32Z jfv $*/ |
| 34 35#ifndef _IXGBE_PHY_H_ 36#define _IXGBE_PHY_H_ 37 38#include "ixgbe_type.h" 39#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 40 41/* EEPROM byte offsets */ --- 5 unchanged lines hidden (view full) --- 47#define IXGBE_SFF_1GBE_COMP_CODES 0x6 48#define IXGBE_SFF_10GBE_COMP_CODES 0x3 49#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 50#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 51 52/* Bitmasks */ 53#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 54#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 | 34 35#ifndef _IXGBE_PHY_H_ 36#define _IXGBE_PHY_H_ 37 38#include "ixgbe_type.h" 39#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 40 41/* EEPROM byte offsets */ --- 5 unchanged lines hidden (view full) --- 47#define IXGBE_SFF_1GBE_COMP_CODES 0x6 48#define IXGBE_SFF_10GBE_COMP_CODES 0x3 49#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 50#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 51 52/* Bitmasks */ 53#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 54#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 |
| 55#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 | 55#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 |
| 56#define IXGBE_SFF_1GBASESX_CAPABLE 0x1 57#define IXGBE_SFF_1GBASELX_CAPABLE 0x2 | 56#define IXGBE_SFF_1GBASESX_CAPABLE 0x1 57#define IXGBE_SFF_1GBASELX_CAPABLE 0x2 |
| 58#define IXGBE_SFF_1GBASET_CAPABLE 0x8 |
|
| 58#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 59#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 60#define IXGBE_I2C_EEPROM_READ_MASK 0x100 61#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 62#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 63#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 64#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 65#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 66 | 59#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 60#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 61#define IXGBE_I2C_EEPROM_READ_MASK 0x100 62#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 63#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 64#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 65#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 66#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 67 |
| 68/* Flow control defines */ 69#define IXGBE_TAF_SYM_PAUSE 0x400 70#define IXGBE_TAF_ASM_PAUSE 0x800 71 |
|
| 67/* Bit-shift macros */ 68#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 69#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 70#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 71 72/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 73#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 74#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 --- 10 unchanged lines hidden (view full) --- 85#define IXGBE_I2C_T_RISE 1 86#define IXGBE_I2C_T_FALL 1 87#define IXGBE_I2C_T_SU_STO 4 88#define IXGBE_I2C_T_BUF 5 89 90#define IXGBE_TN_LASI_STATUS_REG 0x9005 91#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 92 | 72/* Bit-shift macros */ 73#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 74#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 75#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 76 77/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 78#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 79#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 --- 10 unchanged lines hidden (view full) --- 90#define IXGBE_I2C_T_RISE 1 91#define IXGBE_I2C_T_FALL 1 92#define IXGBE_I2C_T_SU_STO 4 93#define IXGBE_I2C_T_BUF 5 94 95#define IXGBE_TN_LASI_STATUS_REG 0x9005 96#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 97 |
| 93 | |
| 94s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 95bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 96enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 97s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 98s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 99s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 100s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 101 u32 device_type, u16 *phy_data); --- 19 unchanged lines hidden (view full) --- 121 u16 *firmware_version); 122 123s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 124s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 125s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 126 u16 *list_offset, 127 u16 *data_offset); 128s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); | 98s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 99bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 100enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 101s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 102s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 103s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 104s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 105 u32 device_type, u16 *phy_data); --- 19 unchanged lines hidden (view full) --- 125 u16 *firmware_version); 126 127s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 128s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 129s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 130 u16 *list_offset, 131 u16 *data_offset); 132s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); |
| 129s32 ixgbe_tn_set_low_power_state(struct ixgbe_hw *hw); | |
| 130s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 131 u8 dev_addr, u8 *data); 132s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 133 u8 dev_addr, u8 data); 134s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 135 u8 *eeprom_data); 136s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 137 u8 eeprom_data); 138#endif /* _IXGBE_PHY_H_ */ | 133s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 134 u8 dev_addr, u8 *data); 135s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 136 u8 dev_addr, u8 data); 137s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 138 u8 *eeprom_data); 139s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 140 u8 eeprom_data); 141#endif /* _IXGBE_PHY_H_ */ |