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ixgbe_common.c (194875) ixgbe_common.c (200239)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 194875 2009-06-24 18:27:07Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 200239 2009-12-07 21:30:54Z jfv $*/
34
35#include "ixgbe_common.h"
36#include "ixgbe_api.h"
37
34
35#include "ixgbe_common.h"
36#include "ixgbe_api.h"
37
38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 u16 count);
46static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 u16 count);
45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
51
52static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
49
50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
51static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
52 u16 *san_mac_offset);
53s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
53
54/**
55 * ixgbe_init_ops_generic - Inits function ptrs
56 * @hw: pointer to the hardware structure
57 *
58 * Initialize the function pointers.
59 **/
60s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
61{
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
63 struct ixgbe_mac_info *mac = &hw->mac;
64 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
65
54
55/**
56 * ixgbe_init_ops_generic - Inits function ptrs
57 * @hw: pointer to the hardware structure
58 *
59 * Initialize the function pointers.
60 **/
61s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
62{
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
64 struct ixgbe_mac_info *mac = &hw->mac;
65 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
66
67 DEBUGFUNC("ixgbe_init_ops_generic");
68
66 /* EEPROM */
67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
68 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
69 if (eec & (1 << 8))
69 /* EEPROM */
70 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
71 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
72 if (eec & (1 << 8))
70 eeprom->ops.read = &ixgbe_read_eeprom_generic;
73 eeprom->ops.read = &ixgbe_read_eerd_generic;
71 else
72 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
73 eeprom->ops.write = &ixgbe_write_eeprom_generic;
74 eeprom->ops.validate_checksum =
75 &ixgbe_validate_eeprom_checksum_generic;
76 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
74 else
75 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
76 eeprom->ops.write = &ixgbe_write_eeprom_generic;
77 eeprom->ops.validate_checksum =
78 &ixgbe_validate_eeprom_checksum_generic;
79 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
80 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
77
78 /* MAC */
79 mac->ops.init_hw = &ixgbe_init_hw_generic;
80 mac->ops.reset_hw = NULL;
81 mac->ops.start_hw = &ixgbe_start_hw_generic;
82 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
83 mac->ops.get_media_type = NULL;
84 mac->ops.get_supported_physical_layer = NULL;

--- 27 unchanged lines hidden (view full) ---

112 mac->ops.init_uta_tables = NULL;
113
114 /* Flow Control */
115 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
116
117 /* Link */
118 mac->ops.get_link_capabilities = NULL;
119 mac->ops.setup_link = NULL;
81
82 /* MAC */
83 mac->ops.init_hw = &ixgbe_init_hw_generic;
84 mac->ops.reset_hw = NULL;
85 mac->ops.start_hw = &ixgbe_start_hw_generic;
86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
87 mac->ops.get_media_type = NULL;
88 mac->ops.get_supported_physical_layer = NULL;

--- 27 unchanged lines hidden (view full) ---

116 mac->ops.init_uta_tables = NULL;
117
118 /* Flow Control */
119 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
120
121 /* Link */
122 mac->ops.get_link_capabilities = NULL;
123 mac->ops.setup_link = NULL;
120 mac->ops.setup_link_speed = NULL;
121 mac->ops.check_link = NULL;
122
123 return IXGBE_SUCCESS;
124}
125
126/**
127 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
128 * @hw: pointer to hardware structure
129 *
130 * Starts the hardware by filling the bus info structure and media type, clears
131 * all on chip counters, initializes receive address registers, multicast
132 * table, VLAN filter table, calls routine to set up link and flow control
133 * settings, and leaves transmit and receive units disabled and uninitialized
134 **/
135s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
136{
137 u32 ctrl_ext;
138 s32 ret_val = IXGBE_SUCCESS;
139
124 mac->ops.check_link = NULL;
125
126 return IXGBE_SUCCESS;
127}
128
129/**
130 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
131 * @hw: pointer to hardware structure
132 *
133 * Starts the hardware by filling the bus info structure and media type, clears
134 * all on chip counters, initializes receive address registers, multicast
135 * table, VLAN filter table, calls routine to set up link and flow control
136 * settings, and leaves transmit and receive units disabled and uninitialized
137 **/
138s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
139{
140 u32 ctrl_ext;
141 s32 ret_val = IXGBE_SUCCESS;
142
143 DEBUGFUNC("ixgbe_start_hw_generic");
144
140 /* Set the media type */
141 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
142
143 /* PHY ops initialization must be done in reset_hw() */
144
145 /* Clear the VLAN filter table */
146 hw->mac.ops.clear_vfta(hw);
147

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172 * address registers, multicast table, VLAN filter table, calls routine to set
173 * up link and flow control settings, and leaves transmit and receive units
174 * disabled and uninitialized
175 **/
176s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
177{
178 s32 status = IXGBE_SUCCESS;
179
145 /* Set the media type */
146 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
147
148 /* PHY ops initialization must be done in reset_hw() */
149
150 /* Clear the VLAN filter table */
151 hw->mac.ops.clear_vfta(hw);
152

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177 * address registers, multicast table, VLAN filter table, calls routine to set
178 * up link and flow control settings, and leaves transmit and receive units
179 * disabled and uninitialized
180 **/
181s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
182{
183 s32 status = IXGBE_SUCCESS;
184
185 DEBUGFUNC("ixgbe_init_hw_generic");
186
180 /* Reset the hardware */
181 status = hw->mac.ops.reset_hw(hw);
182
183 if (status == IXGBE_SUCCESS) {
184 /* Start the HW */
185 status = hw->mac.ops.start_hw(hw);
186 }
187

--- 6 unchanged lines hidden (view full) ---

194 *
195 * Clears all hardware statistics counters by reading them from the hardware
196 * Statistics counters are clear on read.
197 **/
198s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
199{
200 u16 i = 0;
201
187 /* Reset the hardware */
188 status = hw->mac.ops.reset_hw(hw);
189
190 if (status == IXGBE_SUCCESS) {
191 /* Start the HW */
192 status = hw->mac.ops.start_hw(hw);
193 }
194

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201 *
202 * Clears all hardware statistics counters by reading them from the hardware
203 * Statistics counters are clear on read.
204 **/
205s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
206{
207 u16 i = 0;
208
209 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
210
202 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
203 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
204 IXGBE_READ_REG(hw, IXGBE_ERRBC);
205 IXGBE_READ_REG(hw, IXGBE_MSPDC);
206 for (i = 0; i < 8; i++)
207 IXGBE_READ_REG(hw, IXGBE_MPC(i));
208
209 IXGBE_READ_REG(hw, IXGBE_MLFC);

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319 * in order for the MAC address to have been loaded from the EEPROM into RAR0
320 **/
321s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
322{
323 u32 rar_high;
324 u32 rar_low;
325 u16 i;
326
211 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
212 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
213 IXGBE_READ_REG(hw, IXGBE_ERRBC);
214 IXGBE_READ_REG(hw, IXGBE_MSPDC);
215 for (i = 0; i < 8; i++)
216 IXGBE_READ_REG(hw, IXGBE_MPC(i));
217
218 IXGBE_READ_REG(hw, IXGBE_MLFC);

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328 * in order for the MAC address to have been loaded from the EEPROM into RAR0
329 **/
330s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
331{
332 u32 rar_high;
333 u32 rar_low;
334 u16 i;
335
336 DEBUGFUNC("ixgbe_get_mac_addr_generic");
337
327 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
328 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
329
330 for (i = 0; i < 4; i++)
331 mac_addr[i] = (u8)(rar_low >> (i*8));
332
333 for (i = 0; i < 2; i++)
334 mac_addr[i+4] = (u8)(rar_high >> (i*8));

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342 *
343 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
344 **/
345s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
346{
347 struct ixgbe_mac_info *mac = &hw->mac;
348 u16 link_status;
349
338 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
339 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
340
341 for (i = 0; i < 4; i++)
342 mac_addr[i] = (u8)(rar_low >> (i*8));
343
344 for (i = 0; i < 2; i++)
345 mac_addr[i+4] = (u8)(rar_high >> (i*8));

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353 *
354 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
355 **/
356s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
357{
358 struct ixgbe_mac_info *mac = &hw->mac;
359 u16 link_status;
360
361 DEBUGFUNC("ixgbe_get_bus_info_generic");
362
350 hw->bus.type = ixgbe_bus_type_pci_express;
351
352 /* Get the negotiated link width and speed from PCI config space */
353 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
354
355 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
356 case IXGBE_PCI_LINK_WIDTH_1:
357 hw->bus.width = ixgbe_bus_width_pcie_x1;

--- 36 unchanged lines hidden (view full) ---

394 * Determines the LAN function id by reading memory-mapped registers
395 * and swaps the port value if requested.
396 **/
397void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
398{
399 struct ixgbe_bus_info *bus = &hw->bus;
400 u32 reg;
401
363 hw->bus.type = ixgbe_bus_type_pci_express;
364
365 /* Get the negotiated link width and speed from PCI config space */
366 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
367
368 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
369 case IXGBE_PCI_LINK_WIDTH_1:
370 hw->bus.width = ixgbe_bus_width_pcie_x1;

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407 * Determines the LAN function id by reading memory-mapped registers
408 * and swaps the port value if requested.
409 **/
410void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
411{
412 struct ixgbe_bus_info *bus = &hw->bus;
413 u32 reg;
414
415 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
416
402 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
403 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
404 bus->lan_id = bus->func;
405
406 /* check for a port swap */
407 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
408 if (reg & IXGBE_FACTPS_LFS)
409 bus->func ^= 0x1;

--- 9 unchanged lines hidden (view full) ---

419 * state and should not touch the hardware.
420 **/
421s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
422{
423 u32 number_of_queues;
424 u32 reg_val;
425 u16 i;
426
417 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
418 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
419 bus->lan_id = bus->func;
420
421 /* check for a port swap */
422 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
423 if (reg & IXGBE_FACTPS_LFS)
424 bus->func ^= 0x1;

--- 9 unchanged lines hidden (view full) ---

434 * state and should not touch the hardware.
435 **/
436s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
437{
438 u32 number_of_queues;
439 u32 reg_val;
440 u16 i;
441
442 DEBUGFUNC("ixgbe_stop_adapter_generic");
443
427 /*
428 * Set the adapter_stopped flag so other driver functions stop touching
429 * the hardware
430 */
431 hw->adapter_stopped = TRUE;
432
433 /* Disable the receive unit */
434 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);

--- 32 unchanged lines hidden (view full) ---

467 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
468 * @hw: pointer to hardware structure
469 * @index: led number to turn on
470 **/
471s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
472{
473 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
474
444 /*
445 * Set the adapter_stopped flag so other driver functions stop touching
446 * the hardware
447 */
448 hw->adapter_stopped = TRUE;
449
450 /* Disable the receive unit */
451 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);

--- 32 unchanged lines hidden (view full) ---

484 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
485 * @hw: pointer to hardware structure
486 * @index: led number to turn on
487 **/
488s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
489{
490 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
491
492 DEBUGFUNC("ixgbe_led_on_generic");
493
475 /* To turn on the LED, set mode to ON. */
476 led_reg &= ~IXGBE_LED_MODE_MASK(index);
477 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
478 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
479 IXGBE_WRITE_FLUSH(hw);
480
481 return IXGBE_SUCCESS;
482}
483
484/**
485 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
486 * @hw: pointer to hardware structure
487 * @index: led number to turn off
488 **/
489s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
490{
491 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
492
494 /* To turn on the LED, set mode to ON. */
495 led_reg &= ~IXGBE_LED_MODE_MASK(index);
496 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
497 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
498 IXGBE_WRITE_FLUSH(hw);
499
500 return IXGBE_SUCCESS;
501}
502
503/**
504 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
505 * @hw: pointer to hardware structure
506 * @index: led number to turn off
507 **/
508s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
509{
510 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
511
512 DEBUGFUNC("ixgbe_led_off_generic");
513
493 /* To turn off the LED, set mode to OFF. */
494 led_reg &= ~IXGBE_LED_MODE_MASK(index);
495 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
496 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
497 IXGBE_WRITE_FLUSH(hw);
498
499 return IXGBE_SUCCESS;
500}

--- 6 unchanged lines hidden (view full) ---

507 * ixgbe_hw struct in order to set up EEPROM access.
508 **/
509s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
510{
511 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
512 u32 eec;
513 u16 eeprom_size;
514
514 /* To turn off the LED, set mode to OFF. */
515 led_reg &= ~IXGBE_LED_MODE_MASK(index);
516 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
517 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
518 IXGBE_WRITE_FLUSH(hw);
519
520 return IXGBE_SUCCESS;
521}

--- 6 unchanged lines hidden (view full) ---

528 * ixgbe_hw struct in order to set up EEPROM access.
529 **/
530s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
531{
532 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
533 u32 eec;
534 u16 eeprom_size;
535
536 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
537
515 if (eeprom->type == ixgbe_eeprom_uninitialized) {
516 eeprom->type = ixgbe_eeprom_none;
517 /* Set default semaphore delay to 10ms which is a well
518 * tested value */
519 eeprom->semaphore_delay = 10;
520
521 /*
522 * Check for EEPROM present first.

--- 5 unchanged lines hidden (view full) ---

528
529 /*
530 * SPI EEPROM is assumed here. This code would need to
531 * change if a future EEPROM is not SPI.
532 */
533 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
534 IXGBE_EEC_SIZE_SHIFT);
535 eeprom->word_size = 1 << (eeprom_size +
538 if (eeprom->type == ixgbe_eeprom_uninitialized) {
539 eeprom->type = ixgbe_eeprom_none;
540 /* Set default semaphore delay to 10ms which is a well
541 * tested value */
542 eeprom->semaphore_delay = 10;
543
544 /*
545 * Check for EEPROM present first.

--- 5 unchanged lines hidden (view full) ---

551
552 /*
553 * SPI EEPROM is assumed here. This code would need to
554 * change if a future EEPROM is not SPI.
555 */
556 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
557 IXGBE_EEC_SIZE_SHIFT);
558 eeprom->word_size = 1 << (eeprom_size +
536 IXGBE_EEPROM_WORD_SIZE_SHIFT);
559 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT);
537 }
538
539 if (eec & IXGBE_EEC_ADDR_SIZE)
540 eeprom->address_bits = 16;
541 else
542 eeprom->address_bits = 8;
543 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
544 "%d\n", eeprom->type, eeprom->word_size,

--- 12 unchanged lines hidden (view full) ---

557 * If ixgbe_eeprom_update_checksum is not called after this function, the
558 * EEPROM will most likely contain an invalid checksum.
559 **/
560s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
561{
562 s32 status;
563 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
564
560 }
561
562 if (eec & IXGBE_EEC_ADDR_SIZE)
563 eeprom->address_bits = 16;
564 else
565 eeprom->address_bits = 8;
566 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
567 "%d\n", eeprom->type, eeprom->word_size,

--- 12 unchanged lines hidden (view full) ---

580 * If ixgbe_eeprom_update_checksum is not called after this function, the
581 * EEPROM will most likely contain an invalid checksum.
582 **/
583s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
584{
585 s32 status;
586 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
587
588 DEBUGFUNC("ixgbe_write_eeprom_generic");
589
565 hw->eeprom.ops.init_params(hw);
566
567 if (offset >= hw->eeprom.word_size) {
568 status = IXGBE_ERR_EEPROM;
569 goto out;
570 }
571
572 /* Prepare the EEPROM for writing */

--- 51 unchanged lines hidden (view full) ---

624 **/
625s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
626 u16 *data)
627{
628 s32 status;
629 u16 word_in;
630 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
631
590 hw->eeprom.ops.init_params(hw);
591
592 if (offset >= hw->eeprom.word_size) {
593 status = IXGBE_ERR_EEPROM;
594 goto out;
595 }
596
597 /* Prepare the EEPROM for writing */

--- 51 unchanged lines hidden (view full) ---

649 **/
650s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
651 u16 *data)
652{
653 s32 status;
654 u16 word_in;
655 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
656
657 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
658
632 hw->eeprom.ops.init_params(hw);
633
634 if (offset >= hw->eeprom.word_size) {
635 status = IXGBE_ERR_EEPROM;
636 goto out;
637 }
638
639 /* Prepare the EEPROM for reading */

--- 30 unchanged lines hidden (view full) ---

670 ixgbe_release_eeprom(hw);
671 }
672
673out:
674 return status;
675}
676
677/**
659 hw->eeprom.ops.init_params(hw);
660
661 if (offset >= hw->eeprom.word_size) {
662 status = IXGBE_ERR_EEPROM;
663 goto out;
664 }
665
666 /* Prepare the EEPROM for reading */

--- 30 unchanged lines hidden (view full) ---

697 ixgbe_release_eeprom(hw);
698 }
699
700out:
701 return status;
702}
703
704/**
678 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
705 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
679 * @hw: pointer to hardware structure
680 * @offset: offset of word in the EEPROM to read
681 * @data: word read from the EEPROM
682 *
683 * Reads a 16 bit word from the EEPROM using the EERD register.
684 **/
706 * @hw: pointer to hardware structure
707 * @offset: offset of word in the EEPROM to read
708 * @data: word read from the EEPROM
709 *
710 * Reads a 16 bit word from the EEPROM using the EERD register.
711 **/
685s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
712s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
686{
687 u32 eerd;
688 s32 status;
689
713{
714 u32 eerd;
715 s32 status;
716
717 DEBUGFUNC("ixgbe_read_eerd_generic");
718
690 hw->eeprom.ops.init_params(hw);
691
692 if (offset >= hw->eeprom.word_size) {
693 status = IXGBE_ERR_EEPROM;
694 goto out;
695 }
696
719 hw->eeprom.ops.init_params(hw);
720
721 if (offset >= hw->eeprom.word_size) {
722 status = IXGBE_ERR_EEPROM;
723 goto out;
724 }
725
697 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
698 IXGBE_EEPROM_READ_REG_START;
726 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
727 IXGBE_EEPROM_RW_REG_START;
699
700 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
728
729 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
701 status = ixgbe_poll_eeprom_eerd_done(hw);
730 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
702
703 if (status == IXGBE_SUCCESS)
704 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
731
732 if (status == IXGBE_SUCCESS)
733 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
705 IXGBE_EEPROM_READ_REG_DATA);
734 IXGBE_EEPROM_RW_REG_DATA);
706 else
707 DEBUGOUT("Eeprom read timed out\n");
708
709out:
710 return status;
711}
712
713/**
735 else
736 DEBUGOUT("Eeprom read timed out\n");
737
738out:
739 return status;
740}
741
742/**
714 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
743 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
715 * @hw: pointer to hardware structure
744 * @hw: pointer to hardware structure
745 * @ee_reg: EEPROM flag for polling
716 *
746 *
717 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
747 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
748 * read or write is done respectively.
718 **/
749 **/
719static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
750s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
720{
721 u32 i;
722 u32 reg;
723 s32 status = IXGBE_ERR_EEPROM;
724
751{
752 u32 i;
753 u32 reg;
754 s32 status = IXGBE_ERR_EEPROM;
755
725 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
726 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
727 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
756 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
757
758 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
759 if (ee_reg == IXGBE_NVM_POLL_READ)
760 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
761 else
762 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
763
764 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
728 status = IXGBE_SUCCESS;
729 break;
730 }
731 usec_delay(5);
732 }
733 return status;
734}
735

--- 5 unchanged lines hidden (view full) ---

741 * be called before issuing a command to the EEPROM.
742 **/
743static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
744{
745 s32 status = IXGBE_SUCCESS;
746 u32 eec;
747 u32 i;
748
765 status = IXGBE_SUCCESS;
766 break;
767 }
768 usec_delay(5);
769 }
770 return status;
771}
772

--- 5 unchanged lines hidden (view full) ---

778 * be called before issuing a command to the EEPROM.
779 **/
780static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
781{
782 s32 status = IXGBE_SUCCESS;
783 u32 eec;
784 u32 i;
785
786 DEBUGFUNC("ixgbe_acquire_eeprom");
787
749 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
750 status = IXGBE_ERR_SWFW_SYNC;
751
752 if (status == IXGBE_SUCCESS) {
753 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
754
755 /* Request EEPROM Access */
756 eec |= IXGBE_EEC_REQ;

--- 36 unchanged lines hidden (view full) ---

793 **/
794static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
795{
796 s32 status = IXGBE_ERR_EEPROM;
797 u32 timeout = 2000;
798 u32 i;
799 u32 swsm;
800
788 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
789 status = IXGBE_ERR_SWFW_SYNC;
790
791 if (status == IXGBE_SUCCESS) {
792 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
793
794 /* Request EEPROM Access */
795 eec |= IXGBE_EEC_REQ;

--- 36 unchanged lines hidden (view full) ---

832 **/
833static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
834{
835 s32 status = IXGBE_ERR_EEPROM;
836 u32 timeout = 2000;
837 u32 i;
838 u32 swsm;
839
840 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
841
801 /* Get SMBI software semaphore between device drivers first */
802 for (i = 0; i < timeout; i++) {
803 /*
804 * If the SMBI bit is 0 when we read it, then the bit will be
805 * set and we have the semaphore
806 */
807 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
808 if (!(swsm & IXGBE_SWSM_SMBI)) {

--- 46 unchanged lines hidden (view full) ---

855 * @hw: pointer to hardware structure
856 *
857 * This function clears hardware semaphore bits.
858 **/
859static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
860{
861 u32 swsm;
862
842 /* Get SMBI software semaphore between device drivers first */
843 for (i = 0; i < timeout; i++) {
844 /*
845 * If the SMBI bit is 0 when we read it, then the bit will be
846 * set and we have the semaphore
847 */
848 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
849 if (!(swsm & IXGBE_SWSM_SMBI)) {

--- 46 unchanged lines hidden (view full) ---

896 * @hw: pointer to hardware structure
897 *
898 * This function clears hardware semaphore bits.
899 **/
900static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
901{
902 u32 swsm;
903
904 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
905
863 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
864
865 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
866 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
867 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
868 IXGBE_WRITE_FLUSH(hw);
869}
870
871/**
872 * ixgbe_ready_eeprom - Polls for EEPROM ready
873 * @hw: pointer to hardware structure
874 **/
875static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
876{
877 s32 status = IXGBE_SUCCESS;
878 u16 i;
879 u8 spi_stat_reg;
880
906 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
907
908 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
909 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
910 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
911 IXGBE_WRITE_FLUSH(hw);
912}
913
914/**
915 * ixgbe_ready_eeprom - Polls for EEPROM ready
916 * @hw: pointer to hardware structure
917 **/
918static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
919{
920 s32 status = IXGBE_SUCCESS;
921 u16 i;
922 u8 spi_stat_reg;
923
924 DEBUGFUNC("ixgbe_ready_eeprom");
925
881 /*
882 * Read "Status Register" repeatedly until the LSB is cleared. The
883 * EEPROM will signal that the command has been completed by clearing
884 * bit 0 of the internal status register. If it's not cleared within
885 * 5 milliseconds, then error out.
886 */
887 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
888 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,

--- 21 unchanged lines hidden (view full) ---

910/**
911 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
912 * @hw: pointer to hardware structure
913 **/
914static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
915{
916 u32 eec;
917
926 /*
927 * Read "Status Register" repeatedly until the LSB is cleared. The
928 * EEPROM will signal that the command has been completed by clearing
929 * bit 0 of the internal status register. If it's not cleared within
930 * 5 milliseconds, then error out.
931 */
932 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
933 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,

--- 21 unchanged lines hidden (view full) ---

955/**
956 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
957 * @hw: pointer to hardware structure
958 **/
959static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
960{
961 u32 eec;
962
963 DEBUGFUNC("ixgbe_standby_eeprom");
964
918 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
919
920 /* Toggle CS to flush commands */
921 eec |= IXGBE_EEC_CS;
922 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
923 IXGBE_WRITE_FLUSH(hw);
924 usec_delay(1);
925 eec &= ~IXGBE_EEC_CS;

--- 10 unchanged lines hidden (view full) ---

936 **/
937static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
938 u16 count)
939{
940 u32 eec;
941 u32 mask;
942 u32 i;
943
965 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
966
967 /* Toggle CS to flush commands */
968 eec |= IXGBE_EEC_CS;
969 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
970 IXGBE_WRITE_FLUSH(hw);
971 usec_delay(1);
972 eec &= ~IXGBE_EEC_CS;

--- 10 unchanged lines hidden (view full) ---

983 **/
984static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
985 u16 count)
986{
987 u32 eec;
988 u32 mask;
989 u32 i;
990
991 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
992
944 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
945
946 /*
947 * Mask is used to shift "count" bits of "data" out to the EEPROM
948 * one bit at a time. Determine the starting bit based on count
949 */
950 mask = 0x01 << (count - 1);
951

--- 36 unchanged lines hidden (view full) ---

988 * @hw: pointer to hardware structure
989 **/
990static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
991{
992 u32 eec;
993 u32 i;
994 u16 data = 0;
995
993 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
994
995 /*
996 * Mask is used to shift "count" bits of "data" out to the EEPROM
997 * one bit at a time. Determine the starting bit based on count
998 */
999 mask = 0x01 << (count - 1);
1000

--- 36 unchanged lines hidden (view full) ---

1037 * @hw: pointer to hardware structure
1038 **/
1039static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1040{
1041 u32 eec;
1042 u32 i;
1043 u16 data = 0;
1044
1045 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1046
996 /*
997 * In order to read a register from the EEPROM, we need to shift
998 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
999 * the clock input to the EEPROM (setting the SK bit), and then reading
1000 * the value of the "DO" bit. During this "shifting in" process the
1001 * "DI" bit should always be clear.
1002 */
1003 eec = IXGBE_READ_REG(hw, IXGBE_EEC);

--- 18 unchanged lines hidden (view full) ---

1022
1023/**
1024 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1025 * @hw: pointer to hardware structure
1026 * @eec: EEC register's current value
1027 **/
1028static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1029{
1047 /*
1048 * In order to read a register from the EEPROM, we need to shift
1049 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1050 * the clock input to the EEPROM (setting the SK bit), and then reading
1051 * the value of the "DO" bit. During this "shifting in" process the
1052 * "DI" bit should always be clear.
1053 */
1054 eec = IXGBE_READ_REG(hw, IXGBE_EEC);

--- 18 unchanged lines hidden (view full) ---

1073
1074/**
1075 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1076 * @hw: pointer to hardware structure
1077 * @eec: EEC register's current value
1078 **/
1079static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1080{
1081 DEBUGFUNC("ixgbe_raise_eeprom_clk");
1082
1030 /*
1031 * Raise the clock input to the EEPROM
1032 * (setting the SK bit), then delay
1033 */
1034 *eec = *eec | IXGBE_EEC_SK;
1035 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1036 IXGBE_WRITE_FLUSH(hw);
1037 usec_delay(1);
1038}
1039
1040/**
1041 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1042 * @hw: pointer to hardware structure
1043 * @eecd: EECD's current value
1044 **/
1045static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1046{
1083 /*
1084 * Raise the clock input to the EEPROM
1085 * (setting the SK bit), then delay
1086 */
1087 *eec = *eec | IXGBE_EEC_SK;
1088 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1089 IXGBE_WRITE_FLUSH(hw);
1090 usec_delay(1);
1091}
1092
1093/**
1094 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1095 * @hw: pointer to hardware structure
1096 * @eecd: EECD's current value
1097 **/
1098static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1099{
1100 DEBUGFUNC("ixgbe_lower_eeprom_clk");
1101
1047 /*
1048 * Lower the clock input to the EEPROM (clearing the SK bit), then
1049 * delay
1050 */
1051 *eec = *eec & ~IXGBE_EEC_SK;
1052 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1053 IXGBE_WRITE_FLUSH(hw);
1054 usec_delay(1);
1055}
1056
1057/**
1058 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1059 * @hw: pointer to hardware structure
1060 **/
1061static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1062{
1063 u32 eec;
1064
1102 /*
1103 * Lower the clock input to the EEPROM (clearing the SK bit), then
1104 * delay
1105 */
1106 *eec = *eec & ~IXGBE_EEC_SK;
1107 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1108 IXGBE_WRITE_FLUSH(hw);
1109 usec_delay(1);
1110}
1111
1112/**
1113 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1114 * @hw: pointer to hardware structure
1115 **/
1116static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1117{
1118 u32 eec;
1119
1120 DEBUGFUNC("ixgbe_release_eeprom");
1121
1065 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1066
1067 eec |= IXGBE_EEC_CS; /* Pull CS high */
1068 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1069
1070 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1071 IXGBE_WRITE_FLUSH(hw);
1072

--- 5 unchanged lines hidden (view full) ---

1078
1079 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1080
1081 /* Delay before attempt to obtain semaphore again to allow FW access */
1082 msec_delay(hw->eeprom.semaphore_delay);
1083}
1084
1085/**
1122 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1123
1124 eec |= IXGBE_EEC_CS; /* Pull CS high */
1125 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1126
1127 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1128 IXGBE_WRITE_FLUSH(hw);
1129

--- 5 unchanged lines hidden (view full) ---

1135
1136 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1137
1138 /* Delay before attempt to obtain semaphore again to allow FW access */
1139 msec_delay(hw->eeprom.semaphore_delay);
1140}
1141
1142/**
1086 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1143 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1087 * @hw: pointer to hardware structure
1088 **/
1144 * @hw: pointer to hardware structure
1145 **/
1089static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1146u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1090{
1091 u16 i;
1092 u16 j;
1093 u16 checksum = 0;
1094 u16 length = 0;
1095 u16 pointer = 0;
1096 u16 word = 0;
1097
1147{
1148 u16 i;
1149 u16 j;
1150 u16 checksum = 0;
1151 u16 length = 0;
1152 u16 pointer = 0;
1153 u16 word = 0;
1154
1155 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1156
1098 /* Include 0x0-0x3F in the checksum */
1099 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1100 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
1101 DEBUGOUT("EEPROM read failed\n");
1102 break;
1103 }
1104 checksum += word;
1105 }

--- 30 unchanged lines hidden (view full) ---

1136 **/
1137s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1138 u16 *checksum_val)
1139{
1140 s32 status;
1141 u16 checksum;
1142 u16 read_checksum = 0;
1143
1157 /* Include 0x0-0x3F in the checksum */
1158 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1159 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
1160 DEBUGOUT("EEPROM read failed\n");
1161 break;
1162 }
1163 checksum += word;
1164 }

--- 30 unchanged lines hidden (view full) ---

1195 **/
1196s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1197 u16 *checksum_val)
1198{
1199 s32 status;
1200 u16 checksum;
1201 u16 read_checksum = 0;
1202
1203 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
1204
1144 /*
1145 * Read the first word from the EEPROM. If this times out or fails, do
1146 * not continue or we could be in for a very long wait while every
1147 * EEPROM read fails
1148 */
1149 status = hw->eeprom.ops.read(hw, 0, &checksum);
1150
1151 if (status == IXGBE_SUCCESS) {
1205 /*
1206 * Read the first word from the EEPROM. If this times out or fails, do
1207 * not continue or we could be in for a very long wait while every
1208 * EEPROM read fails
1209 */
1210 status = hw->eeprom.ops.read(hw, 0, &checksum);
1211
1212 if (status == IXGBE_SUCCESS) {
1152 checksum = ixgbe_calc_eeprom_checksum(hw);
1213 checksum = hw->eeprom.ops.calc_checksum(hw);
1153
1154 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1155
1156 /*
1157 * Verify read checksum from EEPROM is the same as
1158 * calculated checksum
1159 */
1160 if (read_checksum != checksum)

--- 13 unchanged lines hidden (view full) ---

1174 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1175 * @hw: pointer to hardware structure
1176 **/
1177s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1178{
1179 s32 status;
1180 u16 checksum;
1181
1214
1215 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1216
1217 /*
1218 * Verify read checksum from EEPROM is the same as
1219 * calculated checksum
1220 */
1221 if (read_checksum != checksum)

--- 13 unchanged lines hidden (view full) ---

1235 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1236 * @hw: pointer to hardware structure
1237 **/
1238s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1239{
1240 s32 status;
1241 u16 checksum;
1242
1243 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
1244
1182 /*
1183 * Read the first word from the EEPROM. If this times out or fails, do
1184 * not continue or we could be in for a very long wait while every
1185 * EEPROM read fails
1186 */
1187 status = hw->eeprom.ops.read(hw, 0, &checksum);
1188
1189 if (status == IXGBE_SUCCESS) {
1245 /*
1246 * Read the first word from the EEPROM. If this times out or fails, do
1247 * not continue or we could be in for a very long wait while every
1248 * EEPROM read fails
1249 */
1250 status = hw->eeprom.ops.read(hw, 0, &checksum);
1251
1252 if (status == IXGBE_SUCCESS) {
1190 checksum = ixgbe_calc_eeprom_checksum(hw);
1253 checksum = hw->eeprom.ops.calc_checksum(hw);
1191 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1192 checksum);
1193 } else {
1194 DEBUGOUT("EEPROM read failed\n");
1195 }
1196
1197 return status;
1198}
1199
1200/**
1201 * ixgbe_validate_mac_addr - Validate MAC address
1202 * @mac_addr: pointer to MAC address.
1203 *
1204 * Tests a MAC address to ensure it is a valid Individual Address
1205 **/
1206s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1207{
1208 s32 status = IXGBE_SUCCESS;
1209
1254 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1255 checksum);
1256 } else {
1257 DEBUGOUT("EEPROM read failed\n");
1258 }
1259
1260 return status;
1261}
1262
1263/**
1264 * ixgbe_validate_mac_addr - Validate MAC address
1265 * @mac_addr: pointer to MAC address.
1266 *
1267 * Tests a MAC address to ensure it is a valid Individual Address
1268 **/
1269s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1270{
1271 s32 status = IXGBE_SUCCESS;
1272
1273 DEBUGFUNC("ixgbe_validate_mac_addr");
1274
1210 /* Make sure it is not a multicast address */
1211 if (IXGBE_IS_MULTICAST(mac_addr)) {
1212 DEBUGOUT("MAC address is multicast\n");
1213 status = IXGBE_ERR_INVALID_MAC_ADDR;
1214 /* Not a broadcast address */
1215 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1216 DEBUGOUT("MAC address is broadcast\n");
1217 status = IXGBE_ERR_INVALID_MAC_ADDR;

--- 17 unchanged lines hidden (view full) ---

1235 * Puts an ethernet address into a receive address register.
1236 **/
1237s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1238 u32 enable_addr)
1239{
1240 u32 rar_low, rar_high;
1241 u32 rar_entries = hw->mac.num_rar_entries;
1242
1275 /* Make sure it is not a multicast address */
1276 if (IXGBE_IS_MULTICAST(mac_addr)) {
1277 DEBUGOUT("MAC address is multicast\n");
1278 status = IXGBE_ERR_INVALID_MAC_ADDR;
1279 /* Not a broadcast address */
1280 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1281 DEBUGOUT("MAC address is broadcast\n");
1282 status = IXGBE_ERR_INVALID_MAC_ADDR;

--- 17 unchanged lines hidden (view full) ---

1300 * Puts an ethernet address into a receive address register.
1301 **/
1302s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1303 u32 enable_addr)
1304{
1305 u32 rar_low, rar_high;
1306 u32 rar_entries = hw->mac.num_rar_entries;
1307
1308 DEBUGFUNC("ixgbe_set_rar_generic");
1309
1243 /* setup VMDq pool selection before this RAR gets enabled */
1244 hw->mac.ops.set_vmdq(hw, index, vmdq);
1245
1246 /* Make sure we are using a valid rar index range */
1247 if (index < rar_entries) {
1248 /*
1249 * HW expects these in little endian so we reverse the byte
1250 * order from network order (big endian) to little endian

--- 30 unchanged lines hidden (view full) ---

1281 *
1282 * Clears an ethernet address from a receive address register.
1283 **/
1284s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1285{
1286 u32 rar_high;
1287 u32 rar_entries = hw->mac.num_rar_entries;
1288
1310 /* setup VMDq pool selection before this RAR gets enabled */
1311 hw->mac.ops.set_vmdq(hw, index, vmdq);
1312
1313 /* Make sure we are using a valid rar index range */
1314 if (index < rar_entries) {
1315 /*
1316 * HW expects these in little endian so we reverse the byte
1317 * order from network order (big endian) to little endian

--- 30 unchanged lines hidden (view full) ---

1348 *
1349 * Clears an ethernet address from a receive address register.
1350 **/
1351s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1352{
1353 u32 rar_high;
1354 u32 rar_entries = hw->mac.num_rar_entries;
1355
1356 DEBUGFUNC("ixgbe_clear_rar_generic");
1357
1289 /* Make sure we are using a valid rar index range */
1290 if (index < rar_entries) {
1291 /*
1292 * Some parts put the VMDq setting in the extra RAH bits,
1293 * so save everything except the lower 16 bits that hold part
1294 * of the address and the address valid bit.
1295 */
1296 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));

--- 19 unchanged lines hidden (view full) ---

1316 * of the receive address registers. Clears the multicast table. Assumes
1317 * the receiver is in reset when the routine is called.
1318 **/
1319s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1320{
1321 u32 i;
1322 u32 rar_entries = hw->mac.num_rar_entries;
1323
1358 /* Make sure we are using a valid rar index range */
1359 if (index < rar_entries) {
1360 /*
1361 * Some parts put the VMDq setting in the extra RAH bits,
1362 * so save everything except the lower 16 bits that hold part
1363 * of the address and the address valid bit.
1364 */
1365 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));

--- 19 unchanged lines hidden (view full) ---

1385 * of the receive address registers. Clears the multicast table. Assumes
1386 * the receiver is in reset when the routine is called.
1387 **/
1388s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1389{
1390 u32 i;
1391 u32 rar_entries = hw->mac.num_rar_entries;
1392
1393 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
1394
1324 /*
1325 * If the current mac address is valid, assume it is a software override
1326 * to the permanent address.
1327 * Otherwise, use the permanent address from the eeprom.
1328 */
1329 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1330 IXGBE_ERR_INVALID_MAC_ADDR) {
1331 /* Get the MAC address from the RAR0 for later reference */

--- 46 unchanged lines hidden (view full) ---

1378 *
1379 * Adds it to unused receive address register or goes into promiscuous mode.
1380 **/
1381void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1382{
1383 u32 rar_entries = hw->mac.num_rar_entries;
1384 u32 rar;
1385
1395 /*
1396 * If the current mac address is valid, assume it is a software override
1397 * to the permanent address.
1398 * Otherwise, use the permanent address from the eeprom.
1399 */
1400 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1401 IXGBE_ERR_INVALID_MAC_ADDR) {
1402 /* Get the MAC address from the RAR0 for later reference */

--- 46 unchanged lines hidden (view full) ---

1449 *
1450 * Adds it to unused receive address register or goes into promiscuous mode.
1451 **/
1452void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1453{
1454 u32 rar_entries = hw->mac.num_rar_entries;
1455 u32 rar;
1456
1457 DEBUGFUNC("ixgbe_add_uc_addr");
1458
1386 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1387 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1388
1389 /*
1390 * Place this address in the RAR if there is room,
1391 * else put the controller into promiscuous mode
1392 */
1393 if (hw->addr_ctrl.rar_used_count < rar_entries) {

--- 27 unchanged lines hidden (view full) ---

1421{
1422 u8 *addr;
1423 u32 i;
1424 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1425 u32 uc_addr_in_use;
1426 u32 fctrl;
1427 u32 vmdq;
1428
1459 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1460 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1461
1462 /*
1463 * Place this address in the RAR if there is room,
1464 * else put the controller into promiscuous mode
1465 */
1466 if (hw->addr_ctrl.rar_used_count < rar_entries) {

--- 27 unchanged lines hidden (view full) ---

1494{
1495 u8 *addr;
1496 u32 i;
1497 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1498 u32 uc_addr_in_use;
1499 u32 fctrl;
1500 u32 vmdq;
1501
1502 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
1503
1429 /*
1430 * Clear accounting of old secondary address list,
1431 * don't count RAR[0]
1432 */
1433 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1434 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1435 hw->addr_ctrl.overflow_promisc = 0;
1436
1437 /* Zero out the other receive addresses */
1504 /*
1505 * Clear accounting of old secondary address list,
1506 * don't count RAR[0]
1507 */
1508 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1509 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1510 hw->addr_ctrl.overflow_promisc = 0;
1511
1512 /* Zero out the other receive addresses */
1438 DEBUGOUT1("Clearing RAR[1-%d]\n", hw->addr_ctrl.rar_used_count);
1439 for (i = 1; i <= hw->addr_ctrl.rar_used_count; i++) {
1440 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1441 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1513 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
1514 for (i = 0; i < uc_addr_in_use; i++) {
1515 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1516 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
1442 }
1443
1444 /* Add the new addresses */
1445 for (i = 0; i < addr_count; i++) {
1446 DEBUGOUT(" Adding the secondary addresses:\n");
1447 addr = next(hw, &addr_list, &vmdq);
1448 ixgbe_add_uc_addr(hw, addr, vmdq);
1449 }

--- 31 unchanged lines hidden (view full) ---

1481 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1482 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1483 * to mc_filter_type.
1484 **/
1485static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1486{
1487 u32 vector = 0;
1488
1517 }
1518
1519 /* Add the new addresses */
1520 for (i = 0; i < addr_count; i++) {
1521 DEBUGOUT(" Adding the secondary addresses:\n");
1522 addr = next(hw, &addr_list, &vmdq);
1523 ixgbe_add_uc_addr(hw, addr, vmdq);
1524 }

--- 31 unchanged lines hidden (view full) ---

1556 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1557 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1558 * to mc_filter_type.
1559 **/
1560static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1561{
1562 u32 vector = 0;
1563
1564 DEBUGFUNC("ixgbe_mta_vector");
1565
1489 switch (hw->mac.mc_filter_type) {
1490 case 0: /* use bits [47:36] of the address */
1491 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1492 break;
1493 case 1: /* use bits [46:35] of the address */
1494 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1495 break;
1496 case 2: /* use bits [45:34] of the address */

--- 22 unchanged lines hidden (view full) ---

1519 **/
1520void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1521{
1522 u32 vector;
1523 u32 vector_bit;
1524 u32 vector_reg;
1525 u32 mta_reg;
1526
1566 switch (hw->mac.mc_filter_type) {
1567 case 0: /* use bits [47:36] of the address */
1568 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1569 break;
1570 case 1: /* use bits [46:35] of the address */
1571 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1572 break;
1573 case 2: /* use bits [45:34] of the address */

--- 22 unchanged lines hidden (view full) ---

1596 **/
1597void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1598{
1599 u32 vector;
1600 u32 vector_bit;
1601 u32 vector_reg;
1602 u32 mta_reg;
1603
1604 DEBUGFUNC("ixgbe_set_mta");
1605
1527 hw->addr_ctrl.mta_in_use++;
1528
1529 vector = ixgbe_mta_vector(hw, mc_addr);
1530 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
1531
1532 /*
1533 * The MTA is a register array of 128 32-bit registers. It is treated
1534 * like an array of 4096 bits. We want to set bit

--- 23 unchanged lines hidden (view full) ---

1558 * multicast table.
1559 **/
1560s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1561 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1562{
1563 u32 i;
1564 u32 vmdq;
1565
1606 hw->addr_ctrl.mta_in_use++;
1607
1608 vector = ixgbe_mta_vector(hw, mc_addr);
1609 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
1610
1611 /*
1612 * The MTA is a register array of 128 32-bit registers. It is treated
1613 * like an array of 4096 bits. We want to set bit

--- 23 unchanged lines hidden (view full) ---

1637 * multicast table.
1638 **/
1639s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1640 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1641{
1642 u32 i;
1643 u32 vmdq;
1644
1645 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
1646
1566 /*
1567 * Set the new number of MC addresses that we are being requested to
1568 * use.
1569 */
1570 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1571 hw->addr_ctrl.mta_in_use = 0;
1572
1573 /* Clear the MTA */

--- 21 unchanged lines hidden (view full) ---

1595 * @hw: pointer to hardware structure
1596 *
1597 * Enables multicast address in RAR and the use of the multicast hash table.
1598 **/
1599s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1600{
1601 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1602
1647 /*
1648 * Set the new number of MC addresses that we are being requested to
1649 * use.
1650 */
1651 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1652 hw->addr_ctrl.mta_in_use = 0;
1653
1654 /* Clear the MTA */

--- 21 unchanged lines hidden (view full) ---

1676 * @hw: pointer to hardware structure
1677 *
1678 * Enables multicast address in RAR and the use of the multicast hash table.
1679 **/
1680s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1681{
1682 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1683
1684 DEBUGFUNC("ixgbe_enable_mc_generic");
1685
1603 if (a->mta_in_use > 0)
1604 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1605 hw->mac.mc_filter_type);
1606
1607 return IXGBE_SUCCESS;
1608}
1609
1610/**
1611 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1612 * @hw: pointer to hardware structure
1613 *
1614 * Disables multicast address in RAR and the use of the multicast hash table.
1615 **/
1616s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1617{
1618 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1619
1686 if (a->mta_in_use > 0)
1687 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1688 hw->mac.mc_filter_type);
1689
1690 return IXGBE_SUCCESS;
1691}
1692
1693/**
1694 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1695 * @hw: pointer to hardware structure
1696 *
1697 * Disables multicast address in RAR and the use of the multicast hash table.
1698 **/
1699s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1700{
1701 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1702
1703 DEBUGFUNC("ixgbe_disable_mc_generic");
1704
1620 if (a->mta_in_use > 0)
1621 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1622
1623 return IXGBE_SUCCESS;
1624}
1625
1626/**
1627 * ixgbe_fc_enable_generic - Enable flow control

--- 59 unchanged lines hidden (view full) ---

1687 break;
1688 case ixgbe_fc_full:
1689 /* Flow control (both Rx and Tx) is enabled by SW override. */
1690 mflcn_reg |= IXGBE_MFLCN_RFCE;
1691 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1692 break;
1693 default:
1694 DEBUGOUT("Flow control param set incorrectly\n");
1705 if (a->mta_in_use > 0)
1706 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1707
1708 return IXGBE_SUCCESS;
1709}
1710
1711/**
1712 * ixgbe_fc_enable_generic - Enable flow control

--- 59 unchanged lines hidden (view full) ---

1772 break;
1773 case ixgbe_fc_full:
1774 /* Flow control (both Rx and Tx) is enabled by SW override. */
1775 mflcn_reg |= IXGBE_MFLCN_RFCE;
1776 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1777 break;
1778 default:
1779 DEBUGOUT("Flow control param set incorrectly\n");
1695 ret_val = -IXGBE_ERR_CONFIG;
1780 ret_val = IXGBE_ERR_CONFIG;
1696 goto out;
1697 break;
1698 }
1699
1700 /* Set 802.3x based flow control settings. */
1701 mflcn_reg |= IXGBE_MFLCN_DPF;
1702 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1703 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);

--- 52 unchanged lines hidden (view full) ---

1756 * Compares our advertised flow control capabilities to those advertised by
1757 * our link partner, and determines the proper flow control mode to use.
1758 **/
1759s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1760{
1761 s32 ret_val = IXGBE_SUCCESS;
1762 ixgbe_link_speed speed;
1763 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1781 goto out;
1782 break;
1783 }
1784
1785 /* Set 802.3x based flow control settings. */
1786 mflcn_reg |= IXGBE_MFLCN_DPF;
1787 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1788 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);

--- 52 unchanged lines hidden (view full) ---

1841 * Compares our advertised flow control capabilities to those advertised by
1842 * our link partner, and determines the proper flow control mode to use.
1843 **/
1844s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1845{
1846 s32 ret_val = IXGBE_SUCCESS;
1847 ixgbe_link_speed speed;
1848 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1849 u32 links2, anlp1_reg, autoc_reg, links;
1764 bool link_up;
1765
1766 DEBUGFUNC("ixgbe_fc_autoneg");
1767
1768 /*
1769 * AN should have completed when the cable was plugged in.
1770 * Look for reasons to bail out. Bail out if:
1771 * - FC autoneg is disabled, or if
1850 bool link_up;
1851
1852 DEBUGFUNC("ixgbe_fc_autoneg");
1853
1854 /*
1855 * AN should have completed when the cable was plugged in.
1856 * Look for reasons to bail out. Bail out if:
1857 * - FC autoneg is disabled, or if
1772 * - we don't have multispeed fiber, or if
1773 * - we're not running at 1G, or if
1774 * - link is not up, or if
1775 * - link is up but AN did not complete, or if
1776 * - link is up and AN completed but timed out
1858 * - link is not up.
1777 *
1859 *
1778 * Since we're being called from an LSC, link is already know to be up.
1860 * Since we're being called from an LSC, link is already known to be up.
1779 * So use link_up_wait_to_complete=FALSE.
1780 */
1781 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
1861 * So use link_up_wait_to_complete=FALSE.
1862 */
1863 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
1782 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1783
1864
1784 if (hw->fc.disable_fc_autoneg ||
1785 !hw->phy.multispeed_fiber ||
1786 (speed != IXGBE_LINK_SPEED_1GB_FULL) ||
1787 !link_up ||
1788 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1789 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1865 if (hw->fc.disable_fc_autoneg || (!link_up)) {
1790 hw->fc.fc_was_autonegged = FALSE;
1791 hw->fc.current_mode = hw->fc.requested_mode;
1866 hw->fc.fc_was_autonegged = FALSE;
1867 hw->fc.current_mode = hw->fc.requested_mode;
1792 DEBUGOUT("Autoneg FC was skipped.\n");
1793 goto out;
1794 }
1795
1796 /*
1868 goto out;
1869 }
1870
1871 /*
1872 * On backplane, bail out if
1873 * - backplane autoneg was not completed, or if
1874 * - we are 82599 and link partner is not AN enabled
1875 */
1876 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1877 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
1878 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
1879 hw->fc.fc_was_autonegged = FALSE;
1880 hw->fc.current_mode = hw->fc.requested_mode;
1881 goto out;
1882 }
1883
1884 if (hw->mac.type == ixgbe_mac_82599EB) {
1885 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1886 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1887 hw->fc.fc_was_autonegged = FALSE;
1888 hw->fc.current_mode = hw->fc.requested_mode;
1889 goto out;
1890 }
1891 }
1892 }
1893
1894 /*
1895 * On multispeed fiber at 1g, bail out if
1896 * - link is up but AN did not complete, or if
1897 * - link is up and AN completed but timed out
1898 */
1899 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1900 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1901 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1902 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1903 hw->fc.fc_was_autonegged = FALSE;
1904 hw->fc.current_mode = hw->fc.requested_mode;
1905 goto out;
1906 }
1907 }
1908
1909 /*
1910 * Bail out on
1911 * - copper or CX4 adapters
1912 * - fiber adapters running at 10gig
1913 */
1914 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1915 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1916 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1917 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1918 hw->fc.fc_was_autonegged = FALSE;
1919 hw->fc.current_mode = hw->fc.requested_mode;
1920 goto out;
1921 }
1922
1923 /*
1797 * Read the AN advertisement and LP ability registers and resolve
1798 * local flow control settings accordingly
1799 */
1924 * Read the AN advertisement and LP ability registers and resolve
1925 * local flow control settings accordingly
1926 */
1800 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1801 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1802 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1803 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1927 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1928 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1929 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1930 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1931 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1932 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1933 /*
1934 * Now we need to check if the user selected Rx ONLY
1935 * of pause frames. In this case, we had to advertise
1936 * FULL flow control because we could not advertise RX
1937 * ONLY. Hence, we must now check to see if we need to
1938 * turn OFF the TRANSMISSION of PAUSE frames.
1939 */
1940 if (hw->fc.requested_mode == ixgbe_fc_full) {
1941 hw->fc.current_mode = ixgbe_fc_full;
1942 DEBUGOUT("Flow Control = FULL.\n");
1943 } else {
1944 hw->fc.current_mode = ixgbe_fc_rx_pause;
1945 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1946 }
1947 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1948 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1949 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1950 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1951 hw->fc.current_mode = ixgbe_fc_tx_pause;
1952 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1953 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1954 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1955 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1956 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1957 hw->fc.current_mode = ixgbe_fc_rx_pause;
1958 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1959 } else {
1960 hw->fc.current_mode = ixgbe_fc_none;
1961 DEBUGOUT("Flow Control = NONE.\n");
1962 }
1963 }
1964
1965 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1804 /*
1966 /*
1805 * Now we need to check if the user selected Rx ONLY
1806 * of pause frames. In this case, we had to advertise
1807 * FULL flow control because we could not advertise RX
1808 * ONLY. Hence, we must now check to see if we need to
1809 * turn OFF the TRANSMISSION of PAUSE frames.
1967 * Read the 10g AN autoc and LP ability registers and resolve
1968 * local flow control settings accordingly
1810 */
1969 */
1811 if (hw->fc.requested_mode == ixgbe_fc_full) {
1812 hw->fc.current_mode = ixgbe_fc_full;
1813 DEBUGOUT("Flow Control = FULL.\n");
1814 } else {
1970 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1971 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1972
1973 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1974 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1975 /*
1976 * Now we need to check if the user selected Rx ONLY
1977 * of pause frames. In this case, we had to advertise
1978 * FULL flow control because we could not advertise RX
1979 * ONLY. Hence, we must now check to see if we need to
1980 * turn OFF the TRANSMISSION of PAUSE frames.
1981 */
1982 if (hw->fc.requested_mode == ixgbe_fc_full) {
1983 hw->fc.current_mode = ixgbe_fc_full;
1984 DEBUGOUT("Flow Control = FULL.\n");
1985 } else {
1986 hw->fc.current_mode = ixgbe_fc_rx_pause;
1987 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1988 }
1989 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1990 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1991 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1992 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1993 hw->fc.current_mode = ixgbe_fc_tx_pause;
1994 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1995 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1996 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1997 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1998 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1815 hw->fc.current_mode = ixgbe_fc_rx_pause;
1816 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1999 hw->fc.current_mode = ixgbe_fc_rx_pause;
2000 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2001 } else {
2002 hw->fc.current_mode = ixgbe_fc_none;
2003 DEBUGOUT("Flow Control = NONE.\n");
1817 }
2004 }
1818 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1819 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1820 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1821 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1822 hw->fc.current_mode = ixgbe_fc_tx_pause;
1823 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1824 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1825 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1826 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1827 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1828 hw->fc.current_mode = ixgbe_fc_rx_pause;
1829 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1830 } else {
1831 hw->fc.current_mode = ixgbe_fc_none;
1832 DEBUGOUT("Flow Control = NONE.\n");
1833 }
2005 }
1834
1835 /* Record that current_mode is the result of a successful autoneg */
1836 hw->fc.fc_was_autonegged = TRUE;
1837
1838out:
1839 return ret_val;
1840}
1841
1842/**
1843 * ixgbe_setup_fc - Set up flow control
1844 * @hw: pointer to hardware structure
1845 *
1846 * Called at init time to set up flow control.
1847 **/
1848s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1849{
1850 s32 ret_val = IXGBE_SUCCESS;
1851 u32 reg;
1852
2006 /* Record that current_mode is the result of a successful autoneg */
2007 hw->fc.fc_was_autonegged = TRUE;
2008
2009out:
2010 return ret_val;
2011}
2012
2013/**
2014 * ixgbe_setup_fc - Set up flow control
2015 * @hw: pointer to hardware structure
2016 *
2017 * Called at init time to set up flow control.
2018 **/
2019s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
2020{
2021 s32 ret_val = IXGBE_SUCCESS;
2022 u32 reg;
2023
2024 DEBUGFUNC("ixgbe_setup_fc");
1853
2025
2026
1854 /* Validate the packetbuf configuration */
1855 if (packetbuf_num < 0 || packetbuf_num > 7) {
1856 DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
1857 " 0-7\n", packetbuf_num);
1858 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1859 goto out;
1860 }
1861

--- 66 unchanged lines hidden (view full) ---

1928 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1929 break;
1930 case ixgbe_fc_full:
1931 /* Flow control (both Rx and Tx) is enabled by SW override. */
1932 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1933 break;
1934 default:
1935 DEBUGOUT("Flow control param set incorrectly\n");
2027 /* Validate the packetbuf configuration */
2028 if (packetbuf_num < 0 || packetbuf_num > 7) {
2029 DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
2030 " 0-7\n", packetbuf_num);
2031 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2032 goto out;
2033 }
2034

--- 66 unchanged lines hidden (view full) ---

2101 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
2102 break;
2103 case ixgbe_fc_full:
2104 /* Flow control (both Rx and Tx) is enabled by SW override. */
2105 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2106 break;
2107 default:
2108 DEBUGOUT("Flow control param set incorrectly\n");
1936 ret_val = -IXGBE_ERR_CONFIG;
2109 ret_val = IXGBE_ERR_CONFIG;
1937 goto out;
1938 break;
1939 }
1940
1941 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1942 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1943
2110 goto out;
2111 break;
2112 }
2113
2114 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2115 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2116
1944 /* Enable and restart autoneg to inform the link partner */
1945 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1946
1947 /* Disable AN timeout */
1948 if (hw->fc.strict_ieee)
1949 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1950
1951 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1952 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
1953
2117 /* Disable AN timeout */
2118 if (hw->fc.strict_ieee)
2119 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2120
2121 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2122 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2123
2124 /*
2125 * Set up the 10G flow control advertisement registers so the HW
2126 * can do fc autoneg once the cable is plugged in. If we end up
2127 * using 1g instead, this is harmless.
2128 */
2129 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2130
2131 /*
2132 * The possible values of fc.requested_mode are:
2133 * 0: Flow control is completely disabled
2134 * 1: Rx flow control is enabled (we can receive pause frames,
2135 * but not send pause frames).
2136 * 2: Tx flow control is enabled (we can send pause frames but
2137 * we do not support receiving pause frames).
2138 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2139 * other: Invalid.
2140 */
2141 switch (hw->fc.requested_mode) {
2142 case ixgbe_fc_none:
2143 /* Flow control completely disabled by software override. */
2144 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2145 break;
2146 case ixgbe_fc_rx_pause:
2147 /*
2148 * Rx Flow control is enabled and Tx Flow control is
2149 * disabled by software override. Since there really
2150 * isn't a way to advertise that we are capable of RX
2151 * Pause ONLY, we will advertise that we support both
2152 * symmetric and asymmetric Rx PAUSE. Later, we will
2153 * disable the adapter's ability to send PAUSE frames.
2154 */
2155 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2156 break;
2157 case ixgbe_fc_tx_pause:
2158 /*
2159 * Tx Flow control is enabled, and Rx Flow control is
2160 * disabled by software override.
2161 */
2162 reg |= (IXGBE_AUTOC_ASM_PAUSE);
2163 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
2164 break;
2165 case ixgbe_fc_full:
2166 /* Flow control (both Rx and Tx) is enabled by SW override. */
2167 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2168 break;
2169 default:
2170 DEBUGOUT("Flow control param set incorrectly\n");
2171 ret_val = IXGBE_ERR_CONFIG;
2172 goto out;
2173 break;
2174 }
2175 /*
2176 * AUTOC restart handles negotiation of 1G and 10G. There is
2177 * no need to set the PCS1GCTL register.
2178 */
2179 reg |= IXGBE_AUTOC_AN_RESTART;
2180 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2181 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2182
1954out:
1955 return ret_val;
1956}
1957
1958/**
1959 * ixgbe_disable_pcie_master - Disable PCI-express master access
1960 * @hw: pointer to hardware structure
1961 *

--- 4 unchanged lines hidden (view full) ---

1966 **/
1967s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1968{
1969 u32 i;
1970 u32 reg_val;
1971 u32 number_of_queues;
1972 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1973
2183out:
2184 return ret_val;
2185}
2186
2187/**
2188 * ixgbe_disable_pcie_master - Disable PCI-express master access
2189 * @hw: pointer to hardware structure
2190 *

--- 4 unchanged lines hidden (view full) ---

2195 **/
2196s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2197{
2198 u32 i;
2199 u32 reg_val;
2200 u32 number_of_queues;
2201 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2202
2203 DEBUGFUNC("ixgbe_disable_pcie_master");
2204
1974 /* Disable the receive unit by stopping each queue */
1975 number_of_queues = hw->mac.max_rx_queues;
1976 for (i = 0; i < number_of_queues; i++) {
1977 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1978 if (reg_val & IXGBE_RXDCTL_ENABLE) {
1979 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1980 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1981 }

--- 25 unchanged lines hidden (view full) ---

2007 **/
2008s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2009{
2010 u32 gssr;
2011 u32 swmask = mask;
2012 u32 fwmask = mask << 5;
2013 s32 timeout = 200;
2014
2205 /* Disable the receive unit by stopping each queue */
2206 number_of_queues = hw->mac.max_rx_queues;
2207 for (i = 0; i < number_of_queues; i++) {
2208 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2209 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2210 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2211 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2212 }

--- 25 unchanged lines hidden (view full) ---

2238 **/
2239s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2240{
2241 u32 gssr;
2242 u32 swmask = mask;
2243 u32 fwmask = mask << 5;
2244 s32 timeout = 200;
2245
2246 DEBUGFUNC("ixgbe_acquire_swfw_sync");
2247
2015 while (timeout) {
2016 /*
2017 * SW EEPROM semaphore bit is used for access to all
2018 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2019 */
2020 if (ixgbe_get_eeprom_semaphore(hw))
2248 while (timeout) {
2249 /*
2250 * SW EEPROM semaphore bit is used for access to all
2251 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2252 */
2253 if (ixgbe_get_eeprom_semaphore(hw))
2021 return -IXGBE_ERR_SWFW_SYNC;
2254 return IXGBE_ERR_SWFW_SYNC;
2022
2023 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2024 if (!(gssr & (fwmask | swmask)))
2025 break;
2026
2027 /*
2028 * Firmware currently using resource (fwmask) or other software
2029 * thread currently using resource (swmask)
2030 */
2031 ixgbe_release_eeprom_semaphore(hw);
2032 msec_delay(5);
2033 timeout--;
2034 }
2035
2036 if (!timeout) {
2037 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2255
2256 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2257 if (!(gssr & (fwmask | swmask)))
2258 break;
2259
2260 /*
2261 * Firmware currently using resource (fwmask) or other software
2262 * thread currently using resource (swmask)
2263 */
2264 ixgbe_release_eeprom_semaphore(hw);
2265 msec_delay(5);
2266 timeout--;
2267 }
2268
2269 if (!timeout) {
2270 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2038 return -IXGBE_ERR_SWFW_SYNC;
2271 return IXGBE_ERR_SWFW_SYNC;
2039 }
2040
2041 gssr |= swmask;
2042 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2043
2044 ixgbe_release_eeprom_semaphore(hw);
2045 return IXGBE_SUCCESS;
2046}

--- 6 unchanged lines hidden (view full) ---

2053 * Releases the SWFW semaphore thought the GSSR register for the specified
2054 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2055 **/
2056void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2057{
2058 u32 gssr;
2059 u32 swmask = mask;
2060
2272 }
2273
2274 gssr |= swmask;
2275 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2276
2277 ixgbe_release_eeprom_semaphore(hw);
2278 return IXGBE_SUCCESS;
2279}

--- 6 unchanged lines hidden (view full) ---

2286 * Releases the SWFW semaphore thought the GSSR register for the specified
2287 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2288 **/
2289void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2290{
2291 u32 gssr;
2292 u32 swmask = mask;
2293
2294 DEBUGFUNC("ixgbe_release_swfw_sync");
2295
2061 ixgbe_get_eeprom_semaphore(hw);
2062
2063 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2064 gssr &= ~swmask;
2065 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2066
2067 ixgbe_release_eeprom_semaphore(hw);
2068}
2069
2070/**
2071 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2072 * @hw: pointer to hardware structure
2073 * @regval: register value to write to RXCTRL
2074 *
2075 * Enables the Rx DMA unit
2076 **/
2077s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2078{
2296 ixgbe_get_eeprom_semaphore(hw);
2297
2298 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2299 gssr &= ~swmask;
2300 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2301
2302 ixgbe_release_eeprom_semaphore(hw);
2303}
2304
2305/**
2306 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2307 * @hw: pointer to hardware structure
2308 * @regval: register value to write to RXCTRL
2309 *
2310 * Enables the Rx DMA unit
2311 **/
2312s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2313{
2314 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2315
2079 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2080
2081 return IXGBE_SUCCESS;
2082}
2083
2084/**
2085 * ixgbe_blink_led_start_generic - Blink LED based on index.
2086 * @hw: pointer to hardware structure
2087 * @index: led number to blink
2088 **/
2089s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2090{
2091 ixgbe_link_speed speed = 0;
2092 bool link_up = 0;
2093 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2094 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2095
2316 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2317
2318 return IXGBE_SUCCESS;
2319}
2320
2321/**
2322 * ixgbe_blink_led_start_generic - Blink LED based on index.
2323 * @hw: pointer to hardware structure
2324 * @index: led number to blink
2325 **/
2326s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2327{
2328 ixgbe_link_speed speed = 0;
2329 bool link_up = 0;
2330 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2331 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2332
2333 DEBUGFUNC("ixgbe_blink_led_start_generic");
2334
2096 /*
2097 * Link must be up to auto-blink the LEDs;
2098 * Force it if link is down.
2099 */
2100 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2101
2102 if (!link_up) {
2103

--- 16 unchanged lines hidden (view full) ---

2120 * @hw: pointer to hardware structure
2121 * @index: led number to stop blinking
2122 **/
2123s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2124{
2125 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2126 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2127
2335 /*
2336 * Link must be up to auto-blink the LEDs;
2337 * Force it if link is down.
2338 */
2339 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2340
2341 if (!link_up) {
2342

--- 16 unchanged lines hidden (view full) ---

2359 * @hw: pointer to hardware structure
2360 * @index: led number to stop blinking
2361 **/
2362s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2363{
2364 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2365 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2366
2367 DEBUGFUNC("ixgbe_blink_led_stop_generic");
2128
2368
2369
2129 autoc_reg &= ~IXGBE_AUTOC_FLU;
2130 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2131 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2132
2133 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2134 led_reg &= ~IXGBE_LED_BLINK(index);
2135 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2136 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2137 IXGBE_WRITE_FLUSH(hw);
2138
2139 return IXGBE_SUCCESS;
2140}
2141
2370 autoc_reg &= ~IXGBE_AUTOC_FLU;
2371 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2372 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2373
2374 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2375 led_reg &= ~IXGBE_LED_BLINK(index);
2376 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2377 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2378 IXGBE_WRITE_FLUSH(hw);
2379
2380 return IXGBE_SUCCESS;
2381}
2382
2383/**
2384 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2385 * @hw: pointer to hardware structure
2386 * @san_mac_offset: SAN MAC address offset
2387 *
2388 * This function will read the EEPROM location for the SAN MAC address
2389 * pointer, and returns the value at that location. This is used in both
2390 * get and set mac_addr routines.
2391 **/
2392static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2393 u16 *san_mac_offset)
2394{
2395 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
2396
2397 /*
2398 * First read the EEPROM pointer to see if the MAC addresses are
2399 * available.
2400 */
2401 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2402
2403 return IXGBE_SUCCESS;
2404}
2405
2406/**
2407 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2408 * @hw: pointer to hardware structure
2409 * @san_mac_addr: SAN MAC address
2410 *
2411 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2412 * per-port, so set_lan_id() must be called before reading the addresses.
2413 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2414 * upon for non-SFP connections, so we must call it here.
2415 **/
2416s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2417{
2418 u16 san_mac_data, san_mac_offset;
2419 u8 i;
2420
2421 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
2422
2423 /*
2424 * First read the EEPROM pointer to see if the MAC addresses are
2425 * available. If they're not, no point in calling set_lan_id() here.
2426 */
2427 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2428
2429 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2430 /*
2431 * No addresses available in this EEPROM. It's not an
2432 * error though, so just wipe the local address and return.
2433 */
2434 for (i = 0; i < 6; i++)
2435 san_mac_addr[i] = 0xFF;
2436
2437 goto san_mac_addr_out;
2438 }
2439
2440 /* make sure we know which port we need to program */
2441 hw->mac.ops.set_lan_id(hw);
2442 /* apply the port offset to the address offset */
2443 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2444 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2445 for (i = 0; i < 3; i++) {
2446 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2447 san_mac_addr[i * 2] = (u8)(san_mac_data);
2448 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2449 san_mac_offset++;
2450 }
2451
2452san_mac_addr_out:
2453 return IXGBE_SUCCESS;
2454}
2455
2456/**
2457 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
2458 * @hw: pointer to hardware structure
2459 * @san_mac_addr: SAN MAC address
2460 *
2461 * Write a SAN MAC address to the EEPROM.
2462 **/
2463s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2464{
2465 s32 status = IXGBE_SUCCESS;
2466 u16 san_mac_data, san_mac_offset;
2467 u8 i;
2468
2469 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
2470
2471 /* Look for SAN mac address pointer. If not defined, return */
2472 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2473
2474 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2475 status = IXGBE_ERR_NO_SAN_ADDR_PTR;
2476 goto san_mac_addr_out;
2477 }
2478
2479 /* Make sure we know which port we need to write */
2480 hw->mac.ops.set_lan_id(hw);
2481 /* Apply the port offset to the address offset */
2482 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2483 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2484
2485 for (i = 0; i < 3; i++) {
2486 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
2487 san_mac_data |= (u16)(san_mac_addr[i * 2]);
2488 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
2489 san_mac_offset++;
2490 }
2491
2492san_mac_addr_out:
2493 return status;
2494}
2495
2496/**
2497 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2498 * @hw: pointer to hardware structure
2499 *
2500 * Read PCIe configuration space, and get the MSI-X vector count from
2501 * the capabilities table.
2502 **/
2503u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2504{
2505 u32 msix_count = 64;
2506
2507 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
2508 if (hw->mac.msix_vectors_from_pcie) {
2509 msix_count = IXGBE_READ_PCIE_WORD(hw,
2510 IXGBE_PCIE_MSIX_82599_CAPS);
2511 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2512
2513 /* MSI-X count is zero-based in HW, so increment to give
2514 * proper value */
2515 msix_count++;
2516 }
2517
2518 return msix_count;
2519}
2520
2521/**
2522 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
2523 * @hw: pointer to hardware structure
2524 * @addr: Address to put into receive address register
2525 * @vmdq: VMDq pool to assign
2526 *
2527 * Puts an ethernet address into a receive address register, or
2528 * finds the rar that it is aleady in; adds to the pool list
2529 **/
2530s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2531{
2532 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
2533 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
2534 u32 rar;
2535 u32 rar_low, rar_high;
2536 u32 addr_low, addr_high;
2537
2538 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
2539
2540 /* swap bytes for HW little endian */
2541 addr_low = addr[0] | (addr[1] << 8)
2542 | (addr[2] << 16)
2543 | (addr[3] << 24);
2544 addr_high = addr[4] | (addr[5] << 8);
2545
2546 /*
2547 * Either find the mac_id in rar or find the first empty space.
2548 * rar_highwater points to just after the highest currently used
2549 * rar in order to shorten the search. It grows when we add a new
2550 * rar to the top.
2551 */
2552 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
2553 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
2554
2555 if (((IXGBE_RAH_AV & rar_high) == 0)
2556 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
2557 first_empty_rar = rar;
2558 } else if ((rar_high & 0xFFFF) == addr_high) {
2559 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
2560 if (rar_low == addr_low)
2561 break; /* found it already in the rars */
2562 }
2563 }
2564
2565 if (rar < hw->mac.rar_highwater) {
2566 /* already there so just add to the pool bits */
2567 ixgbe_set_vmdq(hw, rar, vmdq);
2568 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
2569 /* stick it into first empty RAR slot we found */
2570 rar = first_empty_rar;
2571 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2572 } else if (rar == hw->mac.rar_highwater) {
2573 /* add it to the top of the list and inc the highwater mark */
2574 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2575 hw->mac.rar_highwater++;
2576 } else if (rar >= hw->mac.num_rar_entries) {
2577 return IXGBE_ERR_INVALID_MAC_ADDR;
2578 }
2579
2580 /*
2581 * If we found rar[0], make sure the default pool bit (we use pool 0)
2582 * remains cleared to be sure default pool packets will get delivered
2583 */
2584 if (rar == 0)
2585 ixgbe_clear_vmdq(hw, rar, 0);
2586
2587 return rar;
2588}
2589
2590/**
2591 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2592 * @hw: pointer to hardware struct
2593 * @rar: receive address register index to disassociate
2594 * @vmdq: VMDq pool index to remove from the rar
2595 **/
2596s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2597{
2598 u32 mpsar_lo, mpsar_hi;
2599 u32 rar_entries = hw->mac.num_rar_entries;
2600
2601 DEBUGFUNC("ixgbe_clear_vmdq_generic");
2602
2603 if (rar < rar_entries) {
2604 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2605 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2606
2607 if (!mpsar_lo && !mpsar_hi)
2608 goto done;
2609
2610 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2611 if (mpsar_lo) {
2612 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2613 mpsar_lo = 0;
2614 }
2615 if (mpsar_hi) {
2616 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2617 mpsar_hi = 0;
2618 }
2619 } else if (vmdq < 32) {
2620 mpsar_lo &= ~(1 << vmdq);
2621 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2622 } else {
2623 mpsar_hi &= ~(1 << (vmdq - 32));
2624 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2625 }
2626
2627 /* was that the last pool using this rar? */
2628 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2629 hw->mac.ops.clear_rar(hw, rar);
2630 } else {
2631 DEBUGOUT1("RAR index %d is out of range.\n", rar);
2632 }
2633
2634done:
2635 return IXGBE_SUCCESS;
2636}
2637
2638/**
2639 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2640 * @hw: pointer to hardware struct
2641 * @rar: receive address register index to associate with a VMDq index
2642 * @vmdq: VMDq pool index
2643 **/
2644s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2645{
2646 u32 mpsar;
2647 u32 rar_entries = hw->mac.num_rar_entries;
2648
2649 DEBUGFUNC("ixgbe_set_vmdq_generic");
2650
2651 if (rar < rar_entries) {
2652 if (vmdq < 32) {
2653 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2654 mpsar |= 1 << vmdq;
2655 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2656 } else {
2657 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2658 mpsar |= 1 << (vmdq - 32);
2659 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2660 }
2661 } else {
2662 DEBUGOUT1("RAR index %d is out of range.\n", rar);
2663 }
2664 return IXGBE_SUCCESS;
2665}
2666
2667/**
2668 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2669 * @hw: pointer to hardware structure
2670 **/
2671s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2672{
2673 int i;
2674
2675 DEBUGFUNC("ixgbe_init_uta_tables_generic");
2676 DEBUGOUT(" Clearing UTA\n");
2677
2678 for (i = 0; i < 128; i++)
2679 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2680
2681 return IXGBE_SUCCESS;
2682}
2683
2684/**
2685 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2686 * @hw: pointer to hardware structure
2687 * @vlan: VLAN id to write to VLAN filter
2688 *
2689 * return the VLVF index where this VLAN id should be placed
2690 *
2691 **/
2692s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2693{
2694 u32 bits = 0;
2695 u32 first_empty_slot = 0;
2696 s32 regindex;
2697
2698 /*
2699 * Search for the vlan id in the VLVF entries. Save off the first empty
2700 * slot found along the way
2701 */
2702 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2703 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2704 if (!bits && !(first_empty_slot))
2705 first_empty_slot = regindex;
2706 else if ((bits & 0x0FFF) == vlan)
2707 break;
2708 }
2709
2710 /*
2711 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2712 * in the VLVF. Else use the first empty VLVF register for this
2713 * vlan id.
2714 */
2715 if (regindex >= IXGBE_VLVF_ENTRIES) {
2716 if (first_empty_slot)
2717 regindex = first_empty_slot;
2718 else {
2719 DEBUGOUT("No space in VLVF.\n");
2720 regindex = -1;
2721 }
2722 }
2723
2724 return regindex;
2725}
2726
2727/**
2728 * ixgbe_set_vfta_generic - Set VLAN filter table
2729 * @hw: pointer to hardware structure
2730 * @vlan: VLAN id to write to VLAN filter
2731 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2732 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2733 *
2734 * Turn on/off specified VLAN in the VLAN filter table.
2735 **/
2736s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2737 bool vlan_on)
2738{
2739 s32 regindex;
2740 u32 bitindex;
2741 u32 bits;
2742 u32 vt;
2743
2744 DEBUGFUNC("ixgbe_set_vfta_generic");
2745
2746 if (vlan > 4095)
2747 return IXGBE_ERR_PARAM;
2748
2749 /*
2750 * this is a 2 part operation - first the VFTA, then the
2751 * VLVF and VLVFB if VT Mode is set
2752 */
2753
2754 /* Part 1
2755 * The VFTA is a bitstring made up of 128 32-bit registers
2756 * that enable the particular VLAN id, much like the MTA:
2757 * bits[11-5]: which register
2758 * bits[4-0]: which bit in the register
2759 */
2760 regindex = (vlan >> 5) & 0x7F;
2761 bitindex = vlan & 0x1F;
2762 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2763 if (vlan_on)
2764 bits |= (1 << bitindex);
2765 else
2766 bits &= ~(1 << bitindex);
2767 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
2768
2769
2770 /* Part 2
2771 * If VT Mode is set
2772 * Either vlan_on
2773 * make sure the vlan is in VLVF
2774 * set the vind bit in the matching VLVFB
2775 * Or !vlan_on
2776 * clear the pool bit and possibly the vind
2777 */
2778 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2779 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2780 if (vlan == 0) {
2781 regindex = 0;
2782 } else {
2783 regindex = ixgbe_find_vlvf_slot(hw, vlan);
2784 if (regindex < 0)
2785 goto out;
2786 }
2787
2788 if (vlan_on) {
2789 /* set the pool bit */
2790 if (vind < 32) {
2791 bits = IXGBE_READ_REG(hw,
2792 IXGBE_VLVFB(regindex*2));
2793 bits |= (1 << vind);
2794 IXGBE_WRITE_REG(hw,
2795 IXGBE_VLVFB(regindex*2),
2796 bits);
2797 } else {
2798 bits = IXGBE_READ_REG(hw,
2799 IXGBE_VLVFB((regindex*2)+1));
2800 bits |= (1 << vind);
2801 IXGBE_WRITE_REG(hw,
2802 IXGBE_VLVFB((regindex*2)+1),
2803 bits);
2804 }
2805 } else {
2806 /* clear the pool bit */
2807 if (vind < 32) {
2808 bits = IXGBE_READ_REG(hw,
2809 IXGBE_VLVFB(regindex*2));
2810 bits &= ~(1 << vind);
2811 IXGBE_WRITE_REG(hw,
2812 IXGBE_VLVFB(regindex*2),
2813 bits);
2814 bits |= IXGBE_READ_REG(hw,
2815 IXGBE_VLVFB((regindex*2)+1));
2816 } else {
2817 bits = IXGBE_READ_REG(hw,
2818 IXGBE_VLVFB((regindex*2)+1));
2819 bits &= ~(1 << vind);
2820 IXGBE_WRITE_REG(hw,
2821 IXGBE_VLVFB((regindex*2)+1),
2822 bits);
2823 bits |= IXGBE_READ_REG(hw,
2824 IXGBE_VLVFB(regindex*2));
2825 }
2826 }
2827
2828 if (bits)
2829 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
2830 (IXGBE_VLVF_VIEN | vlan));
2831 else
2832 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
2833 }
2834out:
2835 return IXGBE_SUCCESS;
2836}
2837
2838/**
2839 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2840 * @hw: pointer to hardware structure
2841 *
2842 * Clears the VLAN filer table, and the VMDq index associated with the filter
2843 **/
2844s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2845{
2846 u32 offset;
2847
2848 DEBUGFUNC("ixgbe_clear_vfta_generic");
2849
2850 for (offset = 0; offset < hw->mac.vft_size; offset++)
2851 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2852
2853 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2854 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2855 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2856 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2857 }
2858
2859 return IXGBE_SUCCESS;
2860}
2861
2862/**
2863 * ixgbe_check_mac_link_generic - Determine link and speed status
2864 * @hw: pointer to hardware structure
2865 * @speed: pointer to link speed
2866 * @link_up: TRUE when link is up
2867 * @link_up_wait_to_complete: bool used to wait for link up or not
2868 *
2869 * Reads the links register to determine if link is up and the current speed
2870 **/
2871s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2872 bool *link_up, bool link_up_wait_to_complete)
2873{
2874 u32 links_reg;
2875 u32 i;
2876
2877 DEBUGFUNC("ixgbe_check_mac_link_generic");
2878
2879 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2880 if (link_up_wait_to_complete) {
2881 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2882 if (links_reg & IXGBE_LINKS_UP) {
2883 *link_up = TRUE;
2884 break;
2885 } else {
2886 *link_up = FALSE;
2887 }
2888 msec_delay(100);
2889 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2890 }
2891 } else {
2892 if (links_reg & IXGBE_LINKS_UP)
2893 *link_up = TRUE;
2894 else
2895 *link_up = FALSE;
2896 }
2897
2898 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2899 IXGBE_LINKS_SPEED_10G_82599)
2900 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2901 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2902 IXGBE_LINKS_SPEED_1G_82599)
2903 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2904 else
2905 *speed = IXGBE_LINK_SPEED_100_FULL;
2906
2907 /* if link is down, zero out the current_mode */
2908 if (*link_up == FALSE) {
2909 hw->fc.current_mode = ixgbe_fc_none;
2910 hw->fc.fc_was_autonegged = FALSE;
2911 }
2912
2913 return IXGBE_SUCCESS;
2914}
2915
2916/**
2917 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
2918 * the EEPROM
2919 * @hw: pointer to hardware structure
2920 * @wwnn_prefix: the alternative WWNN prefix
2921 * @wwpn_prefix: the alternative WWPN prefix
2922 *
2923 * This function will read the EEPROM from the alternative SAN MAC address
2924 * block to check the support for the alternative WWNN/WWPN prefix support.
2925 **/
2926s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2927 u16 *wwpn_prefix)
2928{
2929 u16 offset, caps;
2930 u16 alt_san_mac_blk_offset;
2931
2932 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
2933
2934 /* clear output first */
2935 *wwnn_prefix = 0xFFFF;
2936 *wwpn_prefix = 0xFFFF;
2937
2938 /* check if alternative SAN MAC is supported */
2939 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2940 &alt_san_mac_blk_offset);
2941
2942 if ((alt_san_mac_blk_offset == 0) ||
2943 (alt_san_mac_blk_offset == 0xFFFF))
2944 goto wwn_prefix_out;
2945
2946 /* check capability in alternative san mac address block */
2947 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2948 hw->eeprom.ops.read(hw, offset, &caps);
2949 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2950 goto wwn_prefix_out;
2951
2952 /* get the corresponding prefix for WWNN/WWPN */
2953 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2954 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2955
2956 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2957 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2958
2959wwn_prefix_out:
2960 return IXGBE_SUCCESS;
2961}