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ixgbe_common.c (181003) ixgbe_common.c (185352)
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 181003 2008-07-30 18:15:18Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 185352 2008-11-26 23:41:18Z jfv $*/
34
35#include "ixgbe_common.h"
36#include "ixgbe_api.h"
37
38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);

--- 38 unchanged lines hidden (view full) ---

80 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
81
82 /* MAC */
83 mac->ops.init_hw = &ixgbe_init_hw_generic;
84 mac->ops.reset_hw = NULL;
85 mac->ops.start_hw = &ixgbe_start_hw_generic;
86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
87 mac->ops.get_media_type = NULL;
34
35#include "ixgbe_common.h"
36#include "ixgbe_api.h"
37
38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);

--- 38 unchanged lines hidden (view full) ---

80 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
81
82 /* MAC */
83 mac->ops.init_hw = &ixgbe_init_hw_generic;
84 mac->ops.reset_hw = NULL;
85 mac->ops.start_hw = &ixgbe_start_hw_generic;
86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
87 mac->ops.get_media_type = NULL;
88 mac->ops.get_supported_physical_layer = NULL;
88 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
89 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
90 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
89 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
90 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
91 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
91 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_generic;
92 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_generic;
92 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
93
94 /* LEDs */
95 mac->ops.led_on = &ixgbe_led_on_generic;
96 mac->ops.led_off = &ixgbe_led_off_generic;
97 mac->ops.blink_led_start = NULL;
98 mac->ops.blink_led_stop = NULL;
99
100 /* RAR, Multicast, VLAN */

--- 5 unchanged lines hidden (view full) ---

106 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
107 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
108 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
109 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
110 mac->ops.clear_vfta = NULL;
111 mac->ops.set_vfta = NULL;
112 mac->ops.init_uta_tables = NULL;
113
93
94 /* LEDs */
95 mac->ops.led_on = &ixgbe_led_on_generic;
96 mac->ops.led_off = &ixgbe_led_off_generic;
97 mac->ops.blink_led_start = NULL;
98 mac->ops.blink_led_stop = NULL;
99
100 /* RAR, Multicast, VLAN */

--- 5 unchanged lines hidden (view full) ---

106 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
107 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
108 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
109 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
110 mac->ops.clear_vfta = NULL;
111 mac->ops.set_vfta = NULL;
112 mac->ops.init_uta_tables = NULL;
113
114 /* Flow Control */
115 mac->ops.setup_fc = NULL;
116
117 /* Link */
118 mac->ops.get_link_capabilities = NULL;
119 mac->ops.setup_link = NULL;
120 mac->ops.setup_link_speed = NULL;
121 mac->ops.check_link = NULL;
122
123 return IXGBE_SUCCESS;

--- 86 unchanged lines hidden (view full) ---

210 IXGBE_READ_REG(hw, IXGBE_MSPDC);
211 for (i = 0; i < 8; i++)
212 IXGBE_READ_REG(hw, IXGBE_MPC(i));
213
214 IXGBE_READ_REG(hw, IXGBE_MLFC);
215 IXGBE_READ_REG(hw, IXGBE_MRFC);
216 IXGBE_READ_REG(hw, IXGBE_RLEC);
217 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
114
115 /* Link */
116 mac->ops.get_link_capabilities = NULL;
117 mac->ops.setup_link = NULL;
118 mac->ops.setup_link_speed = NULL;
119 mac->ops.check_link = NULL;
120
121 return IXGBE_SUCCESS;

--- 86 unchanged lines hidden (view full) ---

208 IXGBE_READ_REG(hw, IXGBE_MSPDC);
209 for (i = 0; i < 8; i++)
210 IXGBE_READ_REG(hw, IXGBE_MPC(i));
211
212 IXGBE_READ_REG(hw, IXGBE_MLFC);
213 IXGBE_READ_REG(hw, IXGBE_MRFC);
214 IXGBE_READ_REG(hw, IXGBE_RLEC);
215 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
218 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
219 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
216 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
217 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
220 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
221
222 for (i = 0; i < 8; i++) {
223 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
218 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
219
220 for (i = 0; i < 8; i++) {
221 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
224 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
225 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
222 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
223 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
226 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
227 }
224 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
225 }
228
229 IXGBE_READ_REG(hw, IXGBE_PRC64);
230 IXGBE_READ_REG(hw, IXGBE_PRC127);
231 IXGBE_READ_REG(hw, IXGBE_PRC255);
232 IXGBE_READ_REG(hw, IXGBE_PRC511);
233 IXGBE_READ_REG(hw, IXGBE_PRC1023);
234 IXGBE_READ_REG(hw, IXGBE_PRC1522);
235 IXGBE_READ_REG(hw, IXGBE_GPRC);
236 IXGBE_READ_REG(hw, IXGBE_BPRC);

--- 30 unchanged lines hidden (view full) ---

267 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
268 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
269 }
270
271 return IXGBE_SUCCESS;
272}
273
274/**
226 IXGBE_READ_REG(hw, IXGBE_PRC64);
227 IXGBE_READ_REG(hw, IXGBE_PRC127);
228 IXGBE_READ_REG(hw, IXGBE_PRC255);
229 IXGBE_READ_REG(hw, IXGBE_PRC511);
230 IXGBE_READ_REG(hw, IXGBE_PRC1023);
231 IXGBE_READ_REG(hw, IXGBE_PRC1522);
232 IXGBE_READ_REG(hw, IXGBE_GPRC);
233 IXGBE_READ_REG(hw, IXGBE_BPRC);

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264 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
265 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
266 }
267
268 return IXGBE_SUCCESS;
269}
270
271/**
275 * ixgbe_read_pba_num - Reads part number from EEPROM
272 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
276 * @hw: pointer to hardware structure
277 * @pba_num: stores the part number from the EEPROM
278 *
279 * Reads the part number from the EEPROM.
280 **/
281s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
282{
283 s32 ret_val;

--- 48 unchanged lines hidden (view full) ---

332/**
333 * ixgbe_get_bus_info_generic - Generic set PCI bus info
334 * @hw: pointer to hardware structure
335 *
336 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
337 **/
338s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
339{
273 * @hw: pointer to hardware structure
274 * @pba_num: stores the part number from the EEPROM
275 *
276 * Reads the part number from the EEPROM.
277 **/
278s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
279{
280 s32 ret_val;

--- 48 unchanged lines hidden (view full) ---

329/**
330 * ixgbe_get_bus_info_generic - Generic set PCI bus info
331 * @hw: pointer to hardware structure
332 *
333 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
334 **/
335s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
336{
337 struct ixgbe_mac_info *mac = &hw->mac;
340 u16 link_status;
341
342 hw->bus.type = ixgbe_bus_type_pci_express;
343
344 /* Get the negotiated link width and speed from PCI config space */
345 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
346
347 switch (link_status & IXGBE_PCI_LINK_WIDTH) {

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369 case IXGBE_PCI_LINK_SPEED_5000:
370 hw->bus.speed = ixgbe_bus_speed_5000;
371 break;
372 default:
373 hw->bus.speed = ixgbe_bus_speed_unknown;
374 break;
375 }
376
338 u16 link_status;
339
340 hw->bus.type = ixgbe_bus_type_pci_express;
341
342 /* Get the negotiated link width and speed from PCI config space */
343 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
344
345 switch (link_status & IXGBE_PCI_LINK_WIDTH) {

--- 21 unchanged lines hidden (view full) ---

367 case IXGBE_PCI_LINK_SPEED_5000:
368 hw->bus.speed = ixgbe_bus_speed_5000;
369 break;
370 default:
371 hw->bus.speed = ixgbe_bus_speed_unknown;
372 break;
373 }
374
375 mac->ops.set_lan_id(hw);
376
377 return IXGBE_SUCCESS;
378}
379
380/**
377 return IXGBE_SUCCESS;
378}
379
380/**
381 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
382 * @hw: pointer to the HW structure
383 *
384 * Determines the LAN function id by reading memory-mapped registers
385 * and swaps the port value if requested.
386 **/
387void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
388{
389 struct ixgbe_bus_info *bus = &hw->bus;
390 u32 reg;
391
392 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
393 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
394
395 /* check for a port swap */
396 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
397 if (reg & IXGBE_FACTPS_LFS)
398 bus->func ^= 0x1;
399}
400
401/**
381 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
382 * @hw: pointer to hardware structure
383 *
384 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
385 * disables transmit and receive units. The adapter_stopped flag is used by
386 * the shared code and drivers to determine if the adapter is in a stopped
387 * state and should not touch the hardware.
388 **/

--- 31 unchanged lines hidden (view full) ---

420 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
421 }
422 }
423
424 /*
425 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
426 * access and verify no pending requests
427 */
402 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
403 * @hw: pointer to hardware structure
404 *
405 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
406 * disables transmit and receive units. The adapter_stopped flag is used by
407 * the shared code and drivers to determine if the adapter is in a stopped
408 * state and should not touch the hardware.
409 **/

--- 31 unchanged lines hidden (view full) ---

441 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
442 }
443 }
444
445 /*
446 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
447 * access and verify no pending requests
448 */
428 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) {
449 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS)
429 DEBUGOUT("PCI-E Master disable polling has failed.\n");
450 DEBUGOUT("PCI-E Master disable polling has failed.\n");
430 }
431
432 return IXGBE_SUCCESS;
433}
434
435/**
436 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
437 * @hw: pointer to hardware structure
438 * @index: led number to turn on

--- 56 unchanged lines hidden (view full) ---

495 if (eec & IXGBE_EEC_PRES) {
496 eeprom->type = ixgbe_eeprom_spi;
497
498 /*
499 * SPI EEPROM is assumed here. This code would need to
500 * change if a future EEPROM is not SPI.
501 */
502 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
451
452 return IXGBE_SUCCESS;
453}
454
455/**
456 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
457 * @hw: pointer to hardware structure
458 * @index: led number to turn on

--- 56 unchanged lines hidden (view full) ---

515 if (eec & IXGBE_EEC_PRES) {
516 eeprom->type = ixgbe_eeprom_spi;
517
518 /*
519 * SPI EEPROM is assumed here. This code would need to
520 * change if a future EEPROM is not SPI.
521 */
522 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
503 IXGBE_EEC_SIZE_SHIFT);
523 IXGBE_EEC_SIZE_SHIFT);
504 eeprom->word_size = 1 << (eeprom_size +
524 eeprom->word_size = 1 << (eeprom_size +
505 IXGBE_EEPROM_WORD_SIZE_SHIFT);
525 IXGBE_EEPROM_WORD_SIZE_SHIFT);
506 }
507
508 if (eec & IXGBE_EEC_ADDR_SIZE)
509 eeprom->address_bits = 16;
510 else
511 eeprom->address_bits = 8;
512 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
526 }
527
528 if (eec & IXGBE_EEC_ADDR_SIZE)
529 eeprom->address_bits = 16;
530 else
531 eeprom->address_bits = 8;
532 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
513 "%d\n", eeprom->type, eeprom->word_size,
514 eeprom->address_bits);
533 "%d\n", eeprom->type, eeprom->word_size,
534 eeprom->address_bits);
515 }
516
517 return IXGBE_SUCCESS;
518}
519
520/**
521 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
522 * @hw: pointer to hardware structure

--- 628 unchanged lines hidden (view full) ---

1151 * not continue or we could be in for a very long wait while every
1152 * EEPROM read fails
1153 */
1154 status = hw->eeprom.ops.read(hw, 0, &checksum);
1155
1156 if (status == IXGBE_SUCCESS) {
1157 checksum = ixgbe_calc_eeprom_checksum(hw);
1158 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
535 }
536
537 return IXGBE_SUCCESS;
538}
539
540/**
541 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
542 * @hw: pointer to hardware structure

--- 628 unchanged lines hidden (view full) ---

1171 * not continue or we could be in for a very long wait while every
1172 * EEPROM read fails
1173 */
1174 status = hw->eeprom.ops.read(hw, 0, &checksum);
1175
1176 if (status == IXGBE_SUCCESS) {
1177 checksum = ixgbe_calc_eeprom_checksum(hw);
1178 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1159 checksum);
1179 checksum);
1160 } else {
1161 DEBUGOUT("EEPROM read failed\n");
1162 }
1163
1164 return status;
1165}
1166
1167/**

--- 280 unchanged lines hidden (view full) ---

1448 DEBUGOUT(" Adding the secondary addresses:\n");
1449 addr = next(hw, &addr_list, &vmdq);
1450 ixgbe_add_uc_addr(hw, addr, vmdq);
1451 }
1452
1453 if (hw->addr_ctrl.overflow_promisc) {
1454 /* enable promisc if not already in overflow or set by user */
1455 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1180 } else {
1181 DEBUGOUT("EEPROM read failed\n");
1182 }
1183
1184 return status;
1185}
1186
1187/**

--- 280 unchanged lines hidden (view full) ---

1468 DEBUGOUT(" Adding the secondary addresses:\n");
1469 addr = next(hw, &addr_list, &vmdq);
1470 ixgbe_add_uc_addr(hw, addr, vmdq);
1471 }
1472
1473 if (hw->addr_ctrl.overflow_promisc) {
1474 /* enable promisc if not already in overflow or set by user */
1475 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1456 DEBUGOUT( " Entering address overflow promisc mode\n");
1476 DEBUGOUT(" Entering address overflow promisc mode\n");
1457 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1458 fctrl |= IXGBE_FCTRL_UPE;
1459 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1460 }
1461 } else {
1462 /* only disable if set by overflow, not by user */
1463 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1464 DEBUGOUT(" Leaving address overflow promisc mode\n");

--- 214 unchanged lines hidden (view full) ---

1679 ixgbe_disable_rar(hw, i);
1680
1681 if (a->mta_in_use > 0)
1682 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1683
1684 return IXGBE_SUCCESS;
1685}
1686
1477 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1478 fctrl |= IXGBE_FCTRL_UPE;
1479 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1480 }
1481 } else {
1482 /* only disable if set by overflow, not by user */
1483 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1484 DEBUGOUT(" Leaving address overflow promisc mode\n");

--- 214 unchanged lines hidden (view full) ---

1699 ixgbe_disable_rar(hw, i);
1700
1701 if (a->mta_in_use > 0)
1702 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1703
1704 return IXGBE_SUCCESS;
1705}
1706
1707
1687/**
1708/**
1709 * ixgbe_fc_autoneg - Configure flow control
1710 * @hw: pointer to hardware structure
1711 *
1712 * Negotiates flow control capabilities with link partner using autoneg and
1713 * applies the results.
1714 **/
1715s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1716{
1717 s32 ret_val = IXGBE_SUCCESS;
1718 u32 i, reg, pcs_anadv_reg, pcs_lpab_reg;
1719
1720 DEBUGFUNC("ixgbe_fc_autoneg");
1721
1722 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1723
1724 /*
1725 * The possible values of fc.current_mode are:
1726 * 0: Flow control is completely disabled
1727 * 1: Rx flow control is enabled (we can receive pause frames,
1728 * but not send pause frames).
1729 * 2: Tx flow control is enabled (we can send pause frames but
1730 * we do not support receiving pause frames).
1731 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1732 * other: Invalid.
1733 */
1734 switch (hw->fc.current_mode) {
1735 case ixgbe_fc_none:
1736 /* Flow control completely disabled by software override. */
1737 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1738 break;
1739 case ixgbe_fc_rx_pause:
1740 /*
1741 * Rx Flow control is enabled and Tx Flow control is
1742 * disabled by software override. Since there really
1743 * isn't a way to advertise that we are capable of RX
1744 * Pause ONLY, we will advertise that we support both
1745 * symmetric and asymmetric Rx PAUSE. Later, we will
1746 * disable the adapter's ability to send PAUSE frames.
1747 */
1748 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1749 break;
1750 case ixgbe_fc_tx_pause:
1751 /*
1752 * Tx Flow control is enabled, and Rx Flow control is
1753 * disabled by software override.
1754 */
1755 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1756 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1757 break;
1758 case ixgbe_fc_full:
1759 /* Flow control (both Rx and Tx) is enabled by SW override. */
1760 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1761 break;
1762 default:
1763 DEBUGOUT("Flow control param set incorrectly\n");
1764 ret_val = -IXGBE_ERR_CONFIG;
1765 goto out;
1766 break;
1767 }
1768
1769 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1770 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1771
1772 /* Set PCS register for autoneg */
1773 /* Enable and restart autoneg */
1774 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1775
1776 /* Disable AN timeout */
1777 if (hw->fc.strict_ieee)
1778 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1779
1780 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1781 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1782
1783 /* See if autonegotiation has succeeded */
1784 hw->mac.autoneg_succeeded = 0;
1785 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1786 msec_delay(10);
1787 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1788 if ((reg & (IXGBE_PCS1GLSTA_LINK_OK |
1789 IXGBE_PCS1GLSTA_AN_COMPLETE)) ==
1790 (IXGBE_PCS1GLSTA_LINK_OK |
1791 IXGBE_PCS1GLSTA_AN_COMPLETE)) {
1792 if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT))
1793 hw->mac.autoneg_succeeded = 1;
1794 break;
1795 }
1796 }
1797
1798 if (!hw->mac.autoneg_succeeded) {
1799 /* Autoneg failed to achieve a link, so we turn fc off */
1800 hw->fc.current_mode = ixgbe_fc_none;
1801 DEBUGOUT("Flow Control = NONE.\n");
1802 goto out;
1803 }
1804
1805 /*
1806 * Read the AN advertisement and LP ability registers and resolve
1807 * local flow control settings accordingly
1808 */
1809 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1810 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1811 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1812 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1813 /*
1814 * Now we need to check if the user selected Rx ONLY
1815 * of pause frames. In this case, we had to advertise
1816 * FULL flow control because we could not advertise RX
1817 * ONLY. Hence, we must now check to see if we need to
1818 * turn OFF the TRANSMISSION of PAUSE frames.
1819 */
1820 if (hw->fc.requested_mode == ixgbe_fc_full) {
1821 hw->fc.current_mode = ixgbe_fc_full;
1822 DEBUGOUT("Flow Control = FULL.\n");
1823 } else {
1824 hw->fc.current_mode = ixgbe_fc_rx_pause;
1825 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1826 }
1827 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1828 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1829 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1830 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1831 hw->fc.current_mode = ixgbe_fc_tx_pause;
1832 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1833 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1834 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1835 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1836 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1837 hw->fc.current_mode = ixgbe_fc_rx_pause;
1838 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1839 } else {
1840 hw->fc.current_mode = ixgbe_fc_none;
1841 DEBUGOUT("Flow Control = NONE.\n");
1842 }
1843
1844out:
1845 return ret_val;
1846}
1847
1848
1849/**
1688 * ixgbe_disable_pcie_master - Disable PCI-express master access
1689 * @hw: pointer to hardware structure
1690 *
1691 * Disables PCI-Express master access and verifies there are no pending
1692 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1693 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
1694 * is returned signifying master requests disabled.
1695 **/

--- 91 unchanged lines hidden (view full) ---

1787
1788 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1789 gssr &= ~swmask;
1790 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1791
1792 ixgbe_release_eeprom_semaphore(hw);
1793}
1794
1850 * ixgbe_disable_pcie_master - Disable PCI-express master access
1851 * @hw: pointer to hardware structure
1852 *
1853 * Disables PCI-Express master access and verifies there are no pending
1854 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1855 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
1856 * is returned signifying master requests disabled.
1857 **/

--- 91 unchanged lines hidden (view full) ---

1949
1950 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1951 gssr &= ~swmask;
1952 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1953
1954 ixgbe_release_eeprom_semaphore(hw);
1955}
1956
1795/**
1796 * ixgbe_read_analog_reg8_generic - Reads 8 bit Atlas analog register
1797 * @hw: pointer to hardware structure
1798 * @reg: analog register to read
1799 * @val: read value
1800 *
1801 * Performs read operation to Atlas analog register specified.
1802 **/
1803s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val)
1804{
1805 u32 atlas_ctl;
1806
1807 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1808 IXGBE_WRITE_FLUSH(hw);
1809 usec_delay(10);
1810 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1811 *val = (u8)atlas_ctl;
1812
1813 return IXGBE_SUCCESS;
1814}
1815
1816/**
1817 * ixgbe_write_analog_reg8_generic - Writes 8 bit Atlas analog register
1818 * @hw: pointer to hardware structure
1819 * @reg: atlas register to write
1820 * @val: value to write
1821 *
1822 * Performs write operation to Atlas analog register specified.
1823 **/
1824s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val)
1825{
1826 u32 atlas_ctl;
1827
1828 atlas_ctl = (reg << 8) | val;
1829 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1830 IXGBE_WRITE_FLUSH(hw);
1831 usec_delay(10);
1832
1833 return IXGBE_SUCCESS;
1834}
1835