| 1/****************************************************************************** 2 |
| 3 Copyright (c) 2001-2017, Intel Corporation |
| 4 All rights reserved. |
| 5 6 Redistribution and use in source and binary forms, with or without |
| 7 modification, are permitted provided that the following conditions are met: |
| 8 9 1. Redistributions of source code must retain the above copyright notice, |
| 10 this list of conditions and the following disclaimer. |
| 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the |
| 14 documentation and/or other materials provided with the distribution. |
| 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from |
| 18 this software without specific prior written permission. |
| 19 |
| 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_common.c 320897 2017-07-11 21:25:07Z erj $*/ |
| 34 35#include "ixgbe_common.h" 36#include "ixgbe_phy.h" 37#include "ixgbe_dcb.h" 38#include "ixgbe_dcb_82599.h" 39#include "ixgbe_api.h" 40 41static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); --- 67 unchanged lines hidden (view full) --- 109 mac->ops.prot_autoc_read = prot_autoc_read_generic; 110 mac->ops.prot_autoc_write = prot_autoc_write_generic; 111 112 /* LEDs */ 113 mac->ops.led_on = ixgbe_led_on_generic; 114 mac->ops.led_off = ixgbe_led_off_generic; 115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; |
| 117 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; |
| 118 119 /* RAR, Multicast, VLAN */ 120 mac->ops.set_rar = ixgbe_set_rar_generic; 121 mac->ops.clear_rar = ixgbe_clear_rar_generic; 122 mac->ops.insert_mac_addr = NULL; 123 mac->ops.set_vmdq = NULL; 124 mac->ops.clear_vmdq = NULL; 125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; --- 6 unchanged lines hidden (view full) --- 132 mac->ops.set_vlvf = NULL; 133 mac->ops.init_uta_tables = NULL; 134 mac->ops.enable_rx = ixgbe_enable_rx_generic; 135 mac->ops.disable_rx = ixgbe_disable_rx_generic; 136 137 /* Flow Control */ 138 mac->ops.fc_enable = ixgbe_fc_enable_generic; 139 mac->ops.setup_fc = ixgbe_setup_fc_generic; |
| 140 mac->ops.fc_autoneg = ixgbe_fc_autoneg; |
| 141 142 /* Link */ 143 mac->ops.get_link_capabilities = NULL; 144 mac->ops.setup_link = NULL; 145 mac->ops.check_link = NULL; 146 mac->ops.dmac_config = NULL; 147 mac->ops.dmac_update_tcs = NULL; 148 mac->ops.dmac_config_tcs = NULL; --- 17 unchanged lines hidden (view full) --- 166 bool link_up; 167 168 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 169 170 switch (hw->phy.media_type) { 171 case ixgbe_media_type_fiber_fixed: 172 case ixgbe_media_type_fiber_qsfp: 173 case ixgbe_media_type_fiber: |
| 174 /* flow control autoneg black list */ 175 switch (hw->device_id) { 176 case IXGBE_DEV_ID_X550EM_A_SFP: 177 case IXGBE_DEV_ID_X550EM_A_SFP_N: 178 case IXGBE_DEV_ID_X550EM_A_QSFP: 179 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 180 supported = FALSE; 181 break; 182 default: 183 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 184 /* if link is down, assume supported */ 185 if (link_up) 186 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? |
| 187 TRUE : FALSE; |
| 188 else 189 supported = TRUE; 190 } 191 192 break; 193 case ixgbe_media_type_backplane: 194 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 195 supported = FALSE; |
| 196 else 197 supported = TRUE; 198 break; |
| 199 case ixgbe_media_type_copper: 200 /* only some copper devices support flow control autoneg */ 201 switch (hw->device_id) { 202 case IXGBE_DEV_ID_82599_T3_LOM: 203 case IXGBE_DEV_ID_X540T: 204 case IXGBE_DEV_ID_X540T1: 205 case IXGBE_DEV_ID_X540_BYPASS: 206 case IXGBE_DEV_ID_X550T: 207 case IXGBE_DEV_ID_X550T1: 208 case IXGBE_DEV_ID_X550EM_X_10G_T: |
| 209 case IXGBE_DEV_ID_X550EM_A_10G_T: 210 case IXGBE_DEV_ID_X550EM_A_1G_T: 211 case IXGBE_DEV_ID_X550EM_A_1G_T_L: |
| 212 supported = TRUE; 213 break; 214 default: 215 supported = FALSE; 216 } 217 default: 218 break; 219 } 220 |
| 221 if (!supported) |
| 222 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, |
| 223 "Device %x does not support flow control autoneg", 224 hw->device_id); |
| 225 return supported; 226} 227 228/** 229 * ixgbe_setup_fc_generic - Set up flow control 230 * @hw: pointer to hardware structure 231 * 232 * Called at init time to set up flow control. --- 29 unchanged lines hidden (view full) --- 262 */ 263 switch (hw->phy.media_type) { 264 case ixgbe_media_type_backplane: 265 /* some MAC's need RMW protection on AUTOC */ 266 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 267 if (ret_val != IXGBE_SUCCESS) 268 goto out; 269 |
| 270 /* fall through - only backplane uses autoc */ |
| 271 case ixgbe_media_type_fiber_fixed: 272 case ixgbe_media_type_fiber_qsfp: 273 case ixgbe_media_type_fiber: 274 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 275 276 break; 277 case ixgbe_media_type_copper: 278 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, --- 110 unchanged lines hidden (view full) --- 389 * all on chip counters, initializes receive address registers, multicast 390 * table, VLAN filter table, calls routine to set up link and flow control 391 * settings, and leaves transmit and receive units disabled and uninitialized 392 **/ 393s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 394{ 395 s32 ret_val; 396 u32 ctrl_ext; |
| 397 u16 device_caps; |
| 398 399 DEBUGFUNC("ixgbe_start_hw_generic"); 400 401 /* Set the media type */ 402 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 403 404 /* PHY ops initialization must be done in reset_hw() */ 405 --- 6 unchanged lines hidden (view full) --- 412 /* Set No Snoop Disable */ 413 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 414 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 415 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 416 IXGBE_WRITE_FLUSH(hw); 417 418 /* Setup flow control */ 419 ret_val = ixgbe_setup_fc(hw); |
| 420 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 421 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 422 return ret_val; 423 } |
| 424 |
| 425 /* Cache bit indicating need for crosstalk fix */ 426 switch (hw->mac.type) { 427 case ixgbe_mac_82599EB: 428 case ixgbe_mac_X550EM_x: 429 case ixgbe_mac_X550EM_a: 430 hw->mac.ops.get_device_caps(hw, &device_caps); 431 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 432 hw->need_crosstalk_fix = FALSE; 433 else 434 hw->need_crosstalk_fix = TRUE; 435 break; 436 default: 437 hw->need_crosstalk_fix = FALSE; 438 break; 439 } 440 |
| 441 /* Clear adapter stopped flag */ 442 hw->adapter_stopped = FALSE; 443 |
| 444 return IXGBE_SUCCESS; |
| 445} 446 447/** 448 * ixgbe_start_hw_gen2 - Init sequence for common device family 449 * @hw: pointer to hw structure 450 * 451 * Performs the init sequence common to the second generation 452 * of 10 GbE devices. --- 44 unchanged lines hidden (view full) --- 497{ 498 s32 status; 499 500 DEBUGFUNC("ixgbe_init_hw_generic"); 501 502 /* Reset the hardware */ 503 status = hw->mac.ops.reset_hw(hw); 504 |
| 505 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { |
| 506 /* Start the HW */ 507 status = hw->mac.ops.start_hw(hw); 508 } 509 |
| 510 /* Initialize the LED link active for LED blink support */ 511 if (hw->mac.ops.init_led_link_act) 512 hw->mac.ops.init_led_link_act(hw); 513 514 if (status != IXGBE_SUCCESS) 515 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 516 |
| 517 return status; 518} 519 520/** 521 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 522 * @hw: pointer to hardware structure 523 * 524 * Clears all hardware statistics counters by reading them from the hardware --- 539 unchanged lines hidden (view full) --- 1064 1065 return IXGBE_SUCCESS; 1066} 1067 1068/** 1069 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1070 * @hw: pointer to the HW structure 1071 * |
| 1072 * Determines the LAN function id by reading memory-mapped registers and swaps 1073 * the port value if requested, and set MAC instance for devices that share 1074 * CS4227. |
| 1075 **/ 1076void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1077{ 1078 struct ixgbe_bus_info *bus = &hw->bus; 1079 u32 reg; |
| 1080 u16 ee_ctrl_4; |
| 1081 1082 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1083 1084 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1085 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; |
| 1086 bus->lan_id = (u8)bus->func; |
| 1087 1088 /* check for a port swap */ 1089 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1090 if (reg & IXGBE_FACTPS_LFS) 1091 bus->func ^= 0x1; |
| 1092 1093 /* Get MAC instance from EEPROM for configuring CS4227 */ 1094 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1095 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1096 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1097 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1098 } |
| 1099} 1100 1101/** 1102 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1103 * @hw: pointer to hardware structure 1104 * 1105 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1106 * disables transmit and receive units. The adapter_stopped flag is used by --- 41 unchanged lines hidden (view full) --- 1148 /* 1149 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1150 * access and verify no pending requests 1151 */ 1152 return ixgbe_disable_pcie_master(hw); 1153} 1154 1155/** |
| 1156 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1157 * @hw: pointer to hardware structure 1158 * 1159 * Store the index for the link active LED. This will be used to support 1160 * blinking the LED. 1161 **/ 1162s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1163{ 1164 struct ixgbe_mac_info *mac = &hw->mac; 1165 u32 led_reg, led_mode; 1166 u8 i; 1167 1168 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1169 1170 /* Get LED link active from the LEDCTL register */ 1171 for (i = 0; i < 4; i++) { 1172 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1173 1174 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1175 IXGBE_LED_LINK_ACTIVE) { 1176 mac->led_link_act = i; 1177 return IXGBE_SUCCESS; 1178 } 1179 } 1180 1181 /* 1182 * If LEDCTL register does not have the LED link active set, then use 1183 * known MAC defaults. 1184 */ 1185 switch (hw->mac.type) { 1186 case ixgbe_mac_X550EM_a: 1187 case ixgbe_mac_X550EM_x: 1188 mac->led_link_act = 1; 1189 break; 1190 default: 1191 mac->led_link_act = 2; 1192 } 1193 return IXGBE_SUCCESS; 1194} 1195 1196/** |
| 1197 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1198 * @hw: pointer to hardware structure 1199 * @index: led number to turn on 1200 **/ 1201s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1202{ 1203 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1204 1205 DEBUGFUNC("ixgbe_led_on_generic"); 1206 |
| 1207 if (index > 3) 1208 return IXGBE_ERR_PARAM; 1209 |
| 1210 /* To turn on the LED, set mode to ON. */ 1211 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1212 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1213 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1214 IXGBE_WRITE_FLUSH(hw); 1215 1216 return IXGBE_SUCCESS; 1217} --- 4 unchanged lines hidden (view full) --- 1222 * @index: led number to turn off 1223 **/ 1224s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1225{ 1226 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1227 1228 DEBUGFUNC("ixgbe_led_off_generic"); 1229 |
| 1230 if (index > 3) 1231 return IXGBE_ERR_PARAM; 1232 |
| 1233 /* To turn off the LED, set mode to OFF. */ 1234 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1235 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1236 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1237 IXGBE_WRITE_FLUSH(hw); 1238 1239 return IXGBE_SUCCESS; 1240} --- 754 unchanged lines hidden (view full) --- 1995 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1996 IXGBE_EEPROM_OPCODE_BITS); 1997 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1998 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1999 break; 2000 2001 usec_delay(5); 2002 ixgbe_standby_eeprom(hw); |
| 2003 }; |
| 2004 2005 /* 2006 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2007 * devices (and only 0-5mSec on 5V devices) 2008 */ 2009 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2010 DEBUGOUT("SPI EEPROM Status error\n"); 2011 status = IXGBE_ERR_EEPROM; --- 69 unchanged lines hidden (view full) --- 2081 ixgbe_raise_eeprom_clk(hw, &eec); 2082 ixgbe_lower_eeprom_clk(hw, &eec); 2083 2084 /* 2085 * Shift mask to signify next bit of data to shift in to the 2086 * EEPROM 2087 */ 2088 mask = mask >> 1; |
| 2089 }; |
| 2090 2091 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2092 eec &= ~IXGBE_EEC_DI; 2093 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2094 IXGBE_WRITE_FLUSH(hw); 2095} 2096 2097/** --- 245 unchanged lines hidden (view full) --- 2343 2344 return status; 2345} 2346 2347/** 2348 * ixgbe_validate_mac_addr - Validate MAC address 2349 * @mac_addr: pointer to MAC address. 2350 * |
| 2351 * Tests a MAC address to ensure it is a valid Individual Address. |
| 2352 **/ 2353s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2354{ 2355 s32 status = IXGBE_SUCCESS; 2356 2357 DEBUGFUNC("ixgbe_validate_mac_addr"); 2358 2359 /* Make sure it is not a multicast address */ 2360 if (IXGBE_IS_MULTICAST(mac_addr)) { |
| 2361 status = IXGBE_ERR_INVALID_MAC_ADDR; 2362 /* Not a broadcast address */ 2363 } else if (IXGBE_IS_BROADCAST(mac_addr)) { |
| 2364 status = IXGBE_ERR_INVALID_MAC_ADDR; 2365 /* Reject the zero address */ 2366 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2367 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { |
| 2368 status = IXGBE_ERR_INVALID_MAC_ADDR; 2369 } 2370 return status; 2371} 2372 2373/** 2374 * ixgbe_set_rar_generic - Set Rx address register 2375 * @hw: pointer to hardware structure --- 121 unchanged lines hidden (view full) --- 2497 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2498 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2499 hw->mac.addr[0], hw->mac.addr[1], 2500 hw->mac.addr[2]); 2501 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2502 hw->mac.addr[4], hw->mac.addr[5]); 2503 2504 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
| 2505 } |
| 2506 2507 /* clear VMDq pool/queue selection for RAR 0 */ 2508 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2509 |
| 2510 hw->addr_ctrl.overflow_promisc = 0; 2511 2512 hw->addr_ctrl.rar_used_count = 1; 2513 2514 /* Zero out the other receive addresses. */ 2515 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2516 for (i = 1; i < rar_entries; i++) { 2517 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); --- 312 unchanged lines hidden (view full) --- 2830 DEBUGOUT("Invalid water mark configuration\n"); 2831 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2832 goto out; 2833 } 2834 } 2835 } 2836 2837 /* Negotiate the fc mode to use */ |
| 2838 hw->mac.ops.fc_autoneg(hw); |
| 2839 2840 /* Disable any previous flow control settings */ 2841 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2842 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2843 2844 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2845 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2846 --- 93 unchanged lines hidden (view full) --- 2940 * @adv_sym: symmetric pause bit in advertisement 2941 * @adv_asm: asymmetric pause bit in advertisement 2942 * @lp_sym: symmetric pause bit in link partner advertisement 2943 * @lp_asm: asymmetric pause bit in link partner advertisement 2944 * 2945 * Find the intersection between advertised settings and link partner's 2946 * advertised settings 2947 **/ |
| 2948s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2949 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) |
| 2950{ 2951 if ((!(adv_reg)) || (!(lp_reg))) { 2952 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2953 "Local or link partner's advertised flow control " 2954 "settings are NULL. Local: %x, link partner: %x\n", 2955 adv_reg, lp_reg); 2956 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2957 } --- 456 unchanged lines hidden (view full) --- 3414/** 3415 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3416 * @hw: pointer to hardware structure 3417 * 3418 * Enables the receive data path. 3419 **/ 3420s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3421{ |
| 3422 u32 secrxreg; |
| 3423 3424 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3425 3426 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3427 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3428 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3429 IXGBE_WRITE_FLUSH(hw); 3430 --- 30 unchanged lines hidden (view full) --- 3461 bool link_up = 0; 3462 u32 autoc_reg = 0; 3463 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3464 s32 ret_val = IXGBE_SUCCESS; 3465 bool locked = FALSE; 3466 3467 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3468 |
| 3469 if (index > 3) 3470 return IXGBE_ERR_PARAM; 3471 |
| 3472 /* 3473 * Link must be up to auto-blink the LEDs; 3474 * Force it if link is down. 3475 */ 3476 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3477 3478 if (!link_up) { 3479 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); --- 29 unchanged lines hidden (view full) --- 3509{ 3510 u32 autoc_reg = 0; 3511 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3512 s32 ret_val = IXGBE_SUCCESS; 3513 bool locked = FALSE; 3514 3515 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3516 |
| 3517 if (index > 3) 3518 return IXGBE_ERR_PARAM; 3519 3520 |
| 3521 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3522 if (ret_val != IXGBE_SUCCESS) 3523 goto out; 3524 3525 autoc_reg &= ~IXGBE_AUTOC_FLU; 3526 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3527 3528 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); --- 150 unchanged lines hidden (view full) --- 3679 case ixgbe_mac_82598EB: 3680 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3681 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3682 break; 3683 case ixgbe_mac_82599EB: 3684 case ixgbe_mac_X540: 3685 case ixgbe_mac_X550: 3686 case ixgbe_mac_X550EM_x: |
| 3687 case ixgbe_mac_X550EM_a: |
| 3688 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3689 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3690 break; 3691 default: 3692 return msix_count; 3693 } 3694 3695 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); --- 13 unchanged lines hidden (view full) --- 3709 3710/** 3711 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3712 * @hw: pointer to hardware structure 3713 * @addr: Address to put into receive address register 3714 * @vmdq: VMDq pool to assign 3715 * 3716 * Puts an ethernet address into a receive address register, or |
| 3717 * finds the rar that it is aleady in; adds to the pool list |
| 3718 **/ 3719s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3720{ 3721 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3722 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3723 u32 rar; 3724 u32 rar_low, rar_high; 3725 u32 addr_low, addr_high; --- 92 unchanged lines hidden (view full) --- 3818 mpsar_lo &= ~(1 << vmdq); 3819 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3820 } else { 3821 mpsar_hi &= ~(1 << (vmdq - 32)); 3822 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3823 } 3824 3825 /* was that the last pool using this rar? */ |
| 3826 if (mpsar_lo == 0 && mpsar_hi == 0 && 3827 rar != 0 && rar != hw->mac.san_mac_rar_index) |
| 3828 hw->mac.ops.clear_rar(hw, rar); 3829done: 3830 return IXGBE_SUCCESS; 3831} 3832 3833/** 3834 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3835 * @hw: pointer to hardware struct --- 73 unchanged lines hidden (view full) --- 3909/** 3910 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3911 * @hw: pointer to hardware structure 3912 * @vlan: VLAN id to write to VLAN filter 3913 * 3914 * return the VLVF index where this VLAN id should be placed 3915 * 3916 **/ |
| 3917s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) |
| 3918{ |
| 3919 s32 regindex, first_empty_slot; 3920 u32 bits; |
| 3921 3922 /* short cut the special case */ 3923 if (vlan == 0) 3924 return 0; 3925 |
| 3926 /* if vlvf_bypass is set we don't want to use an empty slot, we 3927 * will simply bypass the VLVF if there are no entries present in the 3928 * VLVF that contain our VLAN 3929 */ 3930 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3931 3932 /* add VLAN enable bit for comparison */ 3933 vlan |= IXGBE_VLVF_VIEN; 3934 3935 /* Search for the vlan id in the VLVF entries. Save off the first empty 3936 * slot found along the way. 3937 * 3938 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3939 */ 3940 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { |
| 3941 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); |
| 3942 if (bits == vlan) 3943 return regindex; 3944 if (!first_empty_slot && !bits) |
| 3945 first_empty_slot = regindex; |
| 3946 } 3947 |
| 3948 /* If we are here then we didn't find the VLAN. Return first empty 3949 * slot we found during our search, else error. 3950 */ 3951 if (!first_empty_slot) 3952 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); |
| 3953 |
| 3954 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; |
| 3955} 3956 3957/** 3958 * ixgbe_set_vfta_generic - Set VLAN filter table 3959 * @hw: pointer to hardware structure 3960 * @vlan: VLAN id to write to VLAN filter |
| 3961 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3962 * @vlan_on: boolean flag to turn on/off VLAN 3963 * @vlvf_bypass: boolean flag indicating updating default pool is okay |
| 3964 * 3965 * Turn on/off specified VLAN in the VLAN filter table. 3966 **/ 3967s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
| 3968 bool vlan_on, bool vlvf_bypass) |
| 3969{ |
| 3970 u32 regidx, vfta_delta, vfta; 3971 s32 ret_val; |
| 3972 3973 DEBUGFUNC("ixgbe_set_vfta_generic"); 3974 |
| 3975 if (vlan > 4095 || vind > 63) |
| 3976 return IXGBE_ERR_PARAM; 3977 3978 /* 3979 * this is a 2 part operation - first the VFTA, then the 3980 * VLVF and VLVFB if VT Mode is set 3981 * We don't write the VFTA until we know the VLVF part succeeded. 3982 */ 3983 3984 /* Part 1 3985 * The VFTA is a bitstring made up of 128 32-bit registers 3986 * that enable the particular VLAN id, much like the MTA: 3987 * bits[11-5]: which register 3988 * bits[4-0]: which bit in the register 3989 */ |
| 3990 regidx = vlan / 32; 3991 vfta_delta = 1 << (vlan % 32); 3992 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); |
| 3993 |
| 3994 /* 3995 * vfta_delta represents the difference between the current value 3996 * of vfta and the value we want in the register. Since the diff 3997 * is an XOR mask we can just update the vfta using an XOR 3998 */ 3999 vfta_delta &= vlan_on ? ~vfta : vfta; 4000 vfta ^= vfta_delta; |
| 4001 4002 /* Part 2 4003 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4004 */ |
| 4005 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4006 vfta, vlvf_bypass); 4007 if (ret_val != IXGBE_SUCCESS) { 4008 if (vlvf_bypass) 4009 goto vfta_update; |
| 4010 return ret_val; |
| 4011 } |
| 4012 |
| 4013vfta_update: 4014 /* Update VFTA now that we are ready for traffic */ 4015 if (vfta_delta) 4016 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); |
| 4017 4018 return IXGBE_SUCCESS; 4019} 4020 4021/** 4022 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4023 * @hw: pointer to hardware structure 4024 * @vlan: VLAN id to write to VLAN filter |
| 4025 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4026 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4027 * @vfta_delta: pointer to the difference between the current value of VFTA 4028 * and the desired value 4029 * @vfta: the desired value of the VFTA 4030 * @vlvf_bypass: boolean flag indicating updating default pool is okay |
| 4031 * 4032 * Turn on/off specified bit in VLVF table. 4033 **/ 4034s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
| 4035 bool vlan_on, u32 *vfta_delta, u32 vfta, 4036 bool vlvf_bypass) |
| 4037{ |
| 4038 u32 bits; 4039 s32 vlvf_index; |
| 4040 4041 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4042 |
| 4043 if (vlan > 4095 || vind > 63) |
| 4044 return IXGBE_ERR_PARAM; 4045 4046 /* If VT Mode is set 4047 * Either vlan_on 4048 * make sure the vlan is in VLVF 4049 * set the vind bit in the matching VLVFB 4050 * Or !vlan_on 4051 * clear the pool bit and possibly the vind 4052 */ |
| 4053 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4054 return IXGBE_SUCCESS; |
| 4055 |
| 4056 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4057 if (vlvf_index < 0) 4058 return vlvf_index; |
| 4059 |
| 4060 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); |
| 4061 |
| 4062 /* set the pool bit */ 4063 bits |= 1 << (vind % 32); 4064 if (vlan_on) 4065 goto vlvf_update; 4066 4067 /* clear the pool bit */ 4068 bits ^= 1 << (vind % 32); 4069 4070 if (!bits && 4071 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4072 /* Clear VFTA first, then disable VLVF. Otherwise 4073 * we run the risk of stray packets leaking into 4074 * the PF via the default pool |
| 4075 */ |
| 4076 if (*vfta_delta) 4077 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4078 4079 /* disable VLVF and clear remaining bit from pool */ 4080 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4081 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4082 4083 return IXGBE_SUCCESS; |
| 4084 } 4085 |
| 4086 /* If there are still bits set in the VLVFB registers 4087 * for the VLAN ID indicated we need to see if the 4088 * caller is requesting that we clear the VFTA entry bit. 4089 * If the caller has requested that we clear the VFTA 4090 * entry bit but there are still pools/VFs using this VLAN 4091 * ID entry then ignore the request. We're not worried 4092 * about the case where we're turning the VFTA VLAN ID 4093 * entry bit on, only when requested to turn it off as 4094 * there may be multiple pools and/or VFs using the 4095 * VLAN ID entry. In that case we cannot clear the 4096 * VFTA bit until all pools/VFs using that VLAN ID have also 4097 * been cleared. This will be indicated by "bits" being 4098 * zero. 4099 */ 4100 *vfta_delta = 0; 4101 4102vlvf_update: 4103 /* record pool change and enable VLAN ID if not already enabled */ 4104 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4105 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4106 |
| 4107 return IXGBE_SUCCESS; 4108} 4109 4110/** 4111 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4112 * @hw: pointer to hardware structure 4113 * 4114 * Clears the VLAN filer table, and the VMDq index associated with the filter --- 5 unchanged lines hidden (view full) --- 4120 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4121 4122 for (offset = 0; offset < hw->mac.vft_size; offset++) 4123 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4124 4125 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4126 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4127 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); |
| 4128 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); |
| 4129 } 4130 4131 return IXGBE_SUCCESS; 4132} 4133 4134/** |
| 4135 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4136 * @hw: pointer to hardware structure 4137 * 4138 * Contains the logic to identify if we need to verify link for the 4139 * crosstalk fix 4140 **/ 4141static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4142{ 4143 4144 /* Does FW say we need the fix */ 4145 if (!hw->need_crosstalk_fix) 4146 return FALSE; 4147 4148 /* Only consider SFP+ PHYs i.e. media type fiber */ 4149 switch (hw->mac.ops.get_media_type(hw)) { 4150 case ixgbe_media_type_fiber: 4151 case ixgbe_media_type_fiber_qsfp: 4152 break; 4153 default: 4154 return FALSE; 4155 } 4156 4157 return TRUE; 4158} 4159 4160/** |
| 4161 * ixgbe_check_mac_link_generic - Determine link and speed status 4162 * @hw: pointer to hardware structure 4163 * @speed: pointer to link speed 4164 * @link_up: TRUE when link is up 4165 * @link_up_wait_to_complete: bool used to wait for link up or not 4166 * 4167 * Reads the links register to determine if link is up and the current speed 4168 **/ 4169s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4170 bool *link_up, bool link_up_wait_to_complete) 4171{ 4172 u32 links_reg, links_orig; 4173 u32 i; 4174 4175 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4176 |
| 4177 /* If Crosstalk fix enabled do the sanity check of making sure 4178 * the SFP+ cage is full. 4179 */ 4180 if (ixgbe_need_crosstalk_fix(hw)) { 4181 u32 sfp_cage_full; 4182 4183 switch (hw->mac.type) { 4184 case ixgbe_mac_82599EB: 4185 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4186 IXGBE_ESDP_SDP2; 4187 break; 4188 case ixgbe_mac_X550EM_x: 4189 case ixgbe_mac_X550EM_a: 4190 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4191 IXGBE_ESDP_SDP0; 4192 break; 4193 default: 4194 /* sanity check - No SFP+ devices here */ 4195 sfp_cage_full = FALSE; 4196 break; 4197 } 4198 4199 if (!sfp_cage_full) { 4200 *link_up = FALSE; 4201 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4202 return IXGBE_SUCCESS; 4203 } 4204 } 4205 |
| 4206 /* clear the old state */ 4207 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4208 4209 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4210 4211 if (links_orig != links_reg) { 4212 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4213 links_orig, links_reg); --- 25 unchanged lines hidden (view full) --- 4239 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4240 } 4241 break; 4242 case IXGBE_LINKS_SPEED_1G_82599: 4243 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4244 break; 4245 case IXGBE_LINKS_SPEED_100_82599: 4246 *speed = IXGBE_LINK_SPEED_100_FULL; |
| 4247 if (hw->mac.type == ixgbe_mac_X550) { |
| 4248 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4249 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4250 } 4251 break; |
| 4252 case IXGBE_LINKS_SPEED_10_X550EM_A: 4253 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4254 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4255 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 4256 *speed = IXGBE_LINK_SPEED_10_FULL; 4257 } 4258 break; |
| 4259 default: 4260 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4261 } 4262 4263 return IXGBE_SUCCESS; 4264} 4265 4266/** --- 101 unchanged lines hidden (view full) --- 4368 4369out: 4370 return status; 4371} 4372 4373/** 4374 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4375 * @hw: pointer to hardware structure |
| 4376 * @enable: enable or disable switch for MAC anti-spoofing 4377 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing |
| 4378 * 4379 **/ |
| 4380void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) |
| 4381{ |
| 4382 int vf_target_reg = vf >> 3; 4383 int vf_target_shift = vf % 8; 4384 u32 pfvfspoof; |
| 4385 4386 if (hw->mac.type == ixgbe_mac_82598EB) 4387 return; 4388 |
| 4389 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); |
| 4390 if (enable) |
| 4391 pfvfspoof |= (1 << vf_target_shift); 4392 else 4393 pfvfspoof &= ~(1 << vf_target_shift); 4394 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); |
| 4395} 4396 4397/** 4398 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4399 * @hw: pointer to hardware structure 4400 * @enable: enable or disable switch for VLAN anti-spoofing 4401 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4402 * --- 79 unchanged lines hidden (view full) --- 4482 4483 for (i = 0; i < length; i++) 4484 sum += buffer[i]; 4485 4486 return (u8) (0 - sum); 4487} 4488 4489/** |
| 4490 * ixgbe_hic_unlocked - Issue command to manageability block unlocked |
| 4491 * @hw: pointer to the HW structure |
| 4492 * @buffer: command to write and where the return status will be placed |
| 4493 * @length: length of buffer, must be multiple of 4 bytes 4494 * @timeout: time in ms to wait for command completion |
| 4495 * |
| 4496 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4497 * else returns semaphore error when encountering an error acquiring 4498 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4499 * 4500 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4501 * by the caller. |
| 4502 **/ |
| 4503s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4504 u32 timeout) |
| 4505{ |
| 4506 u32 hicr, i, fwsts; |
| 4507 u16 dword_len; 4508 |
| 4509 DEBUGFUNC("ixgbe_hic_unlocked"); |
| 4510 |
| 4511 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { |
| 4512 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4513 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4514 } |
| 4515 |
| 4516 /* Set bit 9 of FWSTS clearing FW reset indication */ 4517 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4518 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4519 4520 /* Check that the host interface is enabled. */ 4521 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); |
| 4522 if (!(hicr & IXGBE_HICR_EN)) { |
| 4523 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4524 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4525 } 4526 4527 /* Calculate length in DWORDs. We must be DWORD aligned */ |
| 4528 if (length % sizeof(u32)) { |
| 4529 DEBUGOUT("Buffer length failure, not aligned to dword"); 4530 return IXGBE_ERR_INVALID_ARGUMENT; 4531 } 4532 4533 dword_len = length >> 2; 4534 4535 /* The device driver writes the relevant command block 4536 * into the ram area. --- 8 unchanged lines hidden (view full) --- 4545 for (i = 0; i < timeout; i++) { 4546 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4547 if (!(hicr & IXGBE_HICR_C)) 4548 break; 4549 msec_delay(1); 4550 } 4551 4552 /* Check command completion */ |
| 4553 if ((timeout && i == timeout) || |
| 4554 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4555 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4556 "Command has failed with no status valid.\n"); 4557 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4558 } 4559 |
| 4560 return IXGBE_SUCCESS; 4561} 4562 4563/** 4564 * ixgbe_host_interface_command - Issue command to manageability block 4565 * @hw: pointer to the HW structure 4566 * @buffer: contains the command to write and where the return status will 4567 * be placed 4568 * @length: length of buffer, must be multiple of 4 bytes 4569 * @timeout: time in ms to wait for command completion 4570 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4571 * Needed because FW structures are big endian and decoding of 4572 * these fields can be 8 bit or 16 bit based on command. Decoding 4573 * is not easily understood without making a table of commands. 4574 * So we will leave this up to the caller to read back the data 4575 * in these cases. 4576 * 4577 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4578 * else returns semaphore error when encountering an error acquiring 4579 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4580 **/ 4581s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4582 u32 length, u32 timeout, bool return_data) 4583{ 4584 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4585 u16 dword_len; 4586 u16 buf_len; 4587 s32 status; 4588 u32 bi; 4589 4590 DEBUGFUNC("ixgbe_host_interface_command"); 4591 4592 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4593 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4594 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4595 } 4596 4597 /* Take management host interface semaphore */ 4598 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4599 if (status) 4600 return status; 4601 4602 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4603 if (status) 4604 goto rel_out; 4605 |
| 4606 if (!return_data) |
| 4607 goto rel_out; |
| 4608 4609 /* Calculate length in DWORDs */ 4610 dword_len = hdr_size >> 2; 4611 4612 /* first pull in the header so we know the buffer length */ 4613 for (bi = 0; bi < dword_len; bi++) { 4614 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4615 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4616 } 4617 4618 /* If there is any thing in data position pull it in */ 4619 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; |
| 4620 if (!buf_len) 4621 goto rel_out; |
| 4622 4623 if (length < buf_len + hdr_size) { 4624 DEBUGOUT("Buffer not large enough for reply message.\n"); |
| 4625 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4626 goto rel_out; |
| 4627 } 4628 4629 /* Calculate length in DWORDs, add 3 for odd lengths */ 4630 dword_len = (buf_len + 3) >> 2; 4631 4632 /* Pull in the rest of the buffer (bi is where we left off) */ 4633 for (; bi <= dword_len; bi++) { 4634 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4635 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4636 } 4637 |
| 4638rel_out: 4639 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4640 4641 return status; |
| 4642} 4643 4644/** 4645 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4646 * @hw: pointer to the HW structure 4647 * @maj: driver version major number 4648 * @min: driver version minor number 4649 * @build: driver version build number 4650 * @sub: driver version sub build number 4651 * 4652 * Sends driver version number to firmware through the manageability 4653 * block. On success return IXGBE_SUCCESS 4654 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4655 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4656 **/ 4657s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, |
| 4658 u8 build, u8 sub, u16 len, 4659 const char *driver_ver) |
| 4660{ 4661 struct ixgbe_hic_drv_info fw_cmd; 4662 int i; 4663 s32 ret_val = IXGBE_SUCCESS; 4664 4665 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); |
| 4666 UNREFERENCED_2PARAMETER(len, driver_ver); |
| 4667 |
| 4668 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4669 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4670 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4671 fw_cmd.port_num = (u8)hw->bus.func; 4672 fw_cmd.ver_maj = maj; 4673 fw_cmd.ver_min = min; 4674 fw_cmd.ver_build = build; 4675 fw_cmd.ver_sub = sub; --- 15 unchanged lines hidden (view full) --- 4691 FW_CEM_RESP_STATUS_SUCCESS) 4692 ret_val = IXGBE_SUCCESS; 4693 else 4694 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4695 4696 break; 4697 } 4698 |
| 4699 return ret_val; 4700} 4701 4702/** 4703 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4704 * @hw: pointer to hardware structure 4705 * @num_pb: number of packet buffers to allocate 4706 * @headroom: reserve n KB of headroom --- 20 unchanged lines hidden (view full) --- 4727 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4728 * buffer with 5/8 of the packet buffer space. 4729 */ 4730 rxpktsize = (pbsize * 5) / (num_pb * 4); 4731 pbsize -= rxpktsize * (num_pb / 2); 4732 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4733 for (; i < (num_pb / 2); i++) 4734 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); |
| 4735 /* fall through - configure remaining packet buffers */ |
| 4736 case PBA_STRATEGY_EQUAL: 4737 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4738 for (; i < num_pb; i++) 4739 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4740 break; 4741 default: 4742 break; 4743 } --- 70 unchanged lines hidden (view full) --- 4814 IXGBE_WRITE_FLUSH(hw); 4815 usec_delay(20); 4816 4817 /* restore previous register values */ 4818 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4819 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4820} 4821 |
| 4822/** 4823 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 4824 * 4825 * @hw: pointer to hardware structure 4826 * @cmd: Command we send to the FW 4827 * @status: The reply from the FW 4828 * 4829 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 4830 **/ 4831#define IXGBE_BYPASS_BB_WAIT 1 4832s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 4833{ 4834 int i; 4835 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 4836 u32 esdp; |
| 4837 |
| 4838 if (!status) 4839 return IXGBE_ERR_PARAM; 4840 4841 *status = 0; 4842 4843 /* SDP vary by MAC type */ 4844 switch (hw->mac.type) { 4845 case ixgbe_mac_82599EB: 4846 sck = IXGBE_ESDP_SDP7; 4847 sdi = IXGBE_ESDP_SDP0; 4848 sdo = IXGBE_ESDP_SDP6; 4849 dir_sck = IXGBE_ESDP_SDP7_DIR; 4850 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4851 dir_sdo = IXGBE_ESDP_SDP6_DIR; 4852 break; 4853 case ixgbe_mac_X540: 4854 sck = IXGBE_ESDP_SDP2; 4855 sdi = IXGBE_ESDP_SDP0; 4856 sdo = IXGBE_ESDP_SDP1; 4857 dir_sck = IXGBE_ESDP_SDP2_DIR; 4858 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4859 dir_sdo = IXGBE_ESDP_SDP1_DIR; 4860 break; 4861 default: 4862 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 4863 } 4864 4865 /* Set SDP pins direction */ 4866 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4867 esdp |= dir_sck; /* SCK as output */ 4868 esdp |= dir_sdi; /* SDI as output */ 4869 esdp &= ~dir_sdo; /* SDO as input */ 4870 esdp |= sck; 4871 esdp |= sdi; 4872 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4873 IXGBE_WRITE_FLUSH(hw); 4874 msec_delay(IXGBE_BYPASS_BB_WAIT); 4875 4876 /* Generate start condition */ 4877 esdp &= ~sdi; 4878 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4879 IXGBE_WRITE_FLUSH(hw); 4880 msec_delay(IXGBE_BYPASS_BB_WAIT); 4881 4882 esdp &= ~sck; 4883 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4884 IXGBE_WRITE_FLUSH(hw); 4885 msec_delay(IXGBE_BYPASS_BB_WAIT); 4886 4887 /* Clock out the new control word and clock in the status */ 4888 for (i = 0; i < 32; i++) { 4889 if ((cmd >> (31 - i)) & 0x01) { 4890 esdp |= sdi; 4891 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4892 } else { 4893 esdp &= ~sdi; 4894 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4895 } 4896 IXGBE_WRITE_FLUSH(hw); 4897 msec_delay(IXGBE_BYPASS_BB_WAIT); 4898 4899 esdp |= sck; 4900 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4901 IXGBE_WRITE_FLUSH(hw); 4902 msec_delay(IXGBE_BYPASS_BB_WAIT); 4903 4904 esdp &= ~sck; 4905 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4906 IXGBE_WRITE_FLUSH(hw); 4907 msec_delay(IXGBE_BYPASS_BB_WAIT); 4908 4909 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4910 if (esdp & sdo) 4911 *status = (*status << 1) | 0x01; 4912 else 4913 *status = (*status << 1) | 0x00; 4914 msec_delay(IXGBE_BYPASS_BB_WAIT); 4915 } 4916 4917 /* stop condition */ 4918 esdp |= sck; 4919 esdp &= ~sdi; 4920 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4921 IXGBE_WRITE_FLUSH(hw); 4922 msec_delay(IXGBE_BYPASS_BB_WAIT); 4923 4924 esdp |= sdi; 4925 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4926 IXGBE_WRITE_FLUSH(hw); 4927 4928 /* set the page bits to match the cmd that the status it belongs to */ 4929 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 4930 4931 return IXGBE_SUCCESS; 4932} 4933 |
| 4934/** |
| 4935 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 4936 * 4937 * If we send a write we can't be sure it took until we can read back 4938 * that same register. It can be a problem as some of the feilds may 4939 * for valid reasons change inbetween the time wrote the register and 4940 * we read it again to verify. So this function check everything we 4941 * can check and then assumes it worked. 4942 * 4943 * @u32 in_reg - The register cmd for the bit-bang read. 4944 * @u32 out_reg - The register returned from a bit-bang read. 4945 **/ 4946bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 4947{ 4948 u32 mask; 4949 4950 /* Page must match for all control pages */ 4951 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 4952 return FALSE; 4953 4954 switch (in_reg & BYPASS_PAGE_M) { 4955 case BYPASS_PAGE_CTL0: 4956 /* All the following can't change since the last write 4957 * - All the event actions 4958 * - The timeout value 4959 */ 4960 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 4961 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 4962 BYPASS_WDTIMEOUT_M | 4963 BYPASS_WDT_VALUE_M; 4964 if ((out_reg & mask) != (in_reg & mask)) 4965 return FALSE; 4966 4967 /* 0x0 is never a valid value for bypass status */ 4968 if (!(out_reg & BYPASS_STATUS_OFF_M)) 4969 return FALSE; 4970 break; 4971 case BYPASS_PAGE_CTL1: 4972 /* All the following can't change since the last write 4973 * - time valid bit 4974 * - time we last sent 4975 */ 4976 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 4977 if ((out_reg & mask) != (in_reg & mask)) 4978 return FALSE; 4979 break; 4980 case BYPASS_PAGE_CTL2: 4981 /* All we can check in this page is control number 4982 * which is already done above. 4983 */ 4984 break; 4985 } 4986 4987 /* We are as sure as we can be return TRUE */ 4988 return TRUE; 4989} 4990 4991/** 4992 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 4993 * 4994 * @hw: pointer to hardware structure 4995 * @cmd: The control word we are setting. 4996 * @event: The event we are setting in the FW. This also happens to 4997 * be the mask for the event we are setting (handy) 4998 * @action: The action we set the event to in the FW. This is in a 4999 * bit field that happens to be what we want to put in 5000 * the event spot (also handy) 5001 **/ 5002s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5003 u32 action) 5004{ 5005 u32 by_ctl = 0; 5006 u32 cmd, verify; 5007 u32 count = 0; 5008 5009 /* Get current values */ 5010 cmd = ctrl; /* just reading only need control number */ 5011 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5012 return IXGBE_ERR_INVALID_ARGUMENT; 5013 5014 /* Set to new action */ 5015 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5016 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5017 return IXGBE_ERR_INVALID_ARGUMENT; 5018 5019 /* Page 0 force a FW eeprom write which is slow so verify */ 5020 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5021 verify = BYPASS_PAGE_CTL0; 5022 do { 5023 if (count++ > 5) 5024 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5025 5026 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5027 return IXGBE_ERR_INVALID_ARGUMENT; 5028 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5029 } else { 5030 /* We have give the FW time for the write to stick */ 5031 msec_delay(100); 5032 } 5033 5034 return IXGBE_SUCCESS; 5035} 5036 5037/** 5038 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5039 * 5040 * @hw: pointer to hardware structure 5041 * @addr: The bypass eeprom address to read. 5042 * @value: The 8b of data at the address above. 5043 **/ 5044s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5045{ 5046 u32 cmd; 5047 u32 status; 5048 5049 5050 /* send the request */ 5051 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5052 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5053 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5054 return IXGBE_ERR_INVALID_ARGUMENT; 5055 5056 /* We have give the FW time for the write to stick */ 5057 msec_delay(100); 5058 5059 /* now read the results */ 5060 cmd &= ~BYPASS_WE; 5061 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5062 return IXGBE_ERR_INVALID_ARGUMENT; 5063 5064 *value = status & BYPASS_CTL2_DATA_M; 5065 5066 return IXGBE_SUCCESS; 5067} 5068 5069 5070/** |
| 5071 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5072 * @hw: pointer to hardware structure 5073 * @map: pointer to u8 arr for returning map 5074 * 5075 * Read the rtrup2tc HW register and resolve its content into map 5076 **/ 5077void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5078{ --- 119 unchanged lines hidden (view full) --- 5198 5199 /* Try each speed one by one, highest priority first. We do this in 5200 * software because 10Gb fiber doesn't support speed autonegotiation. 5201 */ 5202 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5203 speedcnt++; 5204 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5205 |
| 5206 /* Set the module link speed */ 5207 switch (hw->phy.media_type) { 5208 case ixgbe_media_type_fiber_fixed: 5209 case ixgbe_media_type_fiber: 5210 ixgbe_set_rate_select_speed(hw, 5211 IXGBE_LINK_SPEED_10GB_FULL); 5212 break; 5213 case ixgbe_media_type_fiber_qsfp: --- 35 unchanged lines hidden (view full) --- 5249 } 5250 } 5251 5252 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5253 speedcnt++; 5254 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5255 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5256 |
| 5257 /* Set the module link speed */ 5258 switch (hw->phy.media_type) { 5259 case ixgbe_media_type_fiber_fixed: 5260 case ixgbe_media_type_fiber: 5261 ixgbe_set_rate_select_speed(hw, 5262 IXGBE_LINK_SPEED_1GB_FULL); 5263 break; 5264 case ixgbe_media_type_fiber_qsfp: --- 119 unchanged lines hidden --- |