1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_api.c 299200 2016-05-06 22:54:56Z pfg $*/
34
35#include "ixgbe_api.h"
36#include "ixgbe_common.h"
37
38#define IXGBE_EMPTY_PARAM
39
40static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {
41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM)
--- 6 unchanged lines hidden (view full) ---
48static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
49 IXGBE_MVALS_INIT(_X550)
50};
51
52static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
53 IXGBE_MVALS_INIT(_X550EM_x)
54};
55
56/**
57 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
58 * @hw: pointer to hardware structure
59 * @map: pointer to u8 arr for returning map
60 *
61 * Read the rtrup2tc HW register and resolve its content into map
62 **/
63void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
--- 34 unchanged lines hidden (view full) ---
98 break;
99 case ixgbe_mac_X540:
100 status = ixgbe_init_ops_X540(hw);
101 break;
102 case ixgbe_mac_X550:
103 status = ixgbe_init_ops_X550(hw);
104 break;
105 case ixgbe_mac_X550EM_x:
106 status = ixgbe_init_ops_X550EM(hw);
107 break;
108 case ixgbe_mac_82599_vf:
109 case ixgbe_mac_X540_vf:
110 case ixgbe_mac_X550_vf:
111 case ixgbe_mac_X550EM_x_vf:
112 status = ixgbe_init_ops_vf(hw);
113 break;
114 default:
115 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
116 break;
117 }
118 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;
119
120 return status;
--- 48 unchanged lines hidden (view full) ---
169 case IXGBE_DEV_ID_82599_SFP_SF_QP:
170 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
171 case IXGBE_DEV_ID_82599EN_SFP:
172 case IXGBE_DEV_ID_82599_CX4:
173 case IXGBE_DEV_ID_82599_BYPASS:
174 case IXGBE_DEV_ID_82599_T3_LOM:
175 hw->mac.type = ixgbe_mac_82599EB;
176 break;
177 case IXGBE_DEV_ID_82599_VF:
178 case IXGBE_DEV_ID_82599_VF_HV:
179 hw->mac.type = ixgbe_mac_82599_vf;
180 break;
181 case IXGBE_DEV_ID_X540_VF:
182 case IXGBE_DEV_ID_X540_VF_HV:
183 hw->mac.type = ixgbe_mac_X540_vf;
184 hw->mvals = ixgbe_mvals_X540;
185 break;
186 case IXGBE_DEV_ID_X540T:
187 case IXGBE_DEV_ID_X540T1:
188 case IXGBE_DEV_ID_X540_BYPASS:
189 hw->mac.type = ixgbe_mac_X540;
190 hw->mvals = ixgbe_mvals_X540;
191 break;
192 case IXGBE_DEV_ID_X550T:
193 case IXGBE_DEV_ID_X550T1:
194 hw->mac.type = ixgbe_mac_X550;
195 hw->mvals = ixgbe_mvals_X550;
196 break;
197 case IXGBE_DEV_ID_X550EM_X_KX4:
198 case IXGBE_DEV_ID_X550EM_X_KR:
199 case IXGBE_DEV_ID_X550EM_X_10G_T:
200 case IXGBE_DEV_ID_X550EM_X_1G_T:
201 case IXGBE_DEV_ID_X550EM_X_SFP:
202 hw->mac.type = ixgbe_mac_X550EM_x;
203 hw->mvals = ixgbe_mvals_X550EM_x;
204 break;
205 case IXGBE_DEV_ID_X550_VF:
206 case IXGBE_DEV_ID_X550_VF_HV:
207 hw->mac.type = ixgbe_mac_X550_vf;
208 hw->mvals = ixgbe_mvals_X550;
209 break;
210 case IXGBE_DEV_ID_X550EM_X_VF:
211 case IXGBE_DEV_ID_X550EM_X_VF_HV:
212 hw->mac.type = ixgbe_mac_X550EM_x_vf;
213 hw->mvals = ixgbe_mvals_X550EM_x;
214 break;
215 default:
216 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
217 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
218 "Unsupported device id: %x",
219 hw->device_id);
220 break;
221 }
222
--- 829 unchanged lines hidden (view full) ---
1052 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
1053 IXGBE_NOT_IMPLEMENTED);
1054}
1055
1056/**
1057 * ixgbe_set_vfta - Set VLAN filter table
1058 * @hw: pointer to hardware structure
1059 * @vlan: VLAN id to write to VLAN filter
1060 * @vind: VMDq output index that maps queue to VLAN id in VFTA
1061 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1062 *
1063 * Turn on/off specified VLAN in the VLAN filter table.
1064 **/
1065s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
1066{
1067 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
1068 vlan_on), IXGBE_NOT_IMPLEMENTED);
1069}
1070
1071/**
1072 * ixgbe_set_vlvf - Set VLAN Pool Filter
1073 * @hw: pointer to hardware structure
1074 * @vlan: VLAN id to write to VLAN filter
1075 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1076 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1077 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
1078 * should be changed
1079 *
1080 * Turn on/off specified bit in VLVF table.
1081 **/
1082s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
1083 bool *vfta_changed)
1084{
1085 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
1086 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
1087}
1088
1089/**
1090 * ixgbe_fc_enable - Enable flow control
1091 * @hw: pointer to hardware structure
1092 *
1093 * Configures the flow control settings based on SW configuration.
1094 **/
--- 17 unchanged lines hidden (view full) ---
1112
1113/**
1114 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1115 * @hw: pointer to hardware structure
1116 * @maj: driver major number to be sent to firmware
1117 * @min: driver minor number to be sent to firmware
1118 * @build: driver build number to be sent to firmware
1119 * @ver: driver version number to be sent to firmware
1120 **/
1121s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1122 u8 ver)
1123{
1124 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1125 build, ver), IXGBE_NOT_IMPLEMENTED);
1126}
1127
1128
1129
1130/**
1131 * ixgbe_dmac_config - Configure DMA Coalescing registers.
1132 * @hw: pointer to hardware structure
1133 *
--- 178 unchanged lines hidden (view full) ---
1312 */
1313s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)
1314{
1315 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),
1316 IXGBE_NOT_IMPLEMENTED);
1317}
1318
1319/**
1320 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1321 * @hw: pointer to hardware structure
1322 * @reg: analog register to read
1323 * @val: read value
1324 *
1325 * Performs write operation to analog register specified.
1326 **/
1327s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
--- 58 unchanged lines hidden (view full) ---
1386 u8 dev_addr, u8 *data)
1387{
1388 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,
1389 (hw, byte_offset, dev_addr, data),
1390 IXGBE_NOT_IMPLEMENTED);
1391}
1392
1393/**
1394 * ixgbe_read_i2c_combined - Perform I2C read combined operation
1395 * @hw: pointer to the hardware structure
1396 * @addr: I2C bus address to read from
1397 * @reg: I2C device register to read from
1398 * @val: pointer to location to receive read value
1399 *
1400 * Returns an error code on error.
1401 */
1402s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1403{
1404 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,
1405 reg, val), IXGBE_NOT_IMPLEMENTED);
1406}
1407
1408/**
1409 * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation
1410 * @hw: pointer to the hardware structure
1411 * @addr: I2C bus address to read from
1412 * @reg: I2C device register to read from
1413 * @val: pointer to location to receive read value
1414 *
1415 * Returns an error code on error.
1416 **/
1417s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1418 u16 *val)
1419{
1420 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked,
1421 (hw, addr, reg, val),
1422 IXGBE_NOT_IMPLEMENTED);
1423}
1424
1425/**
1426 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1427 * @hw: pointer to hardware structure
1428 * @byte_offset: byte offset to write
1429 * @dev_addr: I2C bus address to write to
1430 * @data: value to write
--- 22 unchanged lines hidden (view full) ---
1453 u8 dev_addr, u8 data)
1454{
1455 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,
1456 (hw, byte_offset, dev_addr, data),
1457 IXGBE_NOT_IMPLEMENTED);
1458}
1459
1460/**
1461 * ixgbe_write_i2c_combined - Perform I2C write combined operation
1462 * @hw: pointer to the hardware structure
1463 * @addr: I2C bus address to write to
1464 * @reg: I2C device register to write to
1465 * @val: value to write
1466 *
1467 * Returns an error code on error.
1468 */
1469s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1470{
1471 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,
1472 reg, val), IXGBE_NOT_IMPLEMENTED);
1473}
1474
1475/**
1476 * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation
1477 * @hw: pointer to the hardware structure
1478 * @addr: I2C bus address to write to
1479 * @reg: I2C device register to write to
1480 * @val: value to write
1481 *
1482 * Returns an error code on error.
1483 **/
1484s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1485 u16 val)
1486{
1487 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked,
1488 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1489}
1490
1491/**
1492 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1493 * @hw: pointer to hardware structure
1494 * @byte_offset: EEPROM byte offset to write
1495 * @eeprom_data: value to write
--- 24 unchanged lines hidden (view full) ---
1520}
1521
1522/**
1523 * ixgbe_get_supported_physical_layer - Returns physical layer type
1524 * @hw: pointer to hardware structure
1525 *
1526 * Determines physical layer capabilities of the current configuration.
1527 **/
1528u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1529{
1530 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1531 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1532}
1533
1534/**
1535 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1536 * @hw: pointer to hardware structure
--- 54 unchanged lines hidden (view full) ---
1591 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1592 **/
1593void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1594{
1595 if (hw->mac.ops.release_swfw_sync)
1596 hw->mac.ops.release_swfw_sync(hw, mask);
1597}
1598
1599
1600void ixgbe_disable_rx(struct ixgbe_hw *hw)
1601{
1602 if (hw->mac.ops.disable_rx)
1603 hw->mac.ops.disable_rx(hw);
1604}
1605
1606void ixgbe_enable_rx(struct ixgbe_hw *hw)
1607{
--- 16 unchanged lines hidden ---
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_api.c 299200 2016-05-06 22:54:56Z pfg $*/
34
35#include "ixgbe_api.h"
36#include "ixgbe_common.h"
37
38#define IXGBE_EMPTY_PARAM
39
40static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {
41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM)
--- 6 unchanged lines hidden (view full) ---
48static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
49 IXGBE_MVALS_INIT(_X550)
50};
51
52static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
53 IXGBE_MVALS_INIT(_X550EM_x)
54};
55
56/**
57 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
58 * @hw: pointer to hardware structure
59 * @map: pointer to u8 arr for returning map
60 *
61 * Read the rtrup2tc HW register and resolve its content into map
62 **/
63void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
--- 34 unchanged lines hidden (view full) ---
98 break;
99 case ixgbe_mac_X540:
100 status = ixgbe_init_ops_X540(hw);
101 break;
102 case ixgbe_mac_X550:
103 status = ixgbe_init_ops_X550(hw);
104 break;
105 case ixgbe_mac_X550EM_x:
106 status = ixgbe_init_ops_X550EM(hw);
107 break;
108 case ixgbe_mac_82599_vf:
109 case ixgbe_mac_X540_vf:
110 case ixgbe_mac_X550_vf:
111 case ixgbe_mac_X550EM_x_vf:
112 status = ixgbe_init_ops_vf(hw);
113 break;
114 default:
115 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
116 break;
117 }
118 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;
119
120 return status;
--- 48 unchanged lines hidden (view full) ---
169 case IXGBE_DEV_ID_82599_SFP_SF_QP:
170 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
171 case IXGBE_DEV_ID_82599EN_SFP:
172 case IXGBE_DEV_ID_82599_CX4:
173 case IXGBE_DEV_ID_82599_BYPASS:
174 case IXGBE_DEV_ID_82599_T3_LOM:
175 hw->mac.type = ixgbe_mac_82599EB;
176 break;
177 case IXGBE_DEV_ID_82599_VF:
178 case IXGBE_DEV_ID_82599_VF_HV:
179 hw->mac.type = ixgbe_mac_82599_vf;
180 break;
181 case IXGBE_DEV_ID_X540_VF:
182 case IXGBE_DEV_ID_X540_VF_HV:
183 hw->mac.type = ixgbe_mac_X540_vf;
184 hw->mvals = ixgbe_mvals_X540;
185 break;
186 case IXGBE_DEV_ID_X540T:
187 case IXGBE_DEV_ID_X540T1:
188 case IXGBE_DEV_ID_X540_BYPASS:
189 hw->mac.type = ixgbe_mac_X540;
190 hw->mvals = ixgbe_mvals_X540;
191 break;
192 case IXGBE_DEV_ID_X550T:
193 case IXGBE_DEV_ID_X550T1:
194 hw->mac.type = ixgbe_mac_X550;
195 hw->mvals = ixgbe_mvals_X550;
196 break;
197 case IXGBE_DEV_ID_X550EM_X_KX4:
198 case IXGBE_DEV_ID_X550EM_X_KR:
199 case IXGBE_DEV_ID_X550EM_X_10G_T:
200 case IXGBE_DEV_ID_X550EM_X_1G_T:
201 case IXGBE_DEV_ID_X550EM_X_SFP:
202 hw->mac.type = ixgbe_mac_X550EM_x;
203 hw->mvals = ixgbe_mvals_X550EM_x;
204 break;
205 case IXGBE_DEV_ID_X550_VF:
206 case IXGBE_DEV_ID_X550_VF_HV:
207 hw->mac.type = ixgbe_mac_X550_vf;
208 hw->mvals = ixgbe_mvals_X550;
209 break;
210 case IXGBE_DEV_ID_X550EM_X_VF:
211 case IXGBE_DEV_ID_X550EM_X_VF_HV:
212 hw->mac.type = ixgbe_mac_X550EM_x_vf;
213 hw->mvals = ixgbe_mvals_X550EM_x;
214 break;
215 default:
216 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
217 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
218 "Unsupported device id: %x",
219 hw->device_id);
220 break;
221 }
222
--- 829 unchanged lines hidden (view full) ---
1052 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
1053 IXGBE_NOT_IMPLEMENTED);
1054}
1055
1056/**
1057 * ixgbe_set_vfta - Set VLAN filter table
1058 * @hw: pointer to hardware structure
1059 * @vlan: VLAN id to write to VLAN filter
1060 * @vind: VMDq output index that maps queue to VLAN id in VFTA
1061 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1062 *
1063 * Turn on/off specified VLAN in the VLAN filter table.
1064 **/
1065s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
1066{
1067 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
1068 vlan_on), IXGBE_NOT_IMPLEMENTED);
1069}
1070
1071/**
1072 * ixgbe_set_vlvf - Set VLAN Pool Filter
1073 * @hw: pointer to hardware structure
1074 * @vlan: VLAN id to write to VLAN filter
1075 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1076 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1077 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
1078 * should be changed
1079 *
1080 * Turn on/off specified bit in VLVF table.
1081 **/
1082s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
1083 bool *vfta_changed)
1084{
1085 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
1086 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
1087}
1088
1089/**
1090 * ixgbe_fc_enable - Enable flow control
1091 * @hw: pointer to hardware structure
1092 *
1093 * Configures the flow control settings based on SW configuration.
1094 **/
--- 17 unchanged lines hidden (view full) ---
1112
1113/**
1114 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1115 * @hw: pointer to hardware structure
1116 * @maj: driver major number to be sent to firmware
1117 * @min: driver minor number to be sent to firmware
1118 * @build: driver build number to be sent to firmware
1119 * @ver: driver version number to be sent to firmware
1120 **/
1121s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1122 u8 ver)
1123{
1124 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1125 build, ver), IXGBE_NOT_IMPLEMENTED);
1126}
1127
1128
1129
1130/**
1131 * ixgbe_dmac_config - Configure DMA Coalescing registers.
1132 * @hw: pointer to hardware structure
1133 *
--- 178 unchanged lines hidden (view full) ---
1312 */
1313s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)
1314{
1315 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),
1316 IXGBE_NOT_IMPLEMENTED);
1317}
1318
1319/**
1320 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1321 * @hw: pointer to hardware structure
1322 * @reg: analog register to read
1323 * @val: read value
1324 *
1325 * Performs write operation to analog register specified.
1326 **/
1327s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
--- 58 unchanged lines hidden (view full) ---
1386 u8 dev_addr, u8 *data)
1387{
1388 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,
1389 (hw, byte_offset, dev_addr, data),
1390 IXGBE_NOT_IMPLEMENTED);
1391}
1392
1393/**
1394 * ixgbe_read_i2c_combined - Perform I2C read combined operation
1395 * @hw: pointer to the hardware structure
1396 * @addr: I2C bus address to read from
1397 * @reg: I2C device register to read from
1398 * @val: pointer to location to receive read value
1399 *
1400 * Returns an error code on error.
1401 */
1402s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1403{
1404 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,
1405 reg, val), IXGBE_NOT_IMPLEMENTED);
1406}
1407
1408/**
1409 * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation
1410 * @hw: pointer to the hardware structure
1411 * @addr: I2C bus address to read from
1412 * @reg: I2C device register to read from
1413 * @val: pointer to location to receive read value
1414 *
1415 * Returns an error code on error.
1416 **/
1417s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1418 u16 *val)
1419{
1420 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked,
1421 (hw, addr, reg, val),
1422 IXGBE_NOT_IMPLEMENTED);
1423}
1424
1425/**
1426 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1427 * @hw: pointer to hardware structure
1428 * @byte_offset: byte offset to write
1429 * @dev_addr: I2C bus address to write to
1430 * @data: value to write
--- 22 unchanged lines hidden (view full) ---
1453 u8 dev_addr, u8 data)
1454{
1455 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,
1456 (hw, byte_offset, dev_addr, data),
1457 IXGBE_NOT_IMPLEMENTED);
1458}
1459
1460/**
1461 * ixgbe_write_i2c_combined - Perform I2C write combined operation
1462 * @hw: pointer to the hardware structure
1463 * @addr: I2C bus address to write to
1464 * @reg: I2C device register to write to
1465 * @val: value to write
1466 *
1467 * Returns an error code on error.
1468 */
1469s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1470{
1471 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,
1472 reg, val), IXGBE_NOT_IMPLEMENTED);
1473}
1474
1475/**
1476 * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation
1477 * @hw: pointer to the hardware structure
1478 * @addr: I2C bus address to write to
1479 * @reg: I2C device register to write to
1480 * @val: value to write
1481 *
1482 * Returns an error code on error.
1483 **/
1484s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,
1485 u16 val)
1486{
1487 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked,
1488 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1489}
1490
1491/**
1492 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1493 * @hw: pointer to hardware structure
1494 * @byte_offset: EEPROM byte offset to write
1495 * @eeprom_data: value to write
--- 24 unchanged lines hidden (view full) ---
1520}
1521
1522/**
1523 * ixgbe_get_supported_physical_layer - Returns physical layer type
1524 * @hw: pointer to hardware structure
1525 *
1526 * Determines physical layer capabilities of the current configuration.
1527 **/
1528u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1529{
1530 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1531 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1532}
1533
1534/**
1535 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1536 * @hw: pointer to hardware structure
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1591 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1592 **/
1593void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1594{
1595 if (hw->mac.ops.release_swfw_sync)
1596 hw->mac.ops.release_swfw_sync(hw, mask);
1597}
1598
1599
1600void ixgbe_disable_rx(struct ixgbe_hw *hw)
1601{
1602 if (hw->mac.ops.disable_rx)
1603 hw->mac.ops.disable_rx(hw);
1604}
1605
1606void ixgbe_enable_rx(struct ixgbe_hw *hw)
1607{
--- 16 unchanged lines hidden ---