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ixgbe_82599.c (302408) ixgbe_82599.c (320897)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
18 this software without specific prior written permission.
19
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_82599.c 292674 2015-12-23 22:45:17Z sbruno $*/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_82599.c 320897 2017-07-11 21:25:07Z erj $*/
34
35#include "ixgbe_type.h"
36#include "ixgbe_82599.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41#define IXGBE_82599_MAX_TX_QUEUES 128

--- 347 unchanged lines hidden (view full) ---

389
390 /* EEPROM */
391 eeprom->ops.read = ixgbe_read_eeprom_82599;
392 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
393
394 /* Manageability interface */
395 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
396
34
35#include "ixgbe_type.h"
36#include "ixgbe_82599.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41#define IXGBE_82599_MAX_TX_QUEUES 128

--- 347 unchanged lines hidden (view full) ---

389
390 /* EEPROM */
391 eeprom->ops.read = ixgbe_read_eeprom_82599;
392 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
393
394 /* Manageability interface */
395 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
396
397 mac->ops.bypass_rw = ixgbe_bypass_rw_generic;
398 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic;
399 mac->ops.bypass_set = ixgbe_bypass_set_generic;
400 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic;
397
398 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
399
400 return ret_val;
401}
402
403/**
404 * ixgbe_get_link_capabilities_82599 - Determines link capabilities

--- 767 unchanged lines hidden (view full) ---

1172 hw->mac.num_rar_entries = 128;
1173 hw->mac.ops.init_rx_addrs(hw);
1174
1175 /* Store the permanent SAN mac address */
1176 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1177
1178 /* Add the SAN MAC address to the RAR only if it's a valid address */
1179 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
401
402 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
403
404 return ret_val;
405}
406
407/**
408 * ixgbe_get_link_capabilities_82599 - Determines link capabilities

--- 767 unchanged lines hidden (view full) ---

1176 hw->mac.num_rar_entries = 128;
1177 hw->mac.ops.init_rx_addrs(hw);
1178
1179 /* Store the permanent SAN mac address */
1180 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1181
1182 /* Add the SAN MAC address to the RAR only if it's a valid address */
1183 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1180 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1181 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1182
1183 /* Save the SAN MAC RAR index */
1184 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1185
1184 /* Save the SAN MAC RAR index */
1185 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1186
1187 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
1188 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1189
1190 /* clear VMDq pool/queue selection for this RAR */
1191 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1192 IXGBE_CLEAR_VMDQ_ALL);
1193
1186 /* Reserve the last RAR for the SAN MAC address */
1187 hw->mac.num_rar_entries--;
1188 }
1189
1190 /* Store the alternative WWNN/WWPN prefix */
1191 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1192 &hw->mac.wwpn_prefix);
1193

--- 182 unchanged lines hidden (view full) ---

1376 * Send interrupt when 64 (0x4 * 16) filters are left
1377 */
1378 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1379 IXGBE_FDIRCTRL_REPORT_STATUS |
1380 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1381 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1382 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1383 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1194 /* Reserve the last RAR for the SAN MAC address */
1195 hw->mac.num_rar_entries--;
1196 }
1197
1198 /* Store the alternative WWNN/WWPN prefix */
1199 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1200 &hw->mac.wwpn_prefix);
1201

--- 182 unchanged lines hidden (view full) ---

1384 * Send interrupt when 64 (0x4 * 16) filters are left
1385 */
1386 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1387 IXGBE_FDIRCTRL_REPORT_STATUS |
1388 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1389 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1390 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1391 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1384 if ((hw->mac.type == ixgbe_mac_X550) ||
1385 (hw->mac.type == ixgbe_mac_X550EM_x))
1386 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1387
1388 if (cloud_mode)
1389 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1390 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1391
1392 /* write hashes and fdirctrl register, poll for completion */
1393 ixgbe_fdir_enable_82599(hw, fdirctrl);
1394

--- 12 unchanged lines hidden (view full) ---

1407 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
1408 /* Clear init done bit and drop queue field */
1409 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1410 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE);
1411
1412 /* Set drop queue */
1413 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1414 if ((hw->mac.type == ixgbe_mac_X550) ||
1392
1393 if (cloud_mode)
1394 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1395 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1396
1397 /* write hashes and fdirctrl register, poll for completion */
1398 ixgbe_fdir_enable_82599(hw, fdirctrl);
1399

--- 12 unchanged lines hidden (view full) ---

1412 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
1413 /* Clear init done bit and drop queue field */
1414 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1415 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE);
1416
1417 /* Set drop queue */
1418 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1419 if ((hw->mac.type == ixgbe_mac_X550) ||
1415 (hw->mac.type == ixgbe_mac_X550EM_x))
1420 (hw->mac.type == ixgbe_mac_X550EM_x) ||
1421 (hw->mac.type == ixgbe_mac_X550EM_a))
1416 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1417
1418 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1419 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1420 IXGBE_FDIRCMD_CLEARHT));
1421 IXGBE_WRITE_FLUSH(hw);
1422 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1423 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &

--- 309 unchanged lines hidden (view full) ---

1733 break;
1734 default:
1735 DEBUGOUT(" Error on flow type mask\n");
1736 return IXGBE_ERR_CONFIG;
1737 }
1738
1739 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1740 case 0x0000:
1422 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1423
1424 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1425 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1426 IXGBE_FDIRCMD_CLEARHT));
1427 IXGBE_WRITE_FLUSH(hw);
1428 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1429 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &

--- 309 unchanged lines hidden (view full) ---

1739 break;
1740 default:
1741 DEBUGOUT(" Error on flow type mask\n");
1742 return IXGBE_ERR_CONFIG;
1743 }
1744
1745 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1746 case 0x0000:
1741 /* mask VLAN ID, fall through to mask VLAN priority */
1747 /* mask VLAN ID */
1742 fdirm |= IXGBE_FDIRM_VLANID;
1748 fdirm |= IXGBE_FDIRM_VLANID;
1749 /* fall through */
1743 case 0x0FFF:
1744 /* mask VLAN priority */
1745 fdirm |= IXGBE_FDIRM_VLANP;
1746 break;
1747 case 0xE000:
1750 case 0x0FFF:
1751 /* mask VLAN priority */
1752 fdirm |= IXGBE_FDIRM_VLANP;
1753 break;
1754 case 0xE000:
1748 /* mask VLAN ID only, fall through */
1755 /* mask VLAN ID only */
1749 fdirm |= IXGBE_FDIRM_VLANID;
1756 fdirm |= IXGBE_FDIRM_VLANID;
1757 /* fall through */
1750 case 0xEFFF:
1751 /* no VLAN fields masked */
1752 break;
1753 default:
1754 DEBUGOUT(" Error on VLAN mask\n");
1755 return IXGBE_ERR_CONFIG;
1756 }
1757
1758 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1759 case 0x0000:
1758 case 0xEFFF:
1759 /* no VLAN fields masked */
1760 break;
1761 default:
1762 DEBUGOUT(" Error on VLAN mask\n");
1763 return IXGBE_ERR_CONFIG;
1764 }
1765
1766 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1767 case 0x0000:
1760 /* Mask Flex Bytes, fall through */
1768 /* Mask Flex Bytes */
1761 fdirm |= IXGBE_FDIRM_FLEX;
1769 fdirm |= IXGBE_FDIRM_FLEX;
1770 /* fall through */
1762 case 0xFFFF:
1763 break;
1764 default:
1765 DEBUGOUT(" Error on flexible byte mask\n");
1766 return IXGBE_ERR_CONFIG;
1767 }
1768
1769 if (cloud_mode) {

--- 34 unchanged lines hidden (view full) ---

1804 case 0xFFFF:
1805 break;
1806 default:
1807 DEBUGOUT(" Error on tunnel type byte mask\n");
1808 return IXGBE_ERR_CONFIG;
1809 }
1810 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1811
1771 case 0xFFFF:
1772 break;
1773 default:
1774 DEBUGOUT(" Error on flexible byte mask\n");
1775 return IXGBE_ERR_CONFIG;
1776 }
1777
1778 if (cloud_mode) {

--- 34 unchanged lines hidden (view full) ---

1813 case 0xFFFF:
1814 break;
1815 default:
1816 DEBUGOUT(" Error on tunnel type byte mask\n");
1817 return IXGBE_ERR_CONFIG;
1818 }
1819 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1820
1812 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
1813 * FDIRDIP4M in cloud mode to allow L3/L3 packets to
1814 * tunnel.
1821 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
1822 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
1823 * L3/L3 packets to tunnel.
1815 */
1816 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1817 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1818 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1819 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1824 */
1825 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1826 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1827 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1828 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1829 switch (hw->mac.type) {
1830 case ixgbe_mac_X550:
1831 case ixgbe_mac_X550EM_x:
1832 case ixgbe_mac_X550EM_a:
1833 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
1834 break;
1835 default:
1836 break;
1837 }
1820 }
1821
1822 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1823 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1824
1825 if (!cloud_mode) {
1826 /* store the TCP/UDP port masks, bit reversed from port
1827 * layout */
1828 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1829
1830 /* write both the same so that UDP and TCP use the same mask */
1831 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1832 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1833 /* also use it for SCTP */
1834 switch (hw->mac.type) {
1835 case ixgbe_mac_X550:
1836 case ixgbe_mac_X550EM_x:
1838 }
1839
1840 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1841 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1842
1843 if (!cloud_mode) {
1844 /* store the TCP/UDP port masks, bit reversed from port
1845 * layout */
1846 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1847
1848 /* write both the same so that UDP and TCP use the same mask */
1849 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1850 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1851 /* also use it for SCTP */
1852 switch (hw->mac.type) {
1853 case ixgbe_mac_X550:
1854 case ixgbe_mac_X550EM_x:
1855 case ixgbe_mac_X550EM_a:
1837 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1838 break;
1839 default:
1840 break;
1841 }
1842
1843 /* store source and destination IP masks (big-enian) */
1844 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,

--- 163 unchanged lines hidden (view full) ---

2008 }
2009 break;
2010 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2011 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2012 if (input->formatted.dst_port || input->formatted.src_port) {
2013 DEBUGOUT(" Error on src/dst port\n");
2014 return IXGBE_ERR_CONFIG;
2015 }
1856 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1857 break;
1858 default:
1859 break;
1860 }
1861
1862 /* store source and destination IP masks (big-enian) */
1863 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,

--- 163 unchanged lines hidden (view full) ---

2027 }
2028 break;
2029 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2030 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2031 if (input->formatted.dst_port || input->formatted.src_port) {
2032 DEBUGOUT(" Error on src/dst port\n");
2033 return IXGBE_ERR_CONFIG;
2034 }
2035 /* fall through */
2016 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2017 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2018 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2019 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2020 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2021 IXGBE_ATR_L4TYPE_MASK;
2022 break;
2023 default:

--- 129 unchanged lines hidden (view full) ---

2153}
2154
2155/**
2156 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2157 * @hw: pointer to hardware structure
2158 *
2159 * Determines physical layer capabilities of the current configuration.
2160 **/
2036 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2037 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2038 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2039 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2040 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2041 IXGBE_ATR_L4TYPE_MASK;
2042 break;
2043 default:

--- 129 unchanged lines hidden (view full) ---

2173}
2174
2175/**
2176 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2177 * @hw: pointer to hardware structure
2178 *
2179 * Determines physical layer capabilities of the current configuration.
2180 **/
2161u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2181u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2162{
2182{
2163 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2183 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2164 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2165 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2166 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2167 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2168 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2169 u16 ext_ability = 0;
2170
2171 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");

--- 439 unchanged lines hidden --- 		2184 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2185 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2186 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2187 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2188 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2189 u16 ext_ability = 0;
2190
2191 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");

--- 439 unchanged lines hidden ---