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ixgbe_82598.c (238149) ixgbe_82598.c (247822)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 238149 2012-07-05 20:51:44Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 247822 2013-03-04 23:07:40Z jfv $*/
34
35#include "ixgbe_type.h"
36#include "ixgbe_82598.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
45static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
48 ixgbe_link_speed *speed, bool *link_up,
49 bool link_up_wait_to_complete);
50static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
34
35#include "ixgbe_type.h"
36#include "ixgbe_82598.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
45static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
48 ixgbe_link_speed *speed, bool *link_up,
49 bool link_up_wait_to_complete);
50static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
54static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
52 bool autoneg_wait_to_complete);
53static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
58static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
59static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
60static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
61static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
62 u32 headroom, int strategy);
55 bool autoneg_wait_to_complete);
56static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
57static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
58static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
59static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
60 u32 headroom, int strategy);
63
61static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
62 u8 *sff8472_data);
64/**
65 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
66 * @hw: pointer to the HW structure
67 *
68 * The defaults for 82598 should be in the range of 50us to 50ms,
69 * however the hardware default for these parts is 500us to 1ms which is less
70 * than the 10ms recommended by the pci-e spec. To address this we need to
71 * increase the value to either 10ms to 250ms for capability version 1 config,

--- 78 unchanged lines hidden (view full) ---

150 mac->num_rar_entries = 16;
151 mac->rx_pb_size = 512;
152 mac->max_tx_queues = 32;
153 mac->max_rx_queues = 64;
154 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
155
156 /* SFP+ Module */
157 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
63/**
64 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
65 * @hw: pointer to the HW structure
66 *
67 * The defaults for 82598 should be in the range of 50us to 50ms,
68 * however the hardware default for these parts is 500us to 1ms which is less
69 * than the 10ms recommended by the pci-e spec. To address this we need to
70 * increase the value to either 10ms to 250ms for capability version 1 config,

--- 78 unchanged lines hidden (view full) ---

149 mac->num_rar_entries = 16;
150 mac->rx_pb_size = 512;
151 mac->max_tx_queues = 32;
152 mac->max_rx_queues = 64;
153 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
154
155 /* SFP+ Module */
156 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
157 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598;
158
159 /* Link */
160 mac->ops.check_link = &ixgbe_check_mac_link_82598;
161 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
162 mac->ops.flap_tx_laser = NULL;
163 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
164 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
165

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707out:
708 return IXGBE_SUCCESS;
709}
710
711/**
712 * ixgbe_setup_mac_link_82598 - Set MAC link speed
713 * @hw: pointer to hardware structure
714 * @speed: new link speed
158
159 /* Link */
160 mac->ops.check_link = &ixgbe_check_mac_link_82598;
161 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
162 mac->ops.flap_tx_laser = NULL;
163 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
164 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
165

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707out:
708 return IXGBE_SUCCESS;
709}
710
711/**
712 * ixgbe_setup_mac_link_82598 - Set MAC link speed
713 * @hw: pointer to hardware structure
714 * @speed: new link speed
715 * @autoneg: TRUE if autonegotiation enabled
716 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
717 *
718 * Set the link speed in the AUTOC register and restarts link.
719 **/
720static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
715 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
716 *
717 * Set the link speed in the AUTOC register and restarts link.
718 **/
719static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
721 ixgbe_link_speed speed, bool autoneg,
720 ixgbe_link_speed speed,
722 bool autoneg_wait_to_complete)
723{
721 bool autoneg_wait_to_complete)
722{
723 bool autoneg = FALSE;
724 s32 status = IXGBE_SUCCESS;
725 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
726 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
727 u32 autoc = curr_autoc;
728 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
729
730 DEBUGFUNC("ixgbe_setup_mac_link_82598");
731

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761 return status;
762}
763
764
765/**
766 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
767 * @hw: pointer to hardware structure
768 * @speed: new link speed
724 s32 status = IXGBE_SUCCESS;
725 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
726 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
727 u32 autoc = curr_autoc;
728 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
729
730 DEBUGFUNC("ixgbe_setup_mac_link_82598");
731

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761 return status;
762}
763
764
765/**
766 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
767 * @hw: pointer to hardware structure
768 * @speed: new link speed
769 * @autoneg: TRUE if autonegotiation enabled
770 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
771 *
772 * Sets the link speed in the AUTOC register in the MAC and restarts link.
773 **/
774static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
775 ixgbe_link_speed speed,
769 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
770 *
771 * Sets the link speed in the AUTOC register in the MAC and restarts link.
772 **/
773static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
774 ixgbe_link_speed speed,
776 bool autoneg,
777 bool autoneg_wait_to_complete)
778{
779 s32 status;
780
781 DEBUGFUNC("ixgbe_setup_copper_link_82598");
782
783 /* Setup the PHY according to input speed */
775 bool autoneg_wait_to_complete)
776{
777 s32 status;
778
779 DEBUGFUNC("ixgbe_setup_copper_link_82598");
780
781 /* Setup the PHY according to input speed */
784 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
782 status = hw->phy.ops.setup_link_speed(hw, speed,
785 autoneg_wait_to_complete);
786 /* Set up MAC */
787 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
788
789 return status;
790}
791
792/**

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1097 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1098 IXGBE_WRITE_FLUSH(hw);
1099 usec_delay(10);
1100
1101 return IXGBE_SUCCESS;
1102}
1103
1104/**
783 autoneg_wait_to_complete);
784 /* Set up MAC */
785 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
786
787 return status;
788}
789
790/**

--- 304 unchanged lines hidden (view full) ---

1095 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1096 IXGBE_WRITE_FLUSH(hw);
1097 usec_delay(10);
1098
1099 return IXGBE_SUCCESS;
1100}
1101
1102/**
1105 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1103 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1106 * @hw: pointer to hardware structure
1104 * @hw: pointer to hardware structure
1107 * @byte_offset: EEPROM byte offset to read
1105 * @dev_addr: address to read from
1106 * @byte_offset: byte offset to read from dev_addr
1108 * @eeprom_data: value read
1109 *
1110 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1111 **/
1107 * @eeprom_data: value read
1108 *
1109 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1110 **/
1112s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1113 u8 *eeprom_data)
1111static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
1112 u8 byte_offset, u8 *eeprom_data)
1114{
1115 s32 status = IXGBE_SUCCESS;
1116 u16 sfp_addr = 0;
1117 u16 sfp_data = 0;
1118 u16 sfp_stat = 0;
1119 u32 i;
1120
1113{
1114 s32 status = IXGBE_SUCCESS;
1115 u16 sfp_addr = 0;
1116 u16 sfp_data = 0;
1117 u16 sfp_stat = 0;
1118 u32 i;
1119
1121 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1120 DEBUGFUNC("ixgbe_read_i2c_phy_82598");
1122
1123 if (hw->phy.type == ixgbe_phy_nl) {
1124 /*
1125 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1126 * 0xC30D. These registers are used to talk to the SFP+
1127 * module's EEPROM through the SDA/SCL (I2C) interface.
1128 */
1121
1122 if (hw->phy.type == ixgbe_phy_nl) {
1123 /*
1124 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1125 * 0xC30D. These registers are used to talk to the SFP+
1126 * module's EEPROM through the SDA/SCL (I2C) interface.
1127 */
1129 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1128 sfp_addr = (dev_addr << 8) + byte_offset;
1130 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1131 hw->phy.ops.write_reg(hw,
1132 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1133 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1134 sfp_addr);
1135
1136 /* Poll status */
1137 for (i = 0; i < 100; i++) {

--- 15 unchanged lines hidden (view full) ---

1153
1154 /* Read data */
1155 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1156 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1157
1158 *eeprom_data = (u8)(sfp_data >> 8);
1159 } else {
1160 status = IXGBE_ERR_PHY;
1129 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1130 hw->phy.ops.write_reg(hw,
1131 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1132 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1133 sfp_addr);
1134
1135 /* Poll status */
1136 for (i = 0; i < 100; i++) {

--- 15 unchanged lines hidden (view full) ---

1152
1153 /* Read data */
1154 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1155 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1156
1157 *eeprom_data = (u8)(sfp_data >> 8);
1158 } else {
1159 status = IXGBE_ERR_PHY;
1161 goto out;
1162 }
1163
1164out:
1165 return status;
1166}
1167
1168/**
1160 }
1161
1162out:
1163 return status;
1164}
1165
1166/**
1167 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1168 * @hw: pointer to hardware structure
1169 * @byte_offset: EEPROM byte offset to read
1170 * @eeprom_data: value read
1171 *
1172 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1173 **/
1174s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1175 u8 *eeprom_data)
1176{
1177 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1178 byte_offset, eeprom_data);
1179}
1180
1181/**
1182 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1183 * @hw: pointer to hardware structure
1184 * @byte_offset: byte offset at address 0xA2
1185 * @eeprom_data: value read
1186 *
1187 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1188 **/
1189static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1190 u8 *sff8472_data)
1191{
1192 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1193 byte_offset, sff8472_data);
1194}
1195
1196/**
1169 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1170 * @hw: pointer to hardware structure
1171 *
1172 * Determines physical layer capabilities of the current configuration.
1173 **/
1174u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1175{
1176 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;

--- 198 unchanged lines hidden --- 		1197 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1198 * @hw: pointer to hardware structure
1199 *
1200 * Determines physical layer capabilities of the current configuration.
1201 **/
1202u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1203{
1204 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;

--- 198 unchanged lines hidden ---