1/******************************************************************************
2
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe.h 320897 2017-07-11 21:25:07Z erj $*/
34
35
36#ifndef _IXGBE_H_
37#define _IXGBE_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/buf_ring.h>
43#include <sys/mbuf.h>
44#include <sys/protosw.h>
45#include <sys/socket.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>
48#include <sys/module.h>
49#include <sys/sockio.h>
50#include <sys/eventhandler.h>
--- 34 unchanged lines hidden (view full) ---
85#include <sys/sysctl.h>
86#include <sys/endian.h>
87#include <sys/taskqueue.h>
88#include <sys/pcpu.h>
89#include <sys/smp.h>
90#include <machine/smp.h>
91#include <sys/sbuf.h>
92
93#include "ixgbe_api.h"
94#include "ixgbe_common.h"
95#include "ixgbe_phy.h"
96#include "ixgbe_vf.h"
97#include "ixgbe_features.h"
98
99/* Tunables */
100
101/*
102 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
103 * number of transmit descriptors allocated by the driver. Increasing this
104 * value allows the driver to queue more transmits. Each descriptor is 16
105 * bytes. Performance tests have show the 2K value to be optimal for top
106 * performance.
107 */
108#define DEFAULT_TXD 1024
109#define PERFORM_TXD 2048
110#define MAX_TXD 4096
111#define MIN_TXD 64
112
113/*
114 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
115 * number of receive descriptors allocated for each RX queue. Increasing this
116 * value allows the driver to buffer more incoming packets. Each descriptor
117 * is 16 bytes. A receive buffer is also allocated for each descriptor.
118 *
119 * Note: with 8 rings and a dual port card, it is possible to bump up
120 * against the system mbuf pool limit, you can tune nmbclusters
121 * to adjust for this.
122 */
123#define DEFAULT_RXD 1024
124#define PERFORM_RXD 2048
125#define MAX_RXD 4096
126#define MIN_RXD 64
127
128/* Alignment for rings */
129#define DBA_ALIGN 128
130
131/*
132 * This is the max watchdog interval, ie. the time that can
133 * pass between any two TX clean operations, such only happening
134 * when the TX hardware is functioning.
135 */
136#define IXGBE_WATCHDOG (10 * hz)
137
138/*
139 * This parameters control when the driver calls the routine to reclaim
140 * transmit descriptors.
141 */
142#define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8)
143#define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32)
144
145/* These defines are used in MTU calculations */
146#define IXGBE_MAX_FRAME_SIZE 9728
147#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN)
148#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \
149 ETHER_VLAN_ENCAP_LEN)
150#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR)
151#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN)
152
153/* Flow control constants */
154#define IXGBE_FC_PAUSE 0xFFFF
155#define IXGBE_FC_HI 0x20000
156#define IXGBE_FC_LO 0x10000
157
158/*
159 * Used for optimizing small rx mbufs. Effort is made to keep the copy
160 * small and aligned for the CPU L1 cache.
161 *
162 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting
163 * 32 byte alignment needed for the fast bcopy results in 8 bytes being
164 * wasted. Getting 64 byte alignment, which _should_ be ideal for
165 * modern Intel CPUs, results in 40 bytes wasted and a significant drop
166 * in observed efficiency of the optimization, 97.9% -> 81.8%.
167 */
168#if __FreeBSD_version < 1002000
169#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr))
170#endif
171#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32)
172#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED)
173#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE)
174
175/* Keep older OS drivers building... */
176#if !defined(SYSCTL_ADD_UQUAD)
177#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
178#endif
179
180/* Defines for printing debug information */
181#define DEBUG_INIT 0
--- 6 unchanged lines hidden (view full) ---
188#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
189#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
190#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
191#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
192#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
193#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
194
195#define MAX_NUM_MULTICAST_ADDRESSES 128
196#define IXGBE_82598_SCATTER 100
197#define IXGBE_82599_SCATTER 32
198#define MSIX_82598_BAR 3
199#define MSIX_82599_BAR 4
200#define IXGBE_TSO_SIZE 262140
201#define IXGBE_RX_HDR 128
202#define IXGBE_VFTA_SIZE 128
203#define IXGBE_BR_SIZE 4096
204#define IXGBE_QUEUE_MIN_FREE 32
205#define IXGBE_MAX_TX_BUSY 10
206#define IXGBE_QUEUE_HUNG 0x80000000
207
208#define IXGBE_EITR_DEFAULT 128
209
210/* Supported offload bits in mbuf flag */
211#if __FreeBSD_version >= 1000000
212#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
213 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
214 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
215#elif __FreeBSD_version >= 800000
216#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
217#else
218#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
219#endif
220
221/* Backward compatibility items for very old versions */
222#ifndef pci_find_cap
223#define pci_find_cap pci_find_extcap
224#endif
225
226#ifndef DEVMETHOD_END
227#define DEVMETHOD_END { NULL, NULL }
228#endif
229
230/*
231 * Interrupt Moderation parameters
232 */
233#define IXGBE_LOW_LATENCY 128
234#define IXGBE_AVE_LATENCY 400
235#define IXGBE_BULK_LATENCY 1200
236
237/* Using 1FF (the max value), the interval is ~1.05ms */
238#define IXGBE_LINK_ITR_QUANTA 0x1FF
239#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \
240 IXGBE_EITR_ITR_INT_MASK)
241
242
243
244/************************************************************************
245 * vendor_info_array
246 *
247 * Contains the list of Subvendor/Subdevice IDs on
248 * which the driver should load.
249 ************************************************************************/
250typedef struct _ixgbe_vendor_info_t {
251 unsigned int vendor_id;
252 unsigned int device_id;
253 unsigned int subvendor_id;
254 unsigned int subdevice_id;
255 unsigned int index;
256} ixgbe_vendor_info_t;
257
258struct ixgbe_bp_data {
259 u32 low;
260 u32 high;
261 u32 log;
262};
263
264struct ixgbe_tx_buf {
265 union ixgbe_adv_tx_desc *eop;
266 struct mbuf *m_head;
267 bus_dmamap_t map;
268};
269
270struct ixgbe_rx_buf {
271 struct mbuf *buf;
272 struct mbuf *fmp;
273 bus_dmamap_t pmap;
274 u_int flags;
275#define IXGBE_RX_COPY 0x01
276 uint64_t addr;
277};
278
279/*
280 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free
281 */
282struct ixgbe_dma_alloc {
283 bus_addr_t dma_paddr;
284 caddr_t dma_vaddr;
285 bus_dma_tag_t dma_tag;
286 bus_dmamap_t dma_map;
287 bus_dma_segment_t dma_seg;
288 bus_size_t dma_size;
289 int dma_nseg;
290};
291
292struct ixgbe_mc_addr {
293 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
294 u32 vmdq;
295};
296
297/*
298 * Driver queue struct: this is the interrupt container
299 * for the associated tx and rx ring.
300 */
301struct ix_queue {
302 struct adapter *adapter;
303 u32 msix; /* This queue's MSI-X vector */
304 u32 eims; /* This queue's EIMS bit */
305 u32 eitr_setting;
306 u32 me;
307 struct resource *res;
308 void *tag;
309 int busy;
310 struct tx_ring *txr;
311 struct rx_ring *rxr;
312 struct task que_task;
313 struct taskqueue *tq;
314 u64 irqs;
315};
316
317/*
318 * The transmit ring, one per queue
319 */
320struct tx_ring {
321 struct adapter *adapter;
322 struct mtx tx_mtx;
323 u32 me;
324 u32 tail;
325 int busy;
326 union ixgbe_adv_tx_desc *tx_base;
327 struct ixgbe_tx_buf *tx_buffers;
328 struct ixgbe_dma_alloc txdma;
329 volatile u16 tx_avail;
330 u16 next_avail_desc;
331 u16 next_to_clean;
332 u16 num_desc;
333 u32 txd_cmd;
334 bus_dma_tag_t txtag;
335 char mtx_name[16];
336 struct buf_ring *br;
337 struct task txq_task;
338
339 /* Flow Director */
340 u16 atr_sample;
341 u16 atr_count;
342
343 u32 bytes; /* used for AIM */
344 u32 packets;
345 /* Soft Stats */
346 u64 tso_tx;
347 u64 no_tx_map_avail;
348 u64 no_tx_dma_setup;
349 u64 no_desc_avail;
350 u64 total_packets;
351};
352
353
354/*
355 * The Receive ring, one per rx queue
356 */
357struct rx_ring {
358 struct adapter *adapter;
359 struct mtx rx_mtx;
360 u32 me;
361 u32 tail;
362 union ixgbe_adv_rx_desc *rx_base;
363 struct ixgbe_dma_alloc rxdma;
364 struct lro_ctrl lro;
365 bool lro_enabled;
366 bool hw_rsc;
367 bool vtag_strip;
368 u16 next_to_refresh;
369 u16 next_to_check;
370 u16 num_desc;
371 u16 mbuf_sz;
372 char mtx_name[16];
373 struct ixgbe_rx_buf *rx_buffers;
374 bus_dma_tag_t ptag;
375
376 u32 bytes; /* Used for AIM calc */
377 u32 packets;
378
379 /* Soft stats */
380 u64 rx_irq;
381 u64 rx_copies;
382 u64 rx_packets;
383 u64 rx_bytes;
384 u64 rx_discarded;
385 u64 rsc_num;
386
387 /* Flow Director */
388 u64 flm;
389};
390
391#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */
392
393struct ixgbe_vf {
394 u_int pool;
395 u_int rar_index;
396 u_int max_frame_size;
397 uint32_t flags;
398 uint8_t ether_addr[ETHER_ADDR_LEN];
399 uint16_t mc_hash[IXGBE_MAX_VF_MC];
400 uint16_t num_mc_hashes;
401 uint16_t default_vlan;
402 uint16_t vlan_tag;
403 uint16_t api_ver;
404};
405
406/* Our adapter structure */
407struct adapter {
408 struct ixgbe_hw hw;
409 struct ixgbe_osdep osdep;
410
411 device_t dev;
412 struct ifnet *ifp;
413
414 struct resource *pci_mem;
415 struct resource *msix_mem;
416
417 /*
418 * Interrupt resources: this set is
419 * either used for legacy, or for Link
420 * when doing MSI-X
421 */
422 void *tag;
423 struct resource *res;
424
425 struct ifmedia media;
426 struct callout timer;
427 int link_rid;
428 int if_flags;
429
430 struct mtx core_mtx;
431
432 eventhandler_tag vlan_attach;
433 eventhandler_tag vlan_detach;
434
435 u16 num_vlans;
436 u16 num_queues;
437
438 /*
439 * Shadow VFTA table, this is needed because
440 * the real vlan filter table gets cleared during
441 * a soft reset and the driver needs to be able
442 * to repopulate it.
443 */
444 u32 shadow_vfta[IXGBE_VFTA_SIZE];
445
446 /* Info about the interface */
447 int advertise; /* link speeds */
448 int enable_aim; /* adaptive interrupt moderation */
449 bool link_active;
450 u16 max_frame_size;
451 u16 num_segs;
452 u32 link_speed;
453 bool link_up;
454 u32 vector;
455 u16 dmac;
456 u32 phy_layer;
457
458 /* Power management-related */
459 bool wol_support;
460 u32 wufc;
461
462 /* Mbuf cluster size */
463 u32 rx_mbuf_sz;
464
465 /* Support for pluggable optics */
466 bool sfp_probe;
467 struct task link_task; /* Link tasklet */
468 struct task mod_task; /* SFP tasklet */
469 struct task msf_task; /* Multispeed Fiber */
470 struct task mbx_task; /* VF -> PF mailbox interrupt */
471
472 /* Flow Director */
473 int fdir_reinit;
474 struct task fdir_task;
475
476 struct task phy_task; /* PHY intr tasklet */
477 struct taskqueue *tq;
478
479 /*
480 * Queues:
481 * This is the irq holder, it has
482 * and RX/TX pair or rings associated
483 * with it.
484 */
485 struct ix_queue *queues;
486
487 /*
488 * Transmit rings
489 * Allocated at run time, an array of rings
490 */
491 struct tx_ring *tx_rings;
492 u32 num_tx_desc;
493 u32 tx_process_limit;
494
495 /*
496 * Receive rings
497 * Allocated at run time, an array of rings
498 */
499 struct rx_ring *rx_rings;
500 u64 active_queues;
501 u32 num_rx_desc;
502 u32 rx_process_limit;
503
504 /* Multicast array memory */
505 struct ixgbe_mc_addr *mta;
506
507 /* SR-IOV */
508 int iov_mode;
509 int num_vfs;
510 int pool;
511 struct ixgbe_vf *vfs;
512
513 /* Bypass */
514 struct ixgbe_bp_data bypass;
515
516 /* Netmap */
517 void (*init_locked)(struct adapter *);
518 void (*stop_locked)(void *);
519
520 /* Misc stats maintained by the driver */
521 unsigned long dropped_pkts;
522 unsigned long mbuf_defrag_failed;
523 unsigned long mbuf_header_failed;
524 unsigned long mbuf_packet_failed;
525 unsigned long watchdog_events;
526 unsigned long link_irq;
527 union {
528 struct ixgbe_hw_stats pf;
529 struct ixgbevf_hw_stats vf;
530 } stats;
531#if __FreeBSD_version >= 1100036
532 /* counter(9) stats */
533 u64 ipackets;
534 u64 ierrors;
535 u64 opackets;
536 u64 oerrors;
537 u64 ibytes;
538 u64 obytes;
539 u64 imcasts;
540 u64 omcasts;
541 u64 iqdrops;
542 u64 noproto;
543#endif
544 /* Feature capable/enabled flags. See ixgbe_features.h */
545 u32 feat_cap;
546 u32 feat_en;
547};
548
549
550/* Precision Time Sync (IEEE 1588) defines */
551#define ETHERTYPE_IEEE1588 0x88F7
552#define PICOSECS_PER_TICK 20833
553#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */
554#define IXGBE_ADVTXD_TSTAMP 0x00080000
555
556
557#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
558 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
559#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
560#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
561#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
562#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
--- 32 unchanged lines hidden (view full) ---
595#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count)
596#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count)
597#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count)
598#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count)
599#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count)
600#endif
601
602/* External PHY register addresses */
603#define IXGBE_PHY_CURRENT_TEMP 0xC820
604#define IXGBE_PHY_OVERTEMP_STATUS 0xC830
605
606/* Sysctl help messages; displayed with sysctl -d */
607#define IXGBE_SYSCTL_DESC_ADV_SPEED \
608 "\nControl advertised link speed using these flags:\n" \
609 "\t0x1 - advertise 100M\n" \
610 "\t0x2 - advertise 1G\n" \
611 "\t0x4 - advertise 10G\n" \
612 "\t0x8 - advertise 10M\n\n" \
613 "\t100M and 10M are only supported on certain adapters.\n"
614
615#define IXGBE_SYSCTL_DESC_SET_FC \
616 "\nSet flow control mode using these values:\n" \
617 "\t0 - off\n" \
618 "\t1 - rx pause\n" \
619 "\t2 - tx pause\n" \
620 "\t3 - tx and rx pause"
621
622/* Workaround to make 8.0 buildable */
623#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
624static __inline int
625drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
626{
627#ifdef ALTQ
628 if (ALTQ_IS_ENABLED(&ifp->if_snd))
629 return (1);
630#endif
631 return (!buf_ring_empty(br));
632}
633#endif
634
635/*
636 * Find the number of unrefreshed RX descriptors
637 */
638static inline u16
639ixgbe_rx_unrefreshed(struct rx_ring *rxr)
640{
641 if (rxr->next_to_check > rxr->next_to_refresh)
642 return (rxr->next_to_check - rxr->next_to_refresh - 1);
643 else
644 return ((rxr->num_desc + rxr->next_to_check) -
645 rxr->next_to_refresh - 1);
646}
647
648static inline int
649ixgbe_legacy_ring_empty(struct ifnet *ifp, struct buf_ring *dummy)
650{
651 UNREFERENCED_1PARAMETER(dummy);
652
653 return IFQ_DRV_IS_EMPTY(&ifp->if_snd);
654}
655
656/*
657 * This checks for a zero mac addr, something that will be likely
658 * unless the Admin on the Host has created one.
659 */
660static inline bool
661ixv_check_ether_addr(u8 *addr)
662{
663 bool status = TRUE;
664
665 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 &&
666 addr[3] == 0 && addr[4]== 0 && addr[5] == 0))
667 status = FALSE;
668
669 return (status);
670}
671
672/* Shared Prototypes */
673void ixgbe_legacy_start(struct ifnet *);
674int ixgbe_legacy_start_locked(struct ifnet *, struct tx_ring *);
675int ixgbe_mq_start(struct ifnet *, struct mbuf *);
676int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *);
677void ixgbe_qflush(struct ifnet *);
678void ixgbe_deferred_mq_start(void *, int);
679
680int ixgbe_allocate_queues(struct adapter *);
681int ixgbe_setup_transmit_structures(struct adapter *);
682void ixgbe_free_transmit_structures(struct adapter *);
683int ixgbe_setup_receive_structures(struct adapter *);
684void ixgbe_free_receive_structures(struct adapter *);
685void ixgbe_txeof(struct tx_ring *);
686bool ixgbe_rxeof(struct ix_queue *);
687
688#include "ixgbe_bypass.h"
689#include "ixgbe_sriov.h"
690#include "ixgbe_fdir.h"
691#include "ixgbe_rss.h"
692#include "ixgbe_netmap.h"
693
694#endif /* _IXGBE_H_ */
2
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe.h 320897 2017-07-11 21:25:07Z erj $*/
34
35
36#ifndef _IXGBE_H_
37#define _IXGBE_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/buf_ring.h>
43#include <sys/mbuf.h>
44#include <sys/protosw.h>
45#include <sys/socket.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>
48#include <sys/module.h>
49#include <sys/sockio.h>
50#include <sys/eventhandler.h>
--- 34 unchanged lines hidden (view full) ---
85#include <sys/sysctl.h>
86#include <sys/endian.h>
87#include <sys/taskqueue.h>
88#include <sys/pcpu.h>
89#include <sys/smp.h>
90#include <machine/smp.h>
91#include <sys/sbuf.h>
92
93#include "ixgbe_api.h"
94#include "ixgbe_common.h"
95#include "ixgbe_phy.h"
96#include "ixgbe_vf.h"
97#include "ixgbe_features.h"
98
99/* Tunables */
100
101/*
102 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
103 * number of transmit descriptors allocated by the driver. Increasing this
104 * value allows the driver to queue more transmits. Each descriptor is 16
105 * bytes. Performance tests have show the 2K value to be optimal for top
106 * performance.
107 */
108#define DEFAULT_TXD 1024
109#define PERFORM_TXD 2048
110#define MAX_TXD 4096
111#define MIN_TXD 64
112
113/*
114 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
115 * number of receive descriptors allocated for each RX queue. Increasing this
116 * value allows the driver to buffer more incoming packets. Each descriptor
117 * is 16 bytes. A receive buffer is also allocated for each descriptor.
118 *
119 * Note: with 8 rings and a dual port card, it is possible to bump up
120 * against the system mbuf pool limit, you can tune nmbclusters
121 * to adjust for this.
122 */
123#define DEFAULT_RXD 1024
124#define PERFORM_RXD 2048
125#define MAX_RXD 4096
126#define MIN_RXD 64
127
128/* Alignment for rings */
129#define DBA_ALIGN 128
130
131/*
132 * This is the max watchdog interval, ie. the time that can
133 * pass between any two TX clean operations, such only happening
134 * when the TX hardware is functioning.
135 */
136#define IXGBE_WATCHDOG (10 * hz)
137
138/*
139 * This parameters control when the driver calls the routine to reclaim
140 * transmit descriptors.
141 */
142#define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8)
143#define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32)
144
145/* These defines are used in MTU calculations */
146#define IXGBE_MAX_FRAME_SIZE 9728
147#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN)
148#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \
149 ETHER_VLAN_ENCAP_LEN)
150#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR)
151#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN)
152
153/* Flow control constants */
154#define IXGBE_FC_PAUSE 0xFFFF
155#define IXGBE_FC_HI 0x20000
156#define IXGBE_FC_LO 0x10000
157
158/*
159 * Used for optimizing small rx mbufs. Effort is made to keep the copy
160 * small and aligned for the CPU L1 cache.
161 *
162 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting
163 * 32 byte alignment needed for the fast bcopy results in 8 bytes being
164 * wasted. Getting 64 byte alignment, which _should_ be ideal for
165 * modern Intel CPUs, results in 40 bytes wasted and a significant drop
166 * in observed efficiency of the optimization, 97.9% -> 81.8%.
167 */
168#if __FreeBSD_version < 1002000
169#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr))
170#endif
171#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32)
172#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED)
173#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE)
174
175/* Keep older OS drivers building... */
176#if !defined(SYSCTL_ADD_UQUAD)
177#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
178#endif
179
180/* Defines for printing debug information */
181#define DEBUG_INIT 0
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188#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
189#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
190#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
191#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
192#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
193#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
194
195#define MAX_NUM_MULTICAST_ADDRESSES 128
196#define IXGBE_82598_SCATTER 100
197#define IXGBE_82599_SCATTER 32
198#define MSIX_82598_BAR 3
199#define MSIX_82599_BAR 4
200#define IXGBE_TSO_SIZE 262140
201#define IXGBE_RX_HDR 128
202#define IXGBE_VFTA_SIZE 128
203#define IXGBE_BR_SIZE 4096
204#define IXGBE_QUEUE_MIN_FREE 32
205#define IXGBE_MAX_TX_BUSY 10
206#define IXGBE_QUEUE_HUNG 0x80000000
207
208#define IXGBE_EITR_DEFAULT 128
209
210/* Supported offload bits in mbuf flag */
211#if __FreeBSD_version >= 1000000
212#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
213 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
214 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
215#elif __FreeBSD_version >= 800000
216#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
217#else
218#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
219#endif
220
221/* Backward compatibility items for very old versions */
222#ifndef pci_find_cap
223#define pci_find_cap pci_find_extcap
224#endif
225
226#ifndef DEVMETHOD_END
227#define DEVMETHOD_END { NULL, NULL }
228#endif
229
230/*
231 * Interrupt Moderation parameters
232 */
233#define IXGBE_LOW_LATENCY 128
234#define IXGBE_AVE_LATENCY 400
235#define IXGBE_BULK_LATENCY 1200
236
237/* Using 1FF (the max value), the interval is ~1.05ms */
238#define IXGBE_LINK_ITR_QUANTA 0x1FF
239#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \
240 IXGBE_EITR_ITR_INT_MASK)
241
242
243
244/************************************************************************
245 * vendor_info_array
246 *
247 * Contains the list of Subvendor/Subdevice IDs on
248 * which the driver should load.
249 ************************************************************************/
250typedef struct _ixgbe_vendor_info_t {
251 unsigned int vendor_id;
252 unsigned int device_id;
253 unsigned int subvendor_id;
254 unsigned int subdevice_id;
255 unsigned int index;
256} ixgbe_vendor_info_t;
257
258struct ixgbe_bp_data {
259 u32 low;
260 u32 high;
261 u32 log;
262};
263
264struct ixgbe_tx_buf {
265 union ixgbe_adv_tx_desc *eop;
266 struct mbuf *m_head;
267 bus_dmamap_t map;
268};
269
270struct ixgbe_rx_buf {
271 struct mbuf *buf;
272 struct mbuf *fmp;
273 bus_dmamap_t pmap;
274 u_int flags;
275#define IXGBE_RX_COPY 0x01
276 uint64_t addr;
277};
278
279/*
280 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free
281 */
282struct ixgbe_dma_alloc {
283 bus_addr_t dma_paddr;
284 caddr_t dma_vaddr;
285 bus_dma_tag_t dma_tag;
286 bus_dmamap_t dma_map;
287 bus_dma_segment_t dma_seg;
288 bus_size_t dma_size;
289 int dma_nseg;
290};
291
292struct ixgbe_mc_addr {
293 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
294 u32 vmdq;
295};
296
297/*
298 * Driver queue struct: this is the interrupt container
299 * for the associated tx and rx ring.
300 */
301struct ix_queue {
302 struct adapter *adapter;
303 u32 msix; /* This queue's MSI-X vector */
304 u32 eims; /* This queue's EIMS bit */
305 u32 eitr_setting;
306 u32 me;
307 struct resource *res;
308 void *tag;
309 int busy;
310 struct tx_ring *txr;
311 struct rx_ring *rxr;
312 struct task que_task;
313 struct taskqueue *tq;
314 u64 irqs;
315};
316
317/*
318 * The transmit ring, one per queue
319 */
320struct tx_ring {
321 struct adapter *adapter;
322 struct mtx tx_mtx;
323 u32 me;
324 u32 tail;
325 int busy;
326 union ixgbe_adv_tx_desc *tx_base;
327 struct ixgbe_tx_buf *tx_buffers;
328 struct ixgbe_dma_alloc txdma;
329 volatile u16 tx_avail;
330 u16 next_avail_desc;
331 u16 next_to_clean;
332 u16 num_desc;
333 u32 txd_cmd;
334 bus_dma_tag_t txtag;
335 char mtx_name[16];
336 struct buf_ring *br;
337 struct task txq_task;
338
339 /* Flow Director */
340 u16 atr_sample;
341 u16 atr_count;
342
343 u32 bytes; /* used for AIM */
344 u32 packets;
345 /* Soft Stats */
346 u64 tso_tx;
347 u64 no_tx_map_avail;
348 u64 no_tx_dma_setup;
349 u64 no_desc_avail;
350 u64 total_packets;
351};
352
353
354/*
355 * The Receive ring, one per rx queue
356 */
357struct rx_ring {
358 struct adapter *adapter;
359 struct mtx rx_mtx;
360 u32 me;
361 u32 tail;
362 union ixgbe_adv_rx_desc *rx_base;
363 struct ixgbe_dma_alloc rxdma;
364 struct lro_ctrl lro;
365 bool lro_enabled;
366 bool hw_rsc;
367 bool vtag_strip;
368 u16 next_to_refresh;
369 u16 next_to_check;
370 u16 num_desc;
371 u16 mbuf_sz;
372 char mtx_name[16];
373 struct ixgbe_rx_buf *rx_buffers;
374 bus_dma_tag_t ptag;
375
376 u32 bytes; /* Used for AIM calc */
377 u32 packets;
378
379 /* Soft stats */
380 u64 rx_irq;
381 u64 rx_copies;
382 u64 rx_packets;
383 u64 rx_bytes;
384 u64 rx_discarded;
385 u64 rsc_num;
386
387 /* Flow Director */
388 u64 flm;
389};
390
391#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */
392
393struct ixgbe_vf {
394 u_int pool;
395 u_int rar_index;
396 u_int max_frame_size;
397 uint32_t flags;
398 uint8_t ether_addr[ETHER_ADDR_LEN];
399 uint16_t mc_hash[IXGBE_MAX_VF_MC];
400 uint16_t num_mc_hashes;
401 uint16_t default_vlan;
402 uint16_t vlan_tag;
403 uint16_t api_ver;
404};
405
406/* Our adapter structure */
407struct adapter {
408 struct ixgbe_hw hw;
409 struct ixgbe_osdep osdep;
410
411 device_t dev;
412 struct ifnet *ifp;
413
414 struct resource *pci_mem;
415 struct resource *msix_mem;
416
417 /*
418 * Interrupt resources: this set is
419 * either used for legacy, or for Link
420 * when doing MSI-X
421 */
422 void *tag;
423 struct resource *res;
424
425 struct ifmedia media;
426 struct callout timer;
427 int link_rid;
428 int if_flags;
429
430 struct mtx core_mtx;
431
432 eventhandler_tag vlan_attach;
433 eventhandler_tag vlan_detach;
434
435 u16 num_vlans;
436 u16 num_queues;
437
438 /*
439 * Shadow VFTA table, this is needed because
440 * the real vlan filter table gets cleared during
441 * a soft reset and the driver needs to be able
442 * to repopulate it.
443 */
444 u32 shadow_vfta[IXGBE_VFTA_SIZE];
445
446 /* Info about the interface */
447 int advertise; /* link speeds */
448 int enable_aim; /* adaptive interrupt moderation */
449 bool link_active;
450 u16 max_frame_size;
451 u16 num_segs;
452 u32 link_speed;
453 bool link_up;
454 u32 vector;
455 u16 dmac;
456 u32 phy_layer;
457
458 /* Power management-related */
459 bool wol_support;
460 u32 wufc;
461
462 /* Mbuf cluster size */
463 u32 rx_mbuf_sz;
464
465 /* Support for pluggable optics */
466 bool sfp_probe;
467 struct task link_task; /* Link tasklet */
468 struct task mod_task; /* SFP tasklet */
469 struct task msf_task; /* Multispeed Fiber */
470 struct task mbx_task; /* VF -> PF mailbox interrupt */
471
472 /* Flow Director */
473 int fdir_reinit;
474 struct task fdir_task;
475
476 struct task phy_task; /* PHY intr tasklet */
477 struct taskqueue *tq;
478
479 /*
480 * Queues:
481 * This is the irq holder, it has
482 * and RX/TX pair or rings associated
483 * with it.
484 */
485 struct ix_queue *queues;
486
487 /*
488 * Transmit rings
489 * Allocated at run time, an array of rings
490 */
491 struct tx_ring *tx_rings;
492 u32 num_tx_desc;
493 u32 tx_process_limit;
494
495 /*
496 * Receive rings
497 * Allocated at run time, an array of rings
498 */
499 struct rx_ring *rx_rings;
500 u64 active_queues;
501 u32 num_rx_desc;
502 u32 rx_process_limit;
503
504 /* Multicast array memory */
505 struct ixgbe_mc_addr *mta;
506
507 /* SR-IOV */
508 int iov_mode;
509 int num_vfs;
510 int pool;
511 struct ixgbe_vf *vfs;
512
513 /* Bypass */
514 struct ixgbe_bp_data bypass;
515
516 /* Netmap */
517 void (*init_locked)(struct adapter *);
518 void (*stop_locked)(void *);
519
520 /* Misc stats maintained by the driver */
521 unsigned long dropped_pkts;
522 unsigned long mbuf_defrag_failed;
523 unsigned long mbuf_header_failed;
524 unsigned long mbuf_packet_failed;
525 unsigned long watchdog_events;
526 unsigned long link_irq;
527 union {
528 struct ixgbe_hw_stats pf;
529 struct ixgbevf_hw_stats vf;
530 } stats;
531#if __FreeBSD_version >= 1100036
532 /* counter(9) stats */
533 u64 ipackets;
534 u64 ierrors;
535 u64 opackets;
536 u64 oerrors;
537 u64 ibytes;
538 u64 obytes;
539 u64 imcasts;
540 u64 omcasts;
541 u64 iqdrops;
542 u64 noproto;
543#endif
544 /* Feature capable/enabled flags. See ixgbe_features.h */
545 u32 feat_cap;
546 u32 feat_en;
547};
548
549
550/* Precision Time Sync (IEEE 1588) defines */
551#define ETHERTYPE_IEEE1588 0x88F7
552#define PICOSECS_PER_TICK 20833
553#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */
554#define IXGBE_ADVTXD_TSTAMP 0x00080000
555
556
557#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
558 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
559#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
560#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
561#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
562#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
--- 32 unchanged lines hidden (view full) ---
595#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count)
596#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count)
597#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count)
598#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count)
599#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count)
600#endif
601
602/* External PHY register addresses */
603#define IXGBE_PHY_CURRENT_TEMP 0xC820
604#define IXGBE_PHY_OVERTEMP_STATUS 0xC830
605
606/* Sysctl help messages; displayed with sysctl -d */
607#define IXGBE_SYSCTL_DESC_ADV_SPEED \
608 "\nControl advertised link speed using these flags:\n" \
609 "\t0x1 - advertise 100M\n" \
610 "\t0x2 - advertise 1G\n" \
611 "\t0x4 - advertise 10G\n" \
612 "\t0x8 - advertise 10M\n\n" \
613 "\t100M and 10M are only supported on certain adapters.\n"
614
615#define IXGBE_SYSCTL_DESC_SET_FC \
616 "\nSet flow control mode using these values:\n" \
617 "\t0 - off\n" \
618 "\t1 - rx pause\n" \
619 "\t2 - tx pause\n" \
620 "\t3 - tx and rx pause"
621
622/* Workaround to make 8.0 buildable */
623#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
624static __inline int
625drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
626{
627#ifdef ALTQ
628 if (ALTQ_IS_ENABLED(&ifp->if_snd))
629 return (1);
630#endif
631 return (!buf_ring_empty(br));
632}
633#endif
634
635/*
636 * Find the number of unrefreshed RX descriptors
637 */
638static inline u16
639ixgbe_rx_unrefreshed(struct rx_ring *rxr)
640{
641 if (rxr->next_to_check > rxr->next_to_refresh)
642 return (rxr->next_to_check - rxr->next_to_refresh - 1);
643 else
644 return ((rxr->num_desc + rxr->next_to_check) -
645 rxr->next_to_refresh - 1);
646}
647
648static inline int
649ixgbe_legacy_ring_empty(struct ifnet *ifp, struct buf_ring *dummy)
650{
651 UNREFERENCED_1PARAMETER(dummy);
652
653 return IFQ_DRV_IS_EMPTY(&ifp->if_snd);
654}
655
656/*
657 * This checks for a zero mac addr, something that will be likely
658 * unless the Admin on the Host has created one.
659 */
660static inline bool
661ixv_check_ether_addr(u8 *addr)
662{
663 bool status = TRUE;
664
665 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 &&
666 addr[3] == 0 && addr[4]== 0 && addr[5] == 0))
667 status = FALSE;
668
669 return (status);
670}
671
672/* Shared Prototypes */
673void ixgbe_legacy_start(struct ifnet *);
674int ixgbe_legacy_start_locked(struct ifnet *, struct tx_ring *);
675int ixgbe_mq_start(struct ifnet *, struct mbuf *);
676int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *);
677void ixgbe_qflush(struct ifnet *);
678void ixgbe_deferred_mq_start(void *, int);
679
680int ixgbe_allocate_queues(struct adapter *);
681int ixgbe_setup_transmit_structures(struct adapter *);
682void ixgbe_free_transmit_structures(struct adapter *);
683int ixgbe_setup_receive_structures(struct adapter *);
684void ixgbe_free_receive_structures(struct adapter *);
685void ixgbe_txeof(struct tx_ring *);
686bool ixgbe_rxeof(struct ix_queue *);
687
688#include "ixgbe_bypass.h"
689#include "ixgbe_sriov.h"
690#include "ixgbe_fdir.h"
691#include "ixgbe_rss.h"
692#include "ixgbe_netmap.h"
693
694#endif /* _IXGBE_H_ */