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ispvar.h (236427) ispvar.h (237210)
1/* $FreeBSD: head/sys/dev/isp/ispvar.h 236427 2012-06-01 23:29:48Z mjacob $ */
1/* $FreeBSD: head/sys/dev/isp/ispvar.h 237210 2012-06-17 21:39:40Z mjacob $ */
2/*-
3 * Copyright (c) 1997-2009 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *

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443 *
444 * This structure is replicated across multiple channels for multi-id
445 * capapble chipsets, with some entities different on a per-channel basis.
446 */
447
448typedef struct {
449 uint32_t
450 link_active : 1,
2/*-
3 * Copyright (c) 1997-2009 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *

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443 *
444 * This structure is replicated across multiple channels for multi-id
445 * capapble chipsets, with some entities different on a per-channel basis.
446 */
447
448typedef struct {
449 uint32_t
450 link_active : 1,
451 npiv_fabric : 1,
452 inorder : 1,
453 sendmarker : 1,
454 role : 2,
455 isp_gbspeed : 4,
456 isp_loopstate : 4, /* Current Loop State */
457 isp_fwstate : 4, /* ISP F/W state */
458 isp_topo : 3, /* Connection Type */
459 loop_seen_once : 1;
460
461 uint32_t : 8,
462 isp_portid : 24; /* S_ID */
463
464
465 uint16_t isp_fwoptions;
466 uint16_t isp_xfwoptions;
467 uint16_t isp_zfwoptions;
468 uint16_t isp_loopid; /* hard loop id */
469 uint16_t isp_sns_hdl; /* N-port handle for SNS */
470 uint16_t isp_lasthdl; /* only valid for channel 0 */
471 uint16_t isp_maxalloc;
451 sendmarker : 1,
452 role : 2,
453 isp_gbspeed : 4,
454 isp_loopstate : 4, /* Current Loop State */
455 isp_fwstate : 4, /* ISP F/W state */
456 isp_topo : 3, /* Connection Type */
457 loop_seen_once : 1;
458
459 uint32_t : 8,
460 isp_portid : 24; /* S_ID */
461
462
463 uint16_t isp_fwoptions;
464 uint16_t isp_xfwoptions;
465 uint16_t isp_zfwoptions;
466 uint16_t isp_loopid; /* hard loop id */
467 uint16_t isp_sns_hdl; /* N-port handle for SNS */
468 uint16_t isp_lasthdl; /* only valid for channel 0 */
469 uint16_t isp_maxalloc;
470 uint16_t isp_fabric_params;
472 uint8_t isp_retry_delay;
473 uint8_t isp_retry_count;
474
475 /*
476 * Current active WWNN/WWPN
477 */
478 uint64_t isp_wwnn;
479 uint64_t isp_wwpn;

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557 struct ispmdvec * isp_mdvec;
558
559 /*
560 * (Mostly) nonvolatile state. Board specific parameters
561 * may contain some volatile state (e.g., current loop state).
562 */
563
564 void * isp_param; /* type specific */
471 uint8_t isp_retry_delay;
472 uint8_t isp_retry_count;
473
474 /*
475 * Current active WWNN/WWPN
476 */
477 uint64_t isp_wwnn;
478 uint64_t isp_wwpn;

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556 struct ispmdvec * isp_mdvec;
557
558 /*
559 * (Mostly) nonvolatile state. Board specific parameters
560 * may contain some volatile state (e.g., current loop state).
561 */
562
563 void * isp_param; /* type specific */
564 uint64_t isp_fwattr; /* firmware attributes */
565 uint16_t isp_fwrev[3]; /* Loaded F/W revision */
566 uint16_t isp_maxcmds; /* max possible I/O cmds */
567 uint8_t isp_type; /* HBA Chip Type */
568 uint8_t isp_revision; /* HBA Chip H/W Revision */
565 uint16_t isp_fwrev[3]; /* Loaded F/W revision */
566 uint16_t isp_maxcmds; /* max possible I/O cmds */
567 uint8_t isp_type; /* HBA Chip Type */
568 uint8_t isp_revision; /* HBA Chip H/W Revision */
569 uint16_t isp_nchan; /* number of channels */
569 uint32_t isp_maxluns; /* maximum luns supported */
570
571 uint32_t isp_clock : 8, /* input clock */
572 : 4,
573 isp_port : 1, /* 23XX/24XX only */
574 isp_open : 1, /* opened (ioctl) */
575 isp_bustype : 1, /* SBus or PCI */
576 isp_loaded_fw : 1, /* loaded firmware */
577 isp_dblev : 16; /* debug log mask */
578
570 uint32_t isp_maxluns; /* maximum luns supported */
571
572 uint32_t isp_clock : 8, /* input clock */
573 : 4,
574 isp_port : 1, /* 23XX/24XX only */
575 isp_open : 1, /* opened (ioctl) */
576 isp_bustype : 1, /* SBus or PCI */
577 isp_loaded_fw : 1, /* loaded firmware */
578 isp_dblev : 16; /* debug log mask */
579
579 uint16_t isp_fwattr; /* firmware attributes */
580 uint16_t isp_nchan; /* number of channels */
581
582 uint32_t isp_confopts; /* config options */
583
584 uint32_t isp_rqstinrp; /* register for REQINP */
585 uint32_t isp_rqstoutrp; /* register for REQOUTP */
586 uint32_t isp_respinrp; /* register for RESINP */
587 uint32_t isp_respoutrp; /* register for RESOUTP */
588

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612 isp_nactive : 16; /* how many commands active */
613 volatile mbreg_t isp_curmbx; /* currently active mailbox command */
614 volatile uint32_t isp_reqodx; /* index of last ISP pickup */
615 volatile uint32_t isp_reqidx; /* index of next request */
616 volatile uint32_t isp_residx; /* index of next result */
617 volatile uint32_t isp_resodx; /* index of next result */
618 volatile uint32_t isp_obits; /* mailbox command output */
619 volatile uint32_t isp_serno; /* rolling serial number */
580
581 uint32_t isp_confopts; /* config options */
582
583 uint32_t isp_rqstinrp; /* register for REQINP */
584 uint32_t isp_rqstoutrp; /* register for REQOUTP */
585 uint32_t isp_respinrp; /* register for RESINP */
586 uint32_t isp_respoutrp; /* register for RESOUTP */
587

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611 isp_nactive : 16; /* how many commands active */
612 volatile mbreg_t isp_curmbx; /* currently active mailbox command */
613 volatile uint32_t isp_reqodx; /* index of last ISP pickup */
614 volatile uint32_t isp_reqidx; /* index of next request */
615 volatile uint32_t isp_residx; /* index of next result */
616 volatile uint32_t isp_resodx; /* index of next result */
617 volatile uint32_t isp_obits; /* mailbox command output */
618 volatile uint32_t isp_serno; /* rolling serial number */
620 volatile uint16_t isp_mboxtmp[MAILBOX_STORAGE];
619 volatile uint16_t isp_mboxtmp[MAX_MAILBOX];
621 volatile uint16_t isp_lastmbxcmd; /* last mbox command sent */
622 volatile uint16_t isp_mbxwrk0;
623 volatile uint16_t isp_mbxwrk1;
624 volatile uint16_t isp_mbxwrk2;
625 volatile uint16_t isp_mbxwrk8;
626 volatile uint16_t isp_seqno; /* running sequence number */
627 void * isp_mbxworkp;
628

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690#define ISP_CFG_LPORT 0x00 /* prefer {N/F}L-Port connection */
691#define ISP_CFG_NPORT 0x04 /* prefer {N/F}-Port connection */
692#define ISP_CFG_NPORT_ONLY 0x08 /* insist on {N/F}-Port connection */
693#define ISP_CFG_LPORT_ONLY 0x0C /* insist on {N/F}L-Port connection */
694#define ISP_CFG_OWNFSZ 0x400 /* override NVRAM frame size */
695#define ISP_CFG_OWNLOOPID 0x800 /* override NVRAM loopid */
696#define ISP_CFG_OWNEXCTHROTTLE 0x1000 /* override NVRAM execution throttle */
697#define ISP_CFG_FOURGB 0x2000 /* force 4GB connection (24XX only) */
620 volatile uint16_t isp_lastmbxcmd; /* last mbox command sent */
621 volatile uint16_t isp_mbxwrk0;
622 volatile uint16_t isp_mbxwrk1;
623 volatile uint16_t isp_mbxwrk2;
624 volatile uint16_t isp_mbxwrk8;
625 volatile uint16_t isp_seqno; /* running sequence number */
626 void * isp_mbxworkp;
627

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689#define ISP_CFG_LPORT 0x00 /* prefer {N/F}L-Port connection */
690#define ISP_CFG_NPORT 0x04 /* prefer {N/F}-Port connection */
691#define ISP_CFG_NPORT_ONLY 0x08 /* insist on {N/F}-Port connection */
692#define ISP_CFG_LPORT_ONLY 0x0C /* insist on {N/F}L-Port connection */
693#define ISP_CFG_OWNFSZ 0x400 /* override NVRAM frame size */
694#define ISP_CFG_OWNLOOPID 0x800 /* override NVRAM loopid */
695#define ISP_CFG_OWNEXCTHROTTLE 0x1000 /* override NVRAM execution throttle */
696#define ISP_CFG_FOURGB 0x2000 /* force 4GB connection (24XX only) */
697#define ISP_CFG_EIGHTGB 0x4000 /* force 8GB connection (25XX only) */
698
699/*
700 * For each channel, the outer layers should know what role that channel
701 * will take: ISP_ROLE_NONE, ISP_ROLE_INITIATOR, ISP_ROLE_TARGET,
702 * ISP_ROLE_BOTH.
703 *
704 * If you set ISP_ROLE_NONE, the cards will be reset, new firmware loaded,
705 * NVRAM read, and defaults set, but any further initialization (e.g.

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1035 * MBOX_WAIT_COMPLETE(ispsoftc_t *, mbreg_t *) wait for cmd to be done
1036 * MBOX_NOTIFY_COMPLETE(ispsoftc_t *) notification of mbox cmd donee
1037 * MBOX_RELEASE(ispsoftc_t *) release lock on mailbox regs
1038 *
1039 * FC_SCRATCH_ACQUIRE(ispsoftc_t *, chan) acquire lock on FC scratch area
1040 * return -1 if you cannot
1041 * FC_SCRATCH_RELEASE(ispsoftc_t *, chan) acquire lock on FC scratch area
1042 *
698
699/*
700 * For each channel, the outer layers should know what role that channel
701 * will take: ISP_ROLE_NONE, ISP_ROLE_INITIATOR, ISP_ROLE_TARGET,
702 * ISP_ROLE_BOTH.
703 *
704 * If you set ISP_ROLE_NONE, the cards will be reset, new firmware loaded,
705 * NVRAM read, and defaults set, but any further initialization (e.g.

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1035 * MBOX_WAIT_COMPLETE(ispsoftc_t *, mbreg_t *) wait for cmd to be done
1036 * MBOX_NOTIFY_COMPLETE(ispsoftc_t *) notification of mbox cmd donee
1037 * MBOX_RELEASE(ispsoftc_t *) release lock on mailbox regs
1038 *
1039 * FC_SCRATCH_ACQUIRE(ispsoftc_t *, chan) acquire lock on FC scratch area
1040 * return -1 if you cannot
1041 * FC_SCRATCH_RELEASE(ispsoftc_t *, chan) acquire lock on FC scratch area
1042 *
1043 * FCP_NEXT_CRN(ispsoftc_t *, XS_T *, rslt, channel, target, lun) generate the next command reference number. XS_T * may be null.
1044 *
1043 * SCSI_GOOD SCSI 'Good' Status
1044 * SCSI_CHECK SCSI 'Check Condition' Status
1045 * SCSI_BUSY SCSI 'Busy' Status
1046 * SCSI_QFULL SCSI 'Queue Full' Status
1047 *
1048 * XS_T Platform SCSI transaction type (i.e., command for HBA)
1049 * XS_DMA_ADDR_T Platform PCI DMA Address Type
1050 * XS_GET_DMA_SEG(..) Get 32 bit dma segment list value

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1045 * SCSI_GOOD SCSI 'Good' Status
1046 * SCSI_CHECK SCSI 'Check Condition' Status
1047 * SCSI_BUSY SCSI 'Busy' Status
1048 * SCSI_QFULL SCSI 'Queue Full' Status
1049 *
1050 * XS_T Platform SCSI transaction type (i.e., command for HBA)
1051 * XS_DMA_ADDR_T Platform PCI DMA Address Type
1052 * XS_GET_DMA_SEG(..) Get 32 bit dma segment list value

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