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ispvar.h (155228) ispvar.h (155704)
1/* $FreeBSD: head/sys/dev/isp/ispvar.h 155228 2006-02-02 21:31:34Z mjacob $ */
1/* $FreeBSD: head/sys/dev/isp/ispvar.h 155704 2006-02-15 00:31:48Z mjacob $ */
2/*-
3 * Soft Definitions for for Qlogic ISP SCSI adapters.
4 *
5 * Copyright (c) 1997-2006 by Matthew Jacob
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions

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27 * SUCH DAMAGE.
28 */
29
30#ifndef _ISPVAR_H
31#define _ISPVAR_H
32
33#if defined(__NetBSD__) || defined(__OpenBSD__)
34#include <dev/ic/ispmbox.h>
2/*-
3 * Soft Definitions for for Qlogic ISP SCSI adapters.
4 *
5 * Copyright (c) 1997-2006 by Matthew Jacob
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions

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27 * SUCH DAMAGE.
28 */
29
30#ifndef _ISPVAR_H
31#define _ISPVAR_H
32
33#if defined(__NetBSD__) || defined(__OpenBSD__)
34#include <dev/ic/ispmbox.h>
35#ifdef ISP_TARGET_MODE
36#include <dev/ic/isp_target.h>
37#include <dev/ic/isp_tpublic.h>
38#endif
35#endif
39#endif
40#ifdef __FreeBSD__
41#include <dev/isp/ispmbox.h>
36#ifdef __FreeBSD__
37#include <dev/isp/ispmbox.h>
42#ifdef ISP_TARGET_MODE
43#include <dev/isp/isp_target.h>
44#include <dev/isp/isp_tpublic.h>
45#endif
38#endif
46#endif
47#ifdef __linux__
48#include "ispmbox.h"
39#ifdef __linux__
40#include "ispmbox.h"
49#ifdef ISP_TARGET_MODE
50#include "isp_target.h"
51#include "isp_tpublic.h"
52#endif
41#endif
42#ifdef __svr4__
43#include "ispmbox.h"
53#endif
54
55#define ISP_CORE_VERSION_MAJOR 2
44#endif
45
46#define ISP_CORE_VERSION_MAJOR 2
56#define ISP_CORE_VERSION_MINOR 10
47#define ISP_CORE_VERSION_MINOR 11
57
58/*
59 * Vector for bus specific code to provide specific services.
60 */
48
49/*
50 * Vector for bus specific code to provide specific services.
51 */
61struct ispsoftc;
52typedef struct ispsoftc ispsoftc_t;
62struct ispmdvec {
63 int (*dv_rd_isr)
53struct ispmdvec {
54 int (*dv_rd_isr)
64 (struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *);
65 u_int16_t (*dv_rd_reg) (struct ispsoftc *, int);
66 void (*dv_wr_reg) (struct ispsoftc *, int, u_int16_t);
67 int (*dv_mbxdma) (struct ispsoftc *);
68 int (*dv_dmaset) (struct ispsoftc *,
69 XS_T *, ispreq_t *, u_int16_t *, u_int16_t);
70 void (*dv_dmaclr)
71 (struct ispsoftc *, XS_T *, u_int16_t);
72 void (*dv_reset0) (struct ispsoftc *);
73 void (*dv_reset1) (struct ispsoftc *);
74 void (*dv_dregs) (struct ispsoftc *, const char *);
75 u_int16_t *dv_ispfw; /* ptr to f/w */
76 u_int16_t dv_conf1;
77 u_int16_t dv_clock; /* clock frequency */
55 (ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
56 uint16_t (*dv_rd_reg) (ispsoftc_t *, int);
57 void (*dv_wr_reg) (ispsoftc_t *, int, uint16_t);
58 int (*dv_mbxdma) (ispsoftc_t *);
59 int (*dv_dmaset)
60 (ispsoftc_t *, XS_T *, ispreq_t *, uint16_t *, uint16_t);
61 void (*dv_dmaclr) (ispsoftc_t *, XS_T *, uint16_t);
62 void (*dv_reset0) (ispsoftc_t *);
63 void (*dv_reset1) (ispsoftc_t *);
64 void (*dv_dregs) (ispsoftc_t *, const char *);
65 uint16_t *dv_ispfw; /* ptr to f/w */
66 uint16_t dv_conf1;
67 uint16_t dv_clock; /* clock frequency */
78};
79
80/*
81 * Overall parameters
82 */
83#define MAX_TARGETS 16
84#define MAX_FC_TARG 256
85#define ISP_MAX_TARGETS(isp) (IS_FC(isp)? MAX_FC_TARG : MAX_TARGETS)
86#define ISP_MAX_LUNS(isp) (isp)->isp_maxluns
87
88/*
68};
69
70/*
71 * Overall parameters
72 */
73#define MAX_TARGETS 16
74#define MAX_FC_TARG 256
75#define ISP_MAX_TARGETS(isp) (IS_FC(isp)? MAX_FC_TARG : MAX_TARGETS)
76#define ISP_MAX_LUNS(isp) (isp)->isp_maxluns
77
78/*
89 * 'Types'
90 */
91#ifdef ISP_DAC_SUPPORTED
92typedef u_int64_t isp_dma_addr_t;
93#else
94typedef u_int32_t isp_dma_addr_t;
95#endif
96
97/*
98 * Macros to access ISP registers through bus specific layers-
99 * mostly wrappers to vector through the mdvec structure.
100 */
101#define ISP_READ_ISR(isp, isrp, semap, mbox0p) \
102 (*(isp)->isp_mdvec->dv_rd_isr)(isp, isrp, semap, mbox0p)
103
104#define ISP_READ(isp, reg) \
105 (*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))
106
107#define ISP_WRITE(isp, reg, val) \
108 (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))
109
110#define ISP_MBOXDMASETUP(isp) \
111 (*(isp)->isp_mdvec->dv_mbxdma)((isp))
112
113#define ISP_DMASETUP(isp, xs, req, iptrp, optr) \
114 (*(isp)->isp_mdvec->dv_dmaset)((isp), (xs), (req), (iptrp), (optr))
115
79 * Macros to access ISP registers through bus specific layers-
80 * mostly wrappers to vector through the mdvec structure.
81 */
82#define ISP_READ_ISR(isp, isrp, semap, mbox0p) \
83 (*(isp)->isp_mdvec->dv_rd_isr)(isp, isrp, semap, mbox0p)
84
85#define ISP_READ(isp, reg) \
86 (*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))
87
88#define ISP_WRITE(isp, reg, val) \
89 (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))
90
91#define ISP_MBOXDMASETUP(isp) \
92 (*(isp)->isp_mdvec->dv_mbxdma)((isp))
93
94#define ISP_DMASETUP(isp, xs, req, iptrp, optr) \
95 (*(isp)->isp_mdvec->dv_dmaset)((isp), (xs), (req), (iptrp), (optr))
96
116#define ISP_DMAFREE(isp, xs, hndl) \
117 if ((isp)->isp_mdvec->dv_dmaclr) \
97#define ISP_DMAFREE(isp, xs, hndl) \
98 if ((isp)->isp_mdvec->dv_dmaclr) \
118 (*(isp)->isp_mdvec->dv_dmaclr)((isp), (xs), (hndl))
119
120#define ISP_RESET0(isp) \
121 if ((isp)->isp_mdvec->dv_reset0) (*(isp)->isp_mdvec->dv_reset0)((isp))
122#define ISP_RESET1(isp) \
123 if ((isp)->isp_mdvec->dv_reset1) (*(isp)->isp_mdvec->dv_reset1)((isp))
124#define ISP_DUMPREGS(isp, m) \
125 if ((isp)->isp_mdvec->dv_dregs) (*(isp)->isp_mdvec->dv_dregs)((isp),(m))

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151/* Both request and result queue length must be a power of two */
152#define RQUEST_QUEUE_LEN(x) MAXISPREQUEST(x)
153#ifdef ISP_TARGET_MODE
154#define RESULT_QUEUE_LEN(x) MAXISPREQUEST(x)
155#else
156#define RESULT_QUEUE_LEN(x) \
157 (((MAXISPREQUEST(x) >> 2) < 64)? 64 : MAXISPREQUEST(x) >> 2)
158#endif
99 (*(isp)->isp_mdvec->dv_dmaclr)((isp), (xs), (hndl))
100
101#define ISP_RESET0(isp) \
102 if ((isp)->isp_mdvec->dv_reset0) (*(isp)->isp_mdvec->dv_reset0)((isp))
103#define ISP_RESET1(isp) \
104 if ((isp)->isp_mdvec->dv_reset1) (*(isp)->isp_mdvec->dv_reset1)((isp))
105#define ISP_DUMPREGS(isp, m) \
106 if ((isp)->isp_mdvec->dv_dregs) (*(isp)->isp_mdvec->dv_dregs)((isp),(m))

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132/* Both request and result queue length must be a power of two */
133#define RQUEST_QUEUE_LEN(x) MAXISPREQUEST(x)
134#ifdef ISP_TARGET_MODE
135#define RESULT_QUEUE_LEN(x) MAXISPREQUEST(x)
136#else
137#define RESULT_QUEUE_LEN(x) \
138 (((MAXISPREQUEST(x) >> 2) < 64)? 64 : MAXISPREQUEST(x) >> 2)
139#endif
159#define ISP_QUEUE_ENTRY(q, idx) ((q) + ((idx) * QENTRY_LEN))
140#define ISP_QUEUE_ENTRY(q, idx) (((uint8_t *)q) + ((idx) * QENTRY_LEN))
160#define ISP_QUEUE_SIZE(n) ((n) * QENTRY_LEN)
161#define ISP_NXT_QENTRY(idx, qlen) (((idx) + 1) & ((qlen)-1))
162#define ISP_QFREE(in, out, qlen) \
163 ((in == out)? (qlen - 1) : ((in > out)? \
164 ((qlen - 1) - (in - out)) : (out - in - 1)))
165#define ISP_QAVAIL(isp) \
166 ISP_QFREE(isp->isp_reqidx, isp->isp_reqodx, RQUEST_QUEUE_LEN(isp))
167
168#define ISP_ADD_REQUEST(isp, nxti) \
169 MEMORYBARRIER(isp, SYNC_REQUEST, isp->isp_reqidx, QENTRY_LEN); \
170 WRITE_REQUEST_QUEUE_IN_POINTER(isp, nxti); \
171 isp->isp_reqidx = nxti
172
173/*
174 * SCSI Specific Host Adapter Parameters- per bus, per target
175 */
176typedef struct {
141#define ISP_QUEUE_SIZE(n) ((n) * QENTRY_LEN)
142#define ISP_NXT_QENTRY(idx, qlen) (((idx) + 1) & ((qlen)-1))
143#define ISP_QFREE(in, out, qlen) \
144 ((in == out)? (qlen - 1) : ((in > out)? \
145 ((qlen - 1) - (in - out)) : (out - in - 1)))
146#define ISP_QAVAIL(isp) \
147 ISP_QFREE(isp->isp_reqidx, isp->isp_reqodx, RQUEST_QUEUE_LEN(isp))
148
149#define ISP_ADD_REQUEST(isp, nxti) \
150 MEMORYBARRIER(isp, SYNC_REQUEST, isp->isp_reqidx, QENTRY_LEN); \
151 WRITE_REQUEST_QUEUE_IN_POINTER(isp, nxti); \
152 isp->isp_reqidx = nxti
153
154/*
155 * SCSI Specific Host Adapter Parameters- per bus, per target
156 */
157typedef struct {
177 u_int isp_gotdparms : 1,
158 uint32_t isp_gotdparms : 1,
178 isp_req_ack_active_neg : 1,
179 isp_data_line_active_neg: 1,
180 isp_cmd_dma_burst_enable: 1,
181 isp_data_dma_burst_enabl: 1,
182 isp_fifo_threshold : 3,
183 isp_ultramode : 1,
184 isp_diffmode : 1,
185 isp_lvdmode : 1,
186 isp_fast_mttr : 1, /* fast sram */
187 isp_initiator_id : 4,
188 isp_async_data_setup : 4;
159 isp_req_ack_active_neg : 1,
160 isp_data_line_active_neg: 1,
161 isp_cmd_dma_burst_enable: 1,
162 isp_data_dma_burst_enabl: 1,
163 isp_fifo_threshold : 3,
164 isp_ultramode : 1,
165 isp_diffmode : 1,
166 isp_lvdmode : 1,
167 isp_fast_mttr : 1, /* fast sram */
168 isp_initiator_id : 4,
169 isp_async_data_setup : 4;
189 u_int16_t isp_selection_timeout;
190 u_int16_t isp_max_queue_depth;
191 u_int8_t isp_tag_aging;
192 u_int8_t isp_bus_reset_delay;
193 u_int8_t isp_retry_count;
194 u_int8_t isp_retry_delay;
170 uint16_t isp_selection_timeout;
171 uint16_t isp_max_queue_depth;
172 uint8_t isp_tag_aging;
173 uint8_t isp_bus_reset_delay;
174 uint8_t isp_retry_count;
175 uint8_t isp_retry_delay;
195 struct {
176 struct {
196 u_int32_t
177 uint32_t
197 exc_throttle : 8,
198 : 1,
199 dev_enable : 1, /* ignored */
200 dev_update : 1,
201 dev_refresh : 1,
202 actv_offset : 4,
203 goal_offset : 4,
204 nvrm_offset : 4;
178 exc_throttle : 8,
179 : 1,
180 dev_enable : 1, /* ignored */
181 dev_update : 1,
182 dev_refresh : 1,
183 actv_offset : 4,
184 goal_offset : 4,
185 nvrm_offset : 4;
205 u_int8_t actv_period; /* current sync period */
206 u_int8_t goal_period; /* goal sync period */
207 u_int8_t nvrm_period; /* nvram sync period */
208 u_int16_t actv_flags; /* current device flags */
209 u_int16_t goal_flags; /* goal device flags */
210 u_int16_t nvrm_flags; /* nvram device flags */
186 uint8_t actv_period; /* current sync period */
187 uint8_t goal_period; /* goal sync period */
188 uint8_t nvrm_period; /* nvram sync period */
189 uint16_t actv_flags; /* current device flags */
190 uint16_t goal_flags; /* goal device flags */
191 uint16_t nvrm_flags; /* nvram device flags */
211 } isp_devparam[MAX_TARGETS];
212} sdparam;
213
214/*
215 * Device Flags
216 */
217#define DPARM_DISC 0x8000
218#define DPARM_PARITY 0x4000

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246#define FC_SNS_ID 0x80 /* SNS Server Special ID */
247
248/* #define ISP_USE_GA_NXT 1 */ /* Use GA_NXT with switches */
249#ifndef GA_NXT_MAX
250#define GA_NXT_MAX 256
251#endif
252
253typedef struct {
192 } isp_devparam[MAX_TARGETS];
193} sdparam;
194
195/*
196 * Device Flags
197 */
198#define DPARM_DISC 0x8000
199#define DPARM_PARITY 0x4000

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227#define FC_SNS_ID 0x80 /* SNS Server Special ID */
228
229/* #define ISP_USE_GA_NXT 1 */ /* Use GA_NXT with switches */
230#ifndef GA_NXT_MAX
231#define GA_NXT_MAX 256
232#endif
233
234typedef struct {
254 u_int32_t : 13,
235 uint32_t : 13,
255 isp_gbspeed : 3,
256 : 2,
257 isp_iid_set : 1,
258 loop_seen_once : 1,
259 isp_loopstate : 4, /* Current Loop State */
260 isp_fwstate : 3, /* ISP F/W state */
261 isp_gotdparms : 1,
262 isp_topo : 3,
263 isp_onfabric : 1;
236 isp_gbspeed : 3,
237 : 2,
238 isp_iid_set : 1,
239 loop_seen_once : 1,
240 isp_loopstate : 4, /* Current Loop State */
241 isp_fwstate : 3, /* ISP F/W state */
242 isp_gotdparms : 1,
243 isp_topo : 3,
244 isp_onfabric : 1;
264 u_int32_t : 8,
245 uint32_t : 8,
265 isp_portid : 24; /* S_ID */
246 isp_portid : 24; /* S_ID */
266 u_int16_t isp_fwoptions;
267 u_int16_t isp_iid; /* 'initiator' id */
268 u_int16_t isp_loopid; /* hard loop id */
269 u_int16_t isp_fwattr; /* firmware attributes */
270 u_int8_t isp_execthrottle;
271 u_int8_t isp_retry_delay;
272 u_int8_t isp_retry_count;
273 u_int8_t isp_reserved;
274 u_int16_t isp_maxalloc;
275 u_int16_t isp_maxfrmlen;
276 u_int64_t isp_nodewwn;
277 u_int64_t isp_portwwn;
247 uint16_t isp_fwoptions;
248 uint16_t isp_iid; /* 'initiator' id */
249 uint16_t isp_loopid; /* hard loop id */
250 uint16_t isp_fwattr; /* firmware attributes */
251 uint8_t isp_execthrottle;
252 uint8_t isp_retry_delay;
253 uint8_t isp_retry_count;
254 uint8_t isp_reserved;
255 uint16_t isp_maxalloc;
256 uint16_t isp_maxfrmlen;
257 uint64_t isp_nodewwn;
258 uint64_t isp_portwwn;
278 /*
279 * Port Data Base. This is indexed by 'target', which is invariate.
280 * However, elements within can move around due to loop changes,
281 * so the actual loop ID passed to the F/W is in this structure.
282 * The first time the loop is seen up, loopid will match the index
283 * (except for fabric nodes which are above mapped above FC_SNS_ID
284 * and are completely virtual), but subsequent LIPs can cause things
285 * to move around.
286 */
287 struct lportdb {
259 /*
260 * Port Data Base. This is indexed by 'target', which is invariate.
261 * However, elements within can move around due to loop changes,
262 * so the actual loop ID passed to the F/W is in this structure.
263 * The first time the loop is seen up, loopid will match the index
264 * (except for fabric nodes which are above mapped above FC_SNS_ID
265 * and are completely virtual), but subsequent LIPs can cause things
266 * to move around.
267 */
268 struct lportdb {
288 u_int32_t loopid : 16,
269 uint32_t loopid : 16,
289 : 2,
290 fc4_type : 4,
291 last_fabric_dev : 1,
292 relogin : 1,
293 force_logout : 1,
294 was_fabric_dev : 1,
295 fabric_dev : 1,
296 loggedin : 1,
297 roles : 2,
298 tvalid : 1,
299 valid : 1;
270 : 2,
271 fc4_type : 4,
272 last_fabric_dev : 1,
273 relogin : 1,
274 force_logout : 1,
275 was_fabric_dev : 1,
276 fabric_dev : 1,
277 loggedin : 1,
278 roles : 2,
279 tvalid : 1,
280 valid : 1;
300 u_int32_t port_type : 8,
281 uint32_t port_type : 8,
301 portid : 24;
282 portid : 24;
302 u_int64_t node_wwn;
303 u_int64_t port_wwn;
283 uint64_t node_wwn;
284 uint64_t port_wwn;
304 } portdb[MAX_FC_TARG], tport[FC_PORT_ID];
305
306 /*
307 * Scratch DMA mapped in area to fetch Port Database stuff, etc.
308 */
285 } portdb[MAX_FC_TARG], tport[FC_PORT_ID];
286
287 /*
288 * Scratch DMA mapped in area to fetch Port Database stuff, etc.
289 */
309 caddr_t isp_scratch;
310 isp_dma_addr_t isp_scdma;
290 void * isp_scratch;
291 XS_DMA_ADDR_T isp_scdma;
311#ifdef ISP_FW_CRASH_DUMP
292#ifdef ISP_FW_CRASH_DUMP
312 u_int16_t *isp_dump_data;
293 uint16_t * isp_dump_data;
313#endif
314} fcparam;
315
316#define FW_CONFIG_WAIT 0
317#define FW_WAIT_AL_PA 1
318#define FW_WAIT_LOGIN 2
319#define FW_READY 3
320#define FW_LOSS_OF_SYNC 4

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336#define TOPO_FL_PORT 1
337#define TOPO_N_PORT 2
338#define TOPO_F_PORT 3
339#define TOPO_PTP_STUB 4
340
341/*
342 * Soft Structure per host adapter
343 */
294#endif
295} fcparam;
296
297#define FW_CONFIG_WAIT 0
298#define FW_WAIT_AL_PA 1
299#define FW_WAIT_LOGIN 2
300#define FW_READY 3
301#define FW_LOSS_OF_SYNC 4

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317#define TOPO_FL_PORT 1
318#define TOPO_N_PORT 2
319#define TOPO_F_PORT 3
320#define TOPO_PTP_STUB 4
321
322/*
323 * Soft Structure per host adapter
324 */
344typedef struct ispsoftc {
325struct ispsoftc {
345 /*
346 * Platform (OS) specific data
347 */
348 struct isposinfo isp_osinfo;
349
350 /*
351 * Pointer to bus specific functions and data
352 */
353 struct ispmdvec * isp_mdvec;
354
355 /*
356 * (Mostly) nonvolatile state. Board specific parameters
357 * may contain some volatile state (e.g., current loop state).
358 */
359
360 void * isp_param; /* type specific */
326 /*
327 * Platform (OS) specific data
328 */
329 struct isposinfo isp_osinfo;
330
331 /*
332 * Pointer to bus specific functions and data
333 */
334 struct ispmdvec * isp_mdvec;
335
336 /*
337 * (Mostly) nonvolatile state. Board specific parameters
338 * may contain some volatile state (e.g., current loop state).
339 */
340
341 void * isp_param; /* type specific */
361 u_int16_t isp_fwrev[3]; /* Loaded F/W revision */
362 u_int16_t isp_romfw_rev[3]; /* PROM F/W revision */
363 u_int16_t isp_maxcmds; /* max possible I/O cmds */
364 u_int8_t isp_type; /* HBA Chip Type */
365 u_int8_t isp_revision; /* HBA Chip H/W Revision */
366 u_int32_t isp_maxluns; /* maximum luns supported */
342 uint16_t isp_fwrev[3]; /* Loaded F/W revision */
343 uint16_t isp_romfw_rev[3]; /* PROM F/W revision */
344 uint16_t isp_maxcmds; /* max possible I/O cmds */
345 uint8_t isp_type; /* HBA Chip Type */
346 uint8_t isp_revision; /* HBA Chip H/W Revision */
347 uint32_t isp_maxluns; /* maximum luns supported */
367
348
368 u_int32_t isp_clock : 8, /* input clock */
349 uint32_t isp_clock : 8, /* input clock */
369 : 4,
370 isp_port : 1, /* 23XX only */
371 isp_failed : 1, /* board failed */
372 isp_open : 1, /* opened (ioctl) */
373 isp_touched : 1, /* board ever seen? */
374 isp_bustype : 1, /* SBus or PCI */
375 isp_loaded_fw : 1, /* loaded firmware */
376 isp_role : 2, /* roles supported */
377 isp_dblev : 12; /* debug log mask */
378
350 : 4,
351 isp_port : 1, /* 23XX only */
352 isp_failed : 1, /* board failed */
353 isp_open : 1, /* opened (ioctl) */
354 isp_touched : 1, /* board ever seen? */
355 isp_bustype : 1, /* SBus or PCI */
356 isp_loaded_fw : 1, /* loaded firmware */
357 isp_role : 2, /* roles supported */
358 isp_dblev : 12; /* debug log mask */
359
379 u_int32_t isp_confopts; /* config options */
360 uint32_t isp_confopts; /* config options */
380
361
381 u_int16_t isp_rqstinrp; /* register for REQINP */
382 u_int16_t isp_rqstoutrp; /* register for REQOUTP */
383 u_int16_t isp_respinrp; /* register for RESINP */
384 u_int16_t isp_respoutrp; /* register for RESOUTP */
362 uint16_t isp_rqstinrp; /* register for REQINP */
363 uint16_t isp_rqstoutrp; /* register for REQOUTP */
364 uint16_t isp_respinrp; /* register for RESINP */
365 uint16_t isp_respoutrp; /* register for RESOUTP */
385
386 /*
387 * Instrumentation
388 */
366
367 /*
368 * Instrumentation
369 */
389 u_int64_t isp_intcnt; /* total int count */
390 u_int64_t isp_intbogus; /* spurious int count */
391 u_int64_t isp_intmboxc; /* mbox completions */
392 u_int64_t isp_intoasync; /* other async */
393 u_int64_t isp_rsltccmplt; /* CMDs on result q */
394 u_int64_t isp_fphccmplt; /* CMDs via fastpost */
395 u_int16_t isp_rscchiwater;
396 u_int16_t isp_fpcchiwater;
370 uint64_t isp_intcnt; /* total int count */
371 uint64_t isp_intbogus; /* spurious int count */
372 uint64_t isp_intmboxc; /* mbox completions */
373 uint64_t isp_intoasync; /* other async */
374 uint64_t isp_rsltccmplt; /* CMDs on result q */
375 uint64_t isp_fphccmplt; /* CMDs via fastpost */
376 uint16_t isp_rscchiwater;
377 uint16_t isp_fpcchiwater;
397
398 /*
399 * Volatile state
400 */
401
378
379 /*
380 * Volatile state
381 */
382
402 volatile u_int32_t
383 volatile uint32_t
403 isp_obits : 8, /* mailbox command output */
404 isp_mboxbsy : 1, /* mailbox command active */
405 isp_state : 3,
406 isp_sendmarker : 2, /* send a marker entry */
407 isp_update : 2, /* update parameters */
408 isp_nactive : 16; /* how many commands active */
384 isp_obits : 8, /* mailbox command output */
385 isp_mboxbsy : 1, /* mailbox command active */
386 isp_state : 3,
387 isp_sendmarker : 2, /* send a marker entry */
388 isp_update : 2, /* update parameters */
389 isp_nactive : 16; /* how many commands active */
409 volatile u_int16_t isp_reqodx; /* index of last ISP pickup */
410 volatile u_int16_t isp_reqidx; /* index of next request */
411 volatile u_int16_t isp_residx; /* index of next result */
412 volatile u_int16_t isp_resodx; /* index of next result */
413 volatile u_int16_t isp_rspbsy;
414 volatile u_int16_t isp_lasthdls; /* last handle seed */
415 volatile u_int16_t isp_mboxtmp[MAILBOX_STORAGE];
416 volatile u_int16_t isp_lastmbxcmd; /* last mbox command sent */
417 volatile u_int16_t isp_mbxwrk0;
418 volatile u_int16_t isp_mbxwrk1;
419 volatile u_int16_t isp_mbxwrk2;
390 volatile uint16_t isp_reqodx; /* index of last ISP pickup */
391 volatile uint16_t isp_reqidx; /* index of next request */
392 volatile uint16_t isp_residx; /* index of next result */
393 volatile uint16_t isp_resodx; /* index of next result */
394 volatile uint16_t isp_rspbsy;
395 volatile uint16_t isp_lasthdls; /* last handle seed */
396 volatile uint16_t isp_mboxtmp[MAILBOX_STORAGE];
397 volatile uint16_t isp_lastmbxcmd; /* last mbox command sent */
398 volatile uint16_t isp_mbxwrk0;
399 volatile uint16_t isp_mbxwrk1;
400 volatile uint16_t isp_mbxwrk2;
420 void * isp_mbxworkp;
421
422 /*
423 * Active commands are stored here, indexed by handle functions.
424 */
425 XS_T **isp_xflist;
426
427#ifdef ISP_TARGET_MODE
428 /*
429 * Active target commands are stored here, indexed by handle function.
430 */
431 void **isp_tgtlist;
432#endif
433
434 /*
435 * request/result queue pointers and DMA handles for them.
436 */
401 void * isp_mbxworkp;
402
403 /*
404 * Active commands are stored here, indexed by handle functions.
405 */
406 XS_T **isp_xflist;
407
408#ifdef ISP_TARGET_MODE
409 /*
410 * Active target commands are stored here, indexed by handle function.
411 */
412 void **isp_tgtlist;
413#endif
414
415 /*
416 * request/result queue pointers and DMA handles for them.
417 */
437 caddr_t isp_rquest;
438 caddr_t isp_result;
439 isp_dma_addr_t isp_rquest_dma;
440 isp_dma_addr_t isp_result_dma;
441} ispsoftc_t;
418 void * isp_rquest;
419 void * isp_result;
420 XS_DMA_ADDR_T isp_rquest_dma;
421 XS_DMA_ADDR_T isp_result_dma;
422};
442
443#define SDPARAM(isp) ((sdparam *) (isp)->isp_param)
444#define FCPARAM(isp) ((fcparam *) (isp)->isp_param)
445
446/*
447 * ISP Driver Run States
448 */
449#define ISP_NILSTATE 0

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574#define IS_2200(isp) ((isp)->isp_type == ISP_HA_FC_2200)
575#define IS_23XX(isp) ((isp)->isp_type >= ISP_HA_FC_2300)
576#define IS_2300(isp) ((isp)->isp_type == ISP_HA_FC_2300)
577#define IS_2312(isp) ((isp)->isp_type == ISP_HA_FC_2312)
578#define IS_2322(isp) ((isp)->isp_type == ISP_HA_FC_2322)
579#define IS_24XX(isp) ((isp)->isp_type >= ISP_HA_FC_2400)
580
581/*
423
424#define SDPARAM(isp) ((sdparam *) (isp)->isp_param)
425#define FCPARAM(isp) ((fcparam *) (isp)->isp_param)
426
427/*
428 * ISP Driver Run States
429 */
430#define ISP_NILSTATE 0

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555#define IS_2200(isp) ((isp)->isp_type == ISP_HA_FC_2200)
556#define IS_23XX(isp) ((isp)->isp_type >= ISP_HA_FC_2300)
557#define IS_2300(isp) ((isp)->isp_type == ISP_HA_FC_2300)
558#define IS_2312(isp) ((isp)->isp_type == ISP_HA_FC_2312)
559#define IS_2322(isp) ((isp)->isp_type == ISP_HA_FC_2322)
560#define IS_24XX(isp) ((isp)->isp_type >= ISP_HA_FC_2400)
561
562/*
582 * DMA cookie macros
563 * DMA related macros
583 */
564 */
584#ifdef ISP_DAC_SUPPORTRED
585#define DMA_WD3(x) (((x) >> 48) & 0xffff)
586#define DMA_WD2(x) (((x) >> 32) & 0xffff)
587#else
588#define DMA_WD3(x) 0
589#define DMA_WD2(x) 0
590#endif
565#define DMA_WD3(x) ((((uint64_t)x) >> 48) & 0xffff)
566#define DMA_WD2(x) ((((uint64_t)x) >> 32) & 0xffff)
591#define DMA_WD1(x) (((x) >> 16) & 0xffff)
592#define DMA_WD0(x) (((x) & 0xffff))
593
567#define DMA_WD1(x) (((x) >> 16) & 0xffff)
568#define DMA_WD0(x) (((x) & 0xffff))
569
570#define DMA_LO32(x) ((uint32_t) (x))
571#define DMA_HI32(x) ((uint32_t)(((uint64_t)x) >> 32))
572
594/*
595 * Core System Function Prototypes
596 */
597
598/*
599 * Reset Hardware. Totally. Assumes that you'll follow this with
600 * a call to isp_init.
601 */
573/*
574 * Core System Function Prototypes
575 */
576
577/*
578 * Reset Hardware. Totally. Assumes that you'll follow this with
579 * a call to isp_init.
580 */
602void isp_reset(struct ispsoftc *);
581void isp_reset(ispsoftc_t *);
603
604/*
605 * Initialize Hardware to known state
606 */
582
583/*
584 * Initialize Hardware to known state
585 */
607void isp_init(struct ispsoftc *);
586void isp_init(ispsoftc_t *);
608
609/*
610 * Reset the ISP and call completion for any orphaned commands.
611 */
587
588/*
589 * Reset the ISP and call completion for any orphaned commands.
590 */
612void isp_reinit(struct ispsoftc *);
591void isp_reinit(ispsoftc_t *);
613
614#ifdef ISP_FW_CRASH_DUMP
615/*
616 * Dump firmware entry point.
617 */
592
593#ifdef ISP_FW_CRASH_DUMP
594/*
595 * Dump firmware entry point.
596 */
618void isp_fw_dump(struct ispsoftc *isp);
597void isp_fw_dump(ispsoftc_t *isp);
619#endif
620
621/*
622 * Internal Interrupt Service Routine
623 *
624 * The outer layers do the spade work to get the appropriate status register,
625 * semaphore register and first mailbox register (if appropriate). This also
626 * means that most spurious/bogus interrupts not for us can be filtered first.
627 */
598#endif
599
600/*
601 * Internal Interrupt Service Routine
602 *
603 * The outer layers do the spade work to get the appropriate status register,
604 * semaphore register and first mailbox register (if appropriate). This also
605 * means that most spurious/bogus interrupts not for us can be filtered first.
606 */
628void isp_intr(struct ispsoftc *, u_int16_t, u_int16_t, u_int16_t);
607void isp_intr(ispsoftc_t *, uint16_t, uint16_t, uint16_t);
629
630
631/*
632 * Command Entry Point- Platform Dependent layers call into this
633 */
634int isp_start(XS_T *);
608
609
610/*
611 * Command Entry Point- Platform Dependent layers call into this
612 */
613int isp_start(XS_T *);
614
635/* these values are what isp_start returns */
636#define CMD_COMPLETE 101 /* command completed */
637#define CMD_EAGAIN 102 /* busy- maybe retry later */
638#define CMD_QUEUED 103 /* command has been queued for execution */
639#define CMD_RQLATER 104 /* requeue this command later */
640
641/*
642 * Command Completion Point- Core layers call out from this with completed cmds

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687 ISPCTL_SCAN_LOOP, /* (Re)scan Local Loop */
688 ISPCTL_PDB_SYNC, /* Synchronize Port Database */
689 ISPCTL_SEND_LIP, /* Send a LIP */
690 ISPCTL_GET_POSMAP, /* Get FC-AL position map */
691 ISPCTL_RUN_MBOXCMD, /* run a mailbox command */
692 ISPCTL_TOGGLE_TMODE, /* toggle target mode */
693 ISPCTL_GET_PDB /* get a single port database entry */
694} ispctl_t;
615/* these values are what isp_start returns */
616#define CMD_COMPLETE 101 /* command completed */
617#define CMD_EAGAIN 102 /* busy- maybe retry later */
618#define CMD_QUEUED 103 /* command has been queued for execution */
619#define CMD_RQLATER 104 /* requeue this command later */
620
621/*
622 * Command Completion Point- Core layers call out from this with completed cmds

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667 ISPCTL_SCAN_LOOP, /* (Re)scan Local Loop */
668 ISPCTL_PDB_SYNC, /* Synchronize Port Database */
669 ISPCTL_SEND_LIP, /* Send a LIP */
670 ISPCTL_GET_POSMAP, /* Get FC-AL position map */
671 ISPCTL_RUN_MBOXCMD, /* run a mailbox command */
672 ISPCTL_TOGGLE_TMODE, /* toggle target mode */
673 ISPCTL_GET_PDB /* get a single port database entry */
674} ispctl_t;
695int isp_control(struct ispsoftc *, ispctl_t, void *);
675int isp_control(ispsoftc_t *, ispctl_t, void *);
696
697
698/*
699 * Platform Dependent to Internal to External Control Function
700 * (each platform must provide such a function)
701 *
702 * Assumes locks are held.
703 *

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748 ISPASYNC_TARGET_NOTIFY, /* target asynchronous notification event */
749 ISPASYNC_TARGET_ACTION, /* target action requested */
750 ISPASYNC_CONF_CHANGE, /* Platform Configuration Change */
751 ISPASYNC_UNHANDLED_RESPONSE, /* Unhandled Response Entry */
752 ISPASYNC_FW_CRASH, /* Firmware has crashed */
753 ISPASYNC_FW_DUMPED, /* Firmware crashdump taken */
754 ISPASYNC_FW_RESTARTED /* Firmware has been restarted */
755} ispasync_t;
676
677
678/*
679 * Platform Dependent to Internal to External Control Function
680 * (each platform must provide such a function)
681 *
682 * Assumes locks are held.
683 *

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728 ISPASYNC_TARGET_NOTIFY, /* target asynchronous notification event */
729 ISPASYNC_TARGET_ACTION, /* target action requested */
730 ISPASYNC_CONF_CHANGE, /* Platform Configuration Change */
731 ISPASYNC_UNHANDLED_RESPONSE, /* Unhandled Response Entry */
732 ISPASYNC_FW_CRASH, /* Firmware has crashed */
733 ISPASYNC_FW_DUMPED, /* Firmware crashdump taken */
734 ISPASYNC_FW_RESTARTED /* Firmware has been restarted */
735} ispasync_t;
756int isp_async(struct ispsoftc *, ispasync_t, void *);
736int isp_async(ispsoftc_t *, ispasync_t, void *);
757
758#define ISPASYNC_CHANGE_PDB ((void *) 0)
759#define ISPASYNC_CHANGE_SNS ((void *) 1)
760#define ISPASYNC_CHANGE_OTHER ((void *) 2)
761
762/*
763 * Platform Dependent Error and Debug Printout
764 *
765 * Generally this is:
766 *
737
738#define ISPASYNC_CHANGE_PDB ((void *) 0)
739#define ISPASYNC_CHANGE_SNS ((void *) 1)
740#define ISPASYNC_CHANGE_OTHER ((void *) 2)
741
742/*
743 * Platform Dependent Error and Debug Printout
744 *
745 * Generally this is:
746 *
767 * void isp_prt(struct ispsoftc *, int level, const char *, ...)
747 * void isp_prt(ispsoftc_t *, int level, const char *, ...)
768 *
769 * but due to compiler differences on different platforms this won't be
770 * formally done here. Instead, it goes in each platform definition file.
771 */
772
773#define ISP_LOGALL 0x0 /* log always */
774#define ISP_LOGCONFIG 0x1 /* log configuration messages */
775#define ISP_LOGINFO 0x2 /* log informational messages */

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786
787/*
788 * Each Platform provides it's own isposinfo substructure of the ispsoftc
789 * defined above.
790 *
791 * Each platform must also provide the following macros/defines:
792 *
793 *
748 *
749 * but due to compiler differences on different platforms this won't be
750 * formally done here. Instead, it goes in each platform definition file.
751 */
752
753#define ISP_LOGALL 0x0 /* log always */
754#define ISP_LOGCONFIG 0x1 /* log configuration messages */
755#define ISP_LOGINFO 0x2 /* log informational messages */

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766
767/*
768 * Each Platform provides it's own isposinfo substructure of the ispsoftc
769 * defined above.
770 *
771 * Each platform must also provide the following macros/defines:
772 *
773 *
794 * ISP_DAC_SUPPORTED - Is DAC (Dual Address Cycle) is supported?
795 * Basically means whether or not DMA for PCI
796 * PCI cards (Ultra2 or better or FC) works
797 * above 4GB.
798 *
799 * ISP2100_SCRLEN - length for the Fibre Channel scratch DMA area
800 *
801 * MEMZERO(dst, src) platform zeroing function
802 * MEMCPY(dst, src, count) platform copying function
803 * SNPRINTF(buf, bufsize, fmt, ...) snprintf
804 * USEC_DELAY(usecs) microsecond spindelay function
805 * USEC_SLEEP(isp, usecs) microsecond sleep function
806 *
807 * NANOTIME_T nanosecond time type
808 *
809 * GET_NANOTIME(NANOTIME_T *) get current nanotime.
810 *
774 * ISP2100_SCRLEN - length for the Fibre Channel scratch DMA area
775 *
776 * MEMZERO(dst, src) platform zeroing function
777 * MEMCPY(dst, src, count) platform copying function
778 * SNPRINTF(buf, bufsize, fmt, ...) snprintf
779 * USEC_DELAY(usecs) microsecond spindelay function
780 * USEC_SLEEP(isp, usecs) microsecond sleep function
781 *
782 * NANOTIME_T nanosecond time type
783 *
784 * GET_NANOTIME(NANOTIME_T *) get current nanotime.
785 *
811 * GET_NANOSEC(NANOTIME_T *) get u_int64_t from NANOTIME_T
786 * GET_NANOSEC(NANOTIME_T *) get uint64_t from NANOTIME_T
812 *
813 * NANOTIME_SUB(NANOTIME_T *, NANOTIME_T *)
814 * subtract two NANOTIME_T values
815 *
816 *
787 *
788 * NANOTIME_SUB(NANOTIME_T *, NANOTIME_T *)
789 * subtract two NANOTIME_T values
790 *
791 *
817 * MAXISPREQUEST(struct ispsoftc *) maximum request queue size
792 * MAXISPREQUEST(ispsoftc_t *) maximum request queue size
818 * for this particular board type
819 *
793 * for this particular board type
794 *
820 * MEMORYBARRIER(struct ispsoftc *, barrier_type, offset, size)
795 * MEMORYBARRIER(ispsoftc_t *, barrier_type, offset, size)
821 *
822 * Function/Macro the provides memory synchronization on
823 * various objects so that the ISP's and the system's view
824 * of the same object is consistent.
825 *
796 *
797 * Function/Macro the provides memory synchronization on
798 * various objects so that the ISP's and the system's view
799 * of the same object is consistent.
800 *
826 * MBOX_ACQUIRE(struct ispsoftc *) acquire lock on mailbox regs
827 * MBOX_WAIT_COMPLETE(struct ispsoftc *) wait for mailbox cmd to be done
828 * MBOX_NOTIFY_COMPLETE(struct ispsoftc *) notification of mbox cmd donee
829 * MBOX_RELEASE(struct ispsoftc *) release lock on mailbox regs
801 * MBOX_ACQUIRE(ispsoftc_t *) acquire lock on mailbox regs
802 * MBOX_WAIT_COMPLETE(ispsoftc_t *) wait for mailbox cmd to be done
803 * MBOX_NOTIFY_COMPLETE(ispsoftc_t *) notification of mbox cmd donee
804 * MBOX_RELEASE(ispsoftc_t *) release lock on mailbox regs
830 *
805 *
831 * FC_SCRATCH_ACQUIRE(struct ispsoftc *) acquire lock on FC scratch area
832 * FC_SCRATCH_RELEASE(struct ispsoftc *) acquire lock on FC scratch area
806 * FC_SCRATCH_ACQUIRE(ispsoftc_t *) acquire lock on FC scratch area
807 * FC_SCRATCH_RELEASE(ispsoftc_t *) acquire lock on FC scratch area
833 *
834 * SCSI_GOOD SCSI 'Good' Status
835 * SCSI_CHECK SCSI 'Check Condition' Status
836 * SCSI_BUSY SCSI 'Busy' Status
837 * SCSI_QFULL SCSI 'Queue Full' Status
838 *
839 * XS_T Platform SCSI transaction type (i.e., command for HBA)
808 *
809 * SCSI_GOOD SCSI 'Good' Status
810 * SCSI_CHECK SCSI 'Check Condition' Status
811 * SCSI_BUSY SCSI 'Busy' Status
812 * SCSI_QFULL SCSI 'Queue Full' Status
813 *
814 * XS_T Platform SCSI transaction type (i.e., command for HBA)
815 * XS_DMA_ADDR_T Platform PCI DMA Address Type
840 * XS_ISP(xs) gets an instance out of an XS_T
841 * XS_CHANNEL(xs) gets the channel (bus # for DUALBUS cards) ""
842 * XS_TGT(xs) gets the target ""
843 * XS_LUN(xs) gets the lun ""
844 * XS_CDBP(xs) gets a pointer to the scsi CDB ""
845 * XS_CDBLEN(xs) gets the CDB's length ""
846 * XS_XFRLEN(xs) gets the associated data transfer length ""
847 * XS_TIME(xs) gets the time (in milliseconds) for this command

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869 * XS_INITERR(xs) initialize error state
870 *
871 * XS_SAVE_SENSE(xs, sp) save sense data
872 *
873 * XS_SET_STATE_STAT(isp, sp, xs) platform dependent interpreter of
874 * response queue entry status bits
875 *
876 *
816 * XS_ISP(xs) gets an instance out of an XS_T
817 * XS_CHANNEL(xs) gets the channel (bus # for DUALBUS cards) ""
818 * XS_TGT(xs) gets the target ""
819 * XS_LUN(xs) gets the lun ""
820 * XS_CDBP(xs) gets a pointer to the scsi CDB ""
821 * XS_CDBLEN(xs) gets the CDB's length ""
822 * XS_XFRLEN(xs) gets the associated data transfer length ""
823 * XS_TIME(xs) gets the time (in milliseconds) for this command

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845 * XS_INITERR(xs) initialize error state
846 *
847 * XS_SAVE_SENSE(xs, sp) save sense data
848 *
849 * XS_SET_STATE_STAT(isp, sp, xs) platform dependent interpreter of
850 * response queue entry status bits
851 *
852 *
877 * DEFAULT_IID(struct ispsoftc *) Default SCSI initiator ID
878 * DEFAULT_LOOPID(struct ispsoftc *) Default FC Loop ID
879 * DEFAULT_NODEWWN(struct ispsoftc *) Default Node WWN
880 * DEFAULT_PORTWWN(struct ispsoftc *) Default Port WWN
881 * DEFAULT_FRAMESIZE(struct ispsoftc *) Default Frame Size
882 * DEFAULT_EXEC_THROTTLE(struct ispsoftc *) Default Execution Throttle
853 * DEFAULT_IID(ispsoftc_t *) Default SCSI initiator ID
854 * DEFAULT_LOOPID(ispsoftc_t *) Default FC Loop ID
855 * DEFAULT_NODEWWN(ispsoftc_t *) Default Node WWN
856 * DEFAULT_PORTWWN(ispsoftc_t *) Default Port WWN
857 * DEFAULT_FRAMESIZE(ispsoftc_t *) Default Frame Size
858 * DEFAULT_EXEC_THROTTLE(ispsoftc_t *) Default Execution Throttle
883 * These establish reasonable defaults for each platform.
884 * These must be available independent of card NVRAM and are
885 * to be used should NVRAM not be readable.
886 *
859 * These establish reasonable defaults for each platform.
860 * These must be available independent of card NVRAM and are
861 * to be used should NVRAM not be readable.
862 *
887 * ISP_NODEWWN(struct ispsoftc *) FC Node WWN to use
888 * ISP_PORTWWN(struct ispsoftc *) FC Port WWN to use
863 * ISP_NODEWWN(ispsoftc_t *) FC Node WWN to use
864 * ISP_PORTWWN(ispsoftc_t *) FC Port WWN to use
889 *
890 * These are to be used after NVRAM is read. The tags
891 * in fcparam.isp_{node,port}wwn reflect the values
892 * read from NVRAM (possibly corrected for card botches).
893 * Each platform can take that information and override
894 * it or ignore and return the Node and Port WWNs to be
895 * used when sending the Qlogic f/w the Initialization Control
896 * Block.
897 *
898 * (XXX these do endian specific transformations- in transition XXX)
899 *
865 *
866 * These are to be used after NVRAM is read. The tags
867 * in fcparam.isp_{node,port}wwn reflect the values
868 * read from NVRAM (possibly corrected for card botches).
869 * Each platform can take that information and override
870 * it or ignore and return the Node and Port WWNs to be
871 * used when sending the Qlogic f/w the Initialization Control
872 * Block.
873 *
874 * (XXX these do endian specific transformations- in transition XXX)
875 *
900 * ISP_IOXPUT_8(struct ispsoftc *, u_int8_t srcval, u_int8_t *dstptr)
901 * ISP_IOXPUT_16(struct ispsoftc *, u_int16_t srcval, u_int16_t *dstptr)
902 * ISP_IOXPUT_32(struct ispsoftc *, u_int32_t srcval, u_int32_t *dstptr)
876 * ISP_IOXPUT_8(ispsoftc_t *, uint8_t srcval, uint8_t *dstptr)
877 * ISP_IOXPUT_16(ispsoftc_t *, uint16_t srcval, uint16_t *dstptr)
878 * ISP_IOXPUT_32(ispsoftc_t *, uint32_t srcval, uint32_t *dstptr)
903 *
879 *
904 * ISP_IOXGET_8(struct ispsoftc *, u_int8_t *srcptr, u_int8_t dstrval)
905 * ISP_IOXGET_16(struct ispsoftc *, u_int16_t *srcptr, u_int16_t dstrval)
906 * ISP_IOXGET_32(struct ispsoftc *, u_int32_t *srcptr, u_int32_t dstrval)
880 * ISP_IOXGET_8(ispsoftc_t *, uint8_t *srcptr, uint8_t dstrval)
881 * ISP_IOXGET_16(ispsoftc_t *, uint16_t *srcptr, uint16_t dstrval)
882 * ISP_IOXGET_32(ispsoftc_t *, uint32_t *srcptr, uint32_t dstrval)
907 *
883 *
908 * ISP_SWIZZLE_NVRAM_WORD(struct ispsoftc *, u_int16_t *)
884 * ISP_SWIZZLE_NVRAM_WORD(ispsoftc_t *, uint16_t *)
909 */
910
911#endif /* _ISPVAR_H */
885 */
886
887#endif /* _ISPVAR_H */