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ispmbox.h (35388) ispmbox.h (39235)
1/* $Id: ispmbox.h,v 1.3 1998/04/14 17:51:32 mjacob Exp $ */
1/* $Id: ispmbox.h,v 1.7 1998/09/14 23:23:26 mjacob Exp $ */
2/*
2/*
3 * Mailbox and Command Definitions for for Qlogic ISP SCSI adapters.
3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
4 *
5 *---------------------------------------
6 * Copyright (c) 1997, 1998 by Matthew Jacob
7 * NASA/Ames Research Center
8 * All rights reserved.
9 *---------------------------------------
10 *
11 * Redistribution and use in source and binary forms, with or without

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117#define MBOX_INIT_LIP 0x62
118#define MBOX_GET_FC_AL_POSITION_MAP 0x63
119#define MBOX_GET_PORT_DB 0x64
120#define MBOX_CLEAR_ACA 0x65
121#define MBOX_TARGET_RESET 0x66
122#define MBOX_CLEAR_TASK_SET 0x67
123#define MBOX_ABORT_TASK_SET 0x68
124#define MBOX_GET_FW_STATE 0x69
4 *
5 *---------------------------------------
6 * Copyright (c) 1997, 1998 by Matthew Jacob
7 * NASA/Ames Research Center
8 * All rights reserved.
9 *---------------------------------------
10 *
11 * Redistribution and use in source and binary forms, with or without

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117#define MBOX_INIT_LIP 0x62
118#define MBOX_GET_FC_AL_POSITION_MAP 0x63
119#define MBOX_GET_PORT_DB 0x64
120#define MBOX_CLEAR_ACA 0x65
121#define MBOX_TARGET_RESET 0x66
122#define MBOX_CLEAR_TASK_SET 0x67
123#define MBOX_ABORT_TASK_SET 0x68
124#define MBOX_GET_FW_STATE 0x69
125#define MBOX_GET_LINK_STATUS 0x6a
126#define MBOX_INIT_LIP_RESET 0x6c
127#define MBOX_INIT_LIP_LOGIN 0x72
125
126#define ISP2100_SET_PCI_PARAM 0x00ff
127
128#define MBOX_BUSY 0x04
129
130typedef struct {
131 u_int16_t param[8];
132} mbreg_t;
133
134/*
128
129#define ISP2100_SET_PCI_PARAM 0x00ff
130
131#define MBOX_BUSY 0x04
132
133typedef struct {
134 u_int16_t param[8];
135} mbreg_t;
136
137/*
138 * Mailbox Command Complete Status Codes
139 */
140#define MBOX_COMMAND_COMPLETE 0x4000
141#define MBOX_INVALID_COMMAND 0x4001
142#define MBOX_HOST_INTERFACE_ERROR 0x4002
143#define MBOX_TEST_FAILED 0x4003
144#define MBOX_COMMAND_ERROR 0x4005
145#define MBOX_COMMAND_PARAM_ERROR 0x4006
146
147/*
148 * Asynchronous event status codes
149 */
150#define ASYNC_BUS_RESET 0x8001
151#define ASYNC_SYSTEM_ERROR 0x8002
152#define ASYNC_RQS_XFER_ERR 0x8003
153#define ASYNC_RSP_XFER_ERR 0x8004
154#define ASYNC_QWAKEUP 0x8005
155#define ASYNC_TIMEOUT_RESET 0x8006
156#define ASYNC_UNSPEC_TMODE 0x8007
157#define ASYNC_EXTMSG_UNDERRUN 0x800A
158#define ASYNC_SCAM_INT 0x800B
159#define ASYNC_HUNG_SCSI 0x800C
160#define ASYNC_KILLED_BUS 0x800D
161#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */
162#define ASYNC_CMD_CMPLT 0x8020
163#define ASYNC_CTIO_DONE 0x8021
164
165/* for ISP2100 only */
166#define ASYNC_LIP_OCCURRED 0x8010
167#define ASYNC_LOOP_UP 0x8011
168#define ASYNC_LOOP_DOWN 0x8012
169#define ASYNC_LOOP_RESET 0x8013
170#define ASYNC_PDB_CHANGED 0x8014 /* Port Database Changed */
171#define ASYNC_CHANGE_NOTIFY 0x8015
172
173/*
135 * Command Structure Definitions
136 */
137
138typedef struct {
139 u_int32_t ds_base;
140 u_int32_t ds_count;
141} ispds_t;
142

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156
157/* RQS Flag definitions */
158#define RQSFLAG_CONTINUATION 0x01
159#define RQSFLAG_FULL 0x02
160#define RQSFLAG_BADHEADER 0x04
161#define RQSFLAG_BADPACKET 0x08
162
163/* RQS entry_type definitions */
174 * Command Structure Definitions
175 */
176
177typedef struct {
178 u_int32_t ds_base;
179 u_int32_t ds_count;
180} ispds_t;
181

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195
196/* RQS Flag definitions */
197#define RQSFLAG_CONTINUATION 0x01
198#define RQSFLAG_FULL 0x02
199#define RQSFLAG_BADHEADER 0x04
200#define RQSFLAG_BADPACKET 0x08
201
202/* RQS entry_type definitions */
164#define RQSTYPE_REQUEST 1
165#define RQSTYPE_DATASEG 2
166#define RQSTYPE_RESPONSE 3
167#define RQSTYPE_MARKER 4
168#define RQSTYPE_CMDONLY 5
169#define RQSTYPE_T2RQS 17
170#define RQSTYPE_T3RQS 25
171#define RQSTYPE_T1DSEG 10
203#define RQSTYPE_REQUEST 0x01
204#define RQSTYPE_DATASEG 0x02
205#define RQSTYPE_RESPONSE 0x03
206#define RQSTYPE_MARKER 0x04
207#define RQSTYPE_CMDONLY 0x05
208#define RQSTYPE_ATIO 0x06 /* Target Mode */
209#define RQSTYPE_CTIO0 0x07 /* Target Mode */
210#define RQSTYPE_SCAM 0x08
211#define RQSTYPE_A64 0x09
212#define RQSTYPE_A64_CONT 0x0a
213#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */
214#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */
215#define RQSTYPE_NOTIFY 0x0d /* Target Mode */
216#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */
217#define RQSTYPE_CTIO1 0x0f /* Target Mode */
218#define RQSTYPE_STATUS_CONT 0x10
219#define RQSTYPE_T2RQS 0x11
172
220
221#define RQSTYPE_T4RQS 0x15
222#define RQSTYPE_ATIO2 0x16
223#define RQSTYPE_CTIO2 0x17
224#define RQSTYPE_CSET0 0x18
225#define RQSTYPE_T3RQS 0x19
173
226
227#define RQSTYPE_CTIO3 0x1f
228
229
174#define ISP_RQDSEG 4
175typedef struct {
176 isphdr_t req_header;
177 u_int32_t req_handle;
178#if BYTE_ORDER == BIG_ENDIAN
179 u_int8_t req_target;
180 u_int8_t req_lun_trn;
181#else

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221#define REQFLAG_TARGET_RTN 0x0010
222
223#define REQFLAG_NODATA 0x0000
224#define REQFLAG_DATA_IN 0x0020
225#define REQFLAG_DATA_OUT 0x0040
226#define REQFLAG_DATA_UNKNOWN 0x0060
227
228#define REQFLAG_DISARQ 0x0100
230#define ISP_RQDSEG 4
231typedef struct {
232 isphdr_t req_header;
233 u_int32_t req_handle;
234#if BYTE_ORDER == BIG_ENDIAN
235 u_int8_t req_target;
236 u_int8_t req_lun_trn;
237#else

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277#define REQFLAG_TARGET_RTN 0x0010
278
279#define REQFLAG_NODATA 0x0000
280#define REQFLAG_DATA_IN 0x0020
281#define REQFLAG_DATA_OUT 0x0040
282#define REQFLAG_DATA_UNKNOWN 0x0060
283
284#define REQFLAG_DISARQ 0x0100
285#define REQFLAG_FRC_ASYNC 0x0200
286#define REQFLAG_FRC_SYNC 0x0400
287#define REQFLAG_FRC_WIDE 0x0800
288#define REQFLAG_NOPARITY 0x1000
289#define REQFLAG_STOPQ 0x2000
290#define REQFLAG_XTRASNS 0x4000
291#define REQFLAG_PRIORITY 0x8000
229
230typedef struct {
231 isphdr_t req_header;
232 u_int32_t req_handle;
233#if BYTE_ORDER == BIG_ENDIAN
234 u_int8_t req_target;
235 u_int8_t req_lun_trn;
236#else

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315#define RQCS_ABORT_MSG_FAILED 0x000e
316#define RQCS_REJECT_MSG_FAILED 0x000f
317#define RQCS_NOP_MSG_FAILED 0x0010
318#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
319#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
320#define RQCS_ID_MSG_FAILED 0x0013
321#define RQCS_UNEXP_BUS_FREE 0x0014
322#define RQCS_DATA_UNDERRUN 0x0015
292
293typedef struct {
294 isphdr_t req_header;
295 u_int32_t req_handle;
296#if BYTE_ORDER == BIG_ENDIAN
297 u_int8_t req_target;
298 u_int8_t req_lun_trn;
299#else

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378#define RQCS_ABORT_MSG_FAILED 0x000e
379#define RQCS_REJECT_MSG_FAILED 0x000f
380#define RQCS_NOP_MSG_FAILED 0x0010
381#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
382#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
383#define RQCS_ID_MSG_FAILED 0x0013
384#define RQCS_UNEXP_BUS_FREE 0x0014
385#define RQCS_DATA_UNDERRUN 0x0015
386#define RQCS_XACT_ERR1 0x0018
387#define RQCS_XACT_ERR2 0x0019
388#define RQCS_XACT_ERR3 0x001A
389#define RQCS_BAD_ENTRY 0x001B
390#define RQCS_QUEUE_FULL 0x001C
391#define RQCS_PHASE_SKIPPED 0x001D
392#define RQCS_ARQS_FAILED 0x001E
393#define RQCS_WIDE_FAILED 0x001F
394#define RQCS_SYNCXFER_FAILED 0x0020
395#define RQCS_LVD_BUSERR 0x0021
396
323/* 2100 Only Completion Codes */
324#define RQCS_PORT_UNAVAILABLE 0x0028
325#define RQCS_PORT_LOGGED_OUT 0x0029
326#define RQCS_PORT_CHANGED 0x002A
327#define RQCS_PORT_BUSY 0x002B
328
329/*
330 * State Flags (not applicable to 2100)

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345#define RQSTF_PARITY_ERROR 0x0004
346#define RQSTF_BUS_RESET 0x0008
347#define RQSTF_DEVICE_RESET 0x0010
348#define RQSTF_ABORTED 0x0020
349#define RQSTF_TIMEOUT 0x0040
350#define RQSTF_NEGOTIATION 0x0080
351
352/*
397/* 2100 Only Completion Codes */
398#define RQCS_PORT_UNAVAILABLE 0x0028
399#define RQCS_PORT_LOGGED_OUT 0x0029
400#define RQCS_PORT_CHANGED 0x002A
401#define RQCS_PORT_BUSY 0x002B
402
403/*
404 * State Flags (not applicable to 2100)

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419#define RQSTF_PARITY_ERROR 0x0004
420#define RQSTF_BUS_RESET 0x0008
421#define RQSTF_DEVICE_RESET 0x0010
422#define RQSTF_ABORTED 0x0020
423#define RQSTF_TIMEOUT 0x0040
424#define RQSTF_NEGOTIATION 0x0080
425
426/*
427 * Target Mode Structures
428 */
429/*
430 * Used for Enable LUN and Modify Lun types.
431 * (for FC, pre-1.14 FW layout revision).
432 */
433typedef struct {
434 isphdr_t req_header;
435 u_int32_t req_handle;
436#if BYTE_ORDER == BIG_ENDIAN
437 u_int8_t _reserved0;
438 u_int8_t req_lun; /* HOST->FW: LUN to enable */
439#else
440 u_int8_t req_lun; /* HOST->FW: LUN to enable */
441 u_int8_t _reserved0;
442#endif
443 u_int16_t _reserved1[3];
444#if BYTE_ORDER == BIG_ENDIAN
445 u_int8_t _reserved2;
446 u_int8_t req_status; /* FW->HOST: Status of Request */
447 u_int8_t req_imcount; /* HOST->FW: Immediate Notify Count */
448 u_int8_t req_cmdcount; /* HOST->FW: ATIO Count */
449#else
450 u_int8_t req_status; /* FW->HOST: Status of Request */
451 u_int8_t _reserved2;
452 u_int8_t req_cmdcount; /* HOST->FW: ATIO Count */
453 u_int8_t req_imcount; /* HOST->FW: Immediate Notify Count */
454#endif
455 u_int16_t _reserved3;
456 u_int16_t req_timeout; /* HOST->FW: Lun timeout value */
457} isplun_t;
458/* inbound status */
459#define LUN_OKAY 0x01
460#define LUN_ERR 0x04
461#define LUN_NOCAP 0x16
462#define LUN_ENABLED 0x3e
463/* outbound flags */
464#define LUN_INCR_CMD 0x0001
465#define LUN_DECR_CMD 0x0002
466#define LUN_INCR_IMMED 0x0100
467#define LUN_DECR_IMMED 0x0200
468
469typedef struct {
470 isphdr_t req_header;
471 u_int32_t req_handle;
472#if BYTE_ORDER == BIG_ENDIAN
473 u_int8_t req_initiator;
474 u_int8_t req_lun;
475#else
476 u_int8_t req_lun;
477 u_int8_t req_initiator;
478#endif
479 u_int16_t req_flags; /* NOTIFY_ACK only */
480 u_int16_t _reserved1[2];
481 u_int16_t req_status;
482 u_int16_t req_task_flags;
483 u_int16_t req_sequence;
484} ispnotify_t;
485
486#define IN_NOCAP 0x16
487#define IN_IDE_RECEIVED 0x33
488#define IN_RSRC_UNAVAIL 0x34
489#define IN_MSG_RECEIVED 0x36
490
491typedef struct {
492 isphdr_t req_header;
493 u_int32_t req_handle;
494#if BYTE_ORDER == BIG_ENDIAN
495 u_int8_t req_initiator;
496 u_int8_t req_lun;
497#else
498 u_int8_t req_lun;
499 u_int8_t req_initiator;
500#endif
501 u_int16_t req_rxid;
502 u_int16_t req_flags;
503 u_int16_t req_status;
504#if BYTE_ORDER == BIG_ENDIAN
505 u_int8_t req_taskcodes;
506 u_int8_t _reserved0;
507 u_int8_t req_execodes;
508 u_int8_t req_taskflags;
509#else
510 u_int8_t _reserved0;
511 u_int8_t req_taskcodes;
512 u_int8_t req_taskflags;
513 u_int8_t req_execodes;
514#endif
515 u_int8_t req_cdb[16];
516 u_int32_t req_datalen;
517 u_int16_t req_scclun;
518 u_int16_t _reserved1;;
519 u_int16_t req_scsi_status;
520 u_int8_t req_sense[18];
521} ispatiot2_t;
522
523#define ATIO_PATH_INVALID 0x07
524#define ATIO_PHASE_ERROR 0x14
525#define ATIO_NOCAP 0x16
526#define ATIO_BDR_MSG 0x17
527#define ATIO_CDB_RECEIVED 0x3d
528
529#define ATIO_SENSEVALID 0x80
530
531/*
532 * Continue Target I/O, type 2
533 */
534typedef struct {
535 isphdr_t req_header;
536 u_int32_t req_handle;
537#if BYTE_ORDER == BIG_ENDIAN
538 u_int8_t req_initiator;
539 u_int8_t req_lun;
540#else
541 u_int8_t req_lun;
542 u_int8_t req_initiator;
543#endif
544 u_int16_t req_rxid;
545 u_int16_t req_flags;
546 u_int16_t req_status;
547 u_int16_t req_timeout;
548 u_int16_t req_seg_count; /* data segment count */
549 u_int8_t req_reloff[4]; /* relative offset */
550 u_int8_t req_resid[4]; /* residual */
551 u_int8_t _reserved0[4];
552 union { /* should be offset 0x20 */
553 struct {
554 u_int16_t _reserved0;
555 u_int16_t req_scsi_status;
556 u_int32_t req_datalen;
557 ispds_t req_dataseg[ISP_RQDSEG_T2];
558 } mode0;
559 struct {
560 u_int16_t req_sense_len;
561 u_int16_t req_scsi_status;
562 u_int32_t req_response_length;
563 u_int8_t req_response[26];
564 } mode1;
565 struct {
566 u_int16_t _reserved0[2];
567 u_int32_t req_datalen;
568 ispds_t req_fcpiudata;
569 } mode2;
570 } req_m;
571} ispctiot2_t;
572
573#define CTIO_SEND_STATUS 0x8000
574#define CTIO_SEND_DATA 0x0040 /* To initiator */
575#define CTIO_RECV_DATA 0x0080
576#define CTIO_NODATA 0x00C0
577
578#define CTIO2_SMODE0 0x0000
579#define CTIO2_SMODE1 0x0001
580#define CTIO2_SMODE2 0x0002
581
582#define CTIO2_RESP_VALID 0x0100
583#define CTIO2_STATUS_VALID 0x0200
584#define CTIO2_RSPOVERUN 0x0400
585#define CTIO2_RSPUNDERUN 0x0800
586
587
588/*
353 * FC (ISP2100) specific data structures
354 */
355
356/*
357 * Initialization Control Block
589 * FC (ISP2100) specific data structures
590 */
591
592/*
593 * Initialization Control Block
594 *
595 * Version One format.
358 */
359typedef struct {
360#if BYTE_ORDER == BIG_ENDIAN
361 u_int8_t _reserved0;
362 u_int8_t icb_version;
363#else
364 u_int8_t icb_version;
365 u_int8_t _reserved0;

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370 u_int16_t icb_execthrottle;
371#if BYTE_ORDER == BIG_ENDIAN
372 u_int8_t icb_retry_delay;
373 u_int8_t icb_retry_count;
374#else
375 u_int8_t icb_retry_count;
376 u_int8_t icb_retry_delay;
377#endif
596 */
597typedef struct {
598#if BYTE_ORDER == BIG_ENDIAN
599 u_int8_t _reserved0;
600 u_int8_t icb_version;
601#else
602 u_int8_t icb_version;
603 u_int8_t _reserved0;

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608 u_int16_t icb_execthrottle;
609#if BYTE_ORDER == BIG_ENDIAN
610 u_int8_t icb_retry_delay;
611 u_int8_t icb_retry_count;
612#else
613 u_int8_t icb_retry_count;
614 u_int8_t icb_retry_delay;
615#endif
378 u_int16_t icb_nodename[4];
616 u_int8_t icb_nodename[8];
379 u_int16_t icb_hardaddr;
617 u_int16_t icb_hardaddr;
380 u_int16_t _reserved1[5];
618#if BYTE_ORDER == BIG_ENDIAN
619 u_int8_t _reserved1;
620 u_int8_t icb_iqdevtype;
621#else
622 u_int8_t icb_iqdevtype;
623 u_int8_t _reserved1;
624#endif
625 u_int8_t icb_portname[8];
381 u_int16_t icb_rqstout;
382 u_int16_t icb_rspnsin;
383 u_int16_t icb_rqstqlen;
384 u_int16_t icb_rsltqlen;
385 u_int16_t icb_rqstaddr[4];
386 u_int16_t icb_respaddr[4];
387} isp_icb_t;
626 u_int16_t icb_rqstout;
627 u_int16_t icb_rspnsin;
628 u_int16_t icb_rqstqlen;
629 u_int16_t icb_rsltqlen;
630 u_int16_t icb_rqstaddr[4];
631 u_int16_t icb_respaddr[4];
632} isp_icb_t;
633#define ICB_VERSION1 1
388
634
389#define ICB_DFLT_FRMLEN 1024
390#define MAKE_NODE_NAME(isp, icbp) \
391 (icbp)->icb_nodename[0] = 0, (icbp)->icb_nodename[1] = 0x5355,\
392 (icbp)->icb_nodename[2] = 0x4E57, (icbp)->icb_nodename[3] = 0
635#define ICBOPT_HARD_ADDRESS (1<<0)
636#define ICBOPT_FAIRNESS (1<<1)
637#define ICBOPT_FULL_DUPLEX (1<<2)
638#define ICBOPT_FAST_POST (1<<3)
639#define ICBOPT_TGT_ENABLE (1<<4)
640#define ICBOPT_INI_DISABLE (1<<5)
641#define ICBOPT_INI_ADISC (1<<6)
642#define ICBOPT_INI_TGTTYPE (1<<7)
643#define ICBOPT_PDBCHANGE_AE (1<<8)
644#define ICBOPT_NOLIP (1<<9)
645#define ICBOPT_SRCHDOWN (1<<10)
646#define ICBOPT_PREVLOOP (1<<11)
647#define ICBOPT_STOP_ON_QFULL (1<<12)
648#define ICBOPT_FULL_LOGIN (1<<13)
649#define ICBOPT_USE_PORTNAME (1<<14)
393
650
651
652#define ICB_MIN_FRMLEN 256
653#define ICB_MAX_FRMLEN 2112
654#define ICB_DFLT_FRMLEN 1024
655
656#define RQRSP_ADDR0015 0
657#define RQRSP_ADDR1631 1
658#define RQRSP_ADDR3247 2
659#define RQRSP_ADDR4863 3
660
661
662#if BYTE_ORDER == BIG_ENDIAN
663#define ICB_NNM0 6
664#define ICB_NNM1 7
665#define ICB_NNM2 4
666#define ICB_NNM3 5
667#define ICB_NNM4 2
668#define ICB_NNM5 3
669#define ICB_NNM6 0
670#define ICB_NNM7 1
671#else
672#define ICB_NNM0 7
673#define ICB_NNM1 6
674#define ICB_NNM2 5
675#define ICB_NNM3 4
676#define ICB_NNM4 3
677#define ICB_NNM5 2
678#define ICB_NNM6 1
679#define ICB_NNM7 0
680#endif
681
682#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \
683 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \
684 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \
685 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \
686 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \
687 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \
688 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \
689 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \
690 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff)
691
394#endif /* _ISPMBOX_H */
692#endif /* _ISPMBOX_H */