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sdiff udiff text old ( 161932 ) new ( 163899 )
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isp_pci.c (161932) isp_pci.c (163899)
1/*-
2 *
3 * Copyright (c) 1997-2006 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 16 unchanged lines hidden (view full) ---

25 * SUCH DAMAGE.
26 *
27 */
28/*
29 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
30 * FreeBSD Version.
31 */
32#include <sys/cdefs.h>
1/*-
2 *
3 * Copyright (c) 1997-2006 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 16 unchanged lines hidden (view full) ---

25 * SUCH DAMAGE.
26 *
27 */
28/*
29 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
30 * FreeBSD Version.
31 */
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/dev/isp/isp_pci.c 161932 2006-09-03 01:26:55Z mjacob $");
33__FBSDID("$FreeBSD: head/sys/dev/isp/isp_pci.c 163899 2006-11-02 03:21:32Z mjacob $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#if __FreeBSD_version >= 700000
40#include <sys/linker.h>
41#include <sys/firmware.h>

--- 15 unchanged lines hidden (view full) ---

57#include <sys/malloc.h>
58
59#include <dev/isp/isp_freebsd.h>
60
61#if __FreeBSD_version < 500000
62#define BUS_PROBE_DEFAULT 0
63#endif
64
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#if __FreeBSD_version >= 700000
40#include <sys/linker.h>
41#include <sys/firmware.h>

--- 15 unchanged lines hidden (view full) ---

57#include <sys/malloc.h>
58
59#include <dev/isp/isp_freebsd.h>
60
61#if __FreeBSD_version < 500000
62#define BUS_PROBE_DEFAULT 0
63#endif
64
65static uint16_t isp_pci_rd_reg(ispsoftc_t *, int);
66static void isp_pci_wr_reg(ispsoftc_t *, int, uint16_t);
67static uint16_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
68static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint16_t);
65static uint32_t isp_pci_rd_reg(ispsoftc_t *, int);
66static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t);
67static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
68static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t);
69static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int);
70static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t);
69static int
71static int
70isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
72isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *);
71static int
73static int
72isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
74isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *);
75static int
76isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *);
73static int isp_pci_mbxdma(ispsoftc_t *);
74static int
77static int isp_pci_mbxdma(ispsoftc_t *);
78static int
75isp_pci_dmasetup(ispsoftc_t *, XS_T *, ispreq_t *, uint16_t *, uint16_t);
79isp_pci_dmasetup(ispsoftc_t *, XS_T *, ispreq_t *, uint32_t *, uint32_t);
76static void
80static void
77isp_pci_dmateardown(ispsoftc_t *, XS_T *, uint16_t);
81isp_pci_dmateardown(ispsoftc_t *, XS_T *, uint32_t);
78
79
80static void isp_pci_reset1(ispsoftc_t *);
81static void isp_pci_dumpregs(ispsoftc_t *, const char *);
82
83static struct ispmdvec mdvec = {
84 isp_pci_rd_isr,
85 isp_pci_rd_reg,

--- 67 unchanged lines hidden (view full) ---

153 isp_pci_mbxdma,
154 isp_pci_dmasetup,
155 isp_pci_dmateardown,
156 NULL,
157 isp_pci_reset1,
158 isp_pci_dumpregs
159};
160
82
83
84static void isp_pci_reset1(ispsoftc_t *);
85static void isp_pci_dumpregs(ispsoftc_t *, const char *);
86
87static struct ispmdvec mdvec = {
88 isp_pci_rd_isr,
89 isp_pci_rd_reg,

--- 67 unchanged lines hidden (view full) ---

157 isp_pci_mbxdma,
158 isp_pci_dmasetup,
159 isp_pci_dmateardown,
160 NULL,
161 isp_pci_reset1,
162 isp_pci_dumpregs
163};
164
165static struct ispmdvec mdvec_2400 = {
166 isp_pci_rd_isr_2400,
167 isp_pci_rd_reg_2400,
168 isp_pci_wr_reg_2400,
169 isp_pci_mbxdma,
170 isp_pci_dmasetup,
171 isp_pci_dmateardown,
172 NULL,
173 isp_pci_reset1,
174 NULL
175};
176
161#ifndef PCIM_CMD_INVEN
162#define PCIM_CMD_INVEN 0x10
163#endif
164#ifndef PCIM_CMD_BUSMASTEREN
165#define PCIM_CMD_BUSMASTEREN 0x0004
166#endif
167#ifndef PCIM_CMD_PERRESPEN
168#define PCIM_CMD_PERRESPEN 0x0040

--- 132 unchanged lines hidden (view full) ---

301#define IO_MAP_REG 0x10
302#define MEM_MAP_REG 0x14
303
304#define PCI_DFLT_LTNCY 0x40
305#define PCI_DFLT_LNSZ 0x10
306
307static int isp_pci_probe (device_t);
308static int isp_pci_attach (device_t);
177#ifndef PCIM_CMD_INVEN
178#define PCIM_CMD_INVEN 0x10
179#endif
180#ifndef PCIM_CMD_BUSMASTEREN
181#define PCIM_CMD_BUSMASTEREN 0x0004
182#endif
183#ifndef PCIM_CMD_PERRESPEN
184#define PCIM_CMD_PERRESPEN 0x0040

--- 132 unchanged lines hidden (view full) ---

317#define IO_MAP_REG 0x10
318#define MEM_MAP_REG 0x14
319
320#define PCI_DFLT_LTNCY 0x40
321#define PCI_DFLT_LNSZ 0x10
322
323static int isp_pci_probe (device_t);
324static int isp_pci_attach (device_t);
325static int isp_pci_detach (device_t);
309
310
311struct isp_pcisoftc {
312 ispsoftc_t pci_isp;
313 device_t pci_dev;
314 struct resource * pci_reg;
315 bus_space_tag_t pci_st;
316 bus_space_handle_t pci_sh;
317 void * ih;
318 int16_t pci_poff[_NREG_BLKS];
319 bus_dma_tag_t dmat;
320 bus_dmamap_t *dmaps;
321};
322
326
327
328struct isp_pcisoftc {
329 ispsoftc_t pci_isp;
330 device_t pci_dev;
331 struct resource * pci_reg;
332 bus_space_tag_t pci_st;
333 bus_space_handle_t pci_sh;
334 void * ih;
335 int16_t pci_poff[_NREG_BLKS];
336 bus_dma_tag_t dmat;
337 bus_dmamap_t *dmaps;
338};
339
340
323static device_method_t isp_pci_methods[] = {
324 /* Device interface */
325 DEVMETHOD(device_probe, isp_pci_probe),
326 DEVMETHOD(device_attach, isp_pci_attach),
341static device_method_t isp_pci_methods[] = {
342 /* Device interface */
343 DEVMETHOD(device_probe, isp_pci_probe),
344 DEVMETHOD(device_attach, isp_pci_attach),
345 DEVMETHOD(device_detach, isp_pci_detach),
327 { 0, 0 }
328};
329static void isp_pci_intr(void *);
330
331static driver_t isp_pci_driver = {
332 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc)
333};
334static devclass_t isp_devclass;

--- 40 unchanged lines hidden (view full) ---

375 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter");
376 break;
377 case PCI_QLOGIC_ISP2312:
378 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter");
379 break;
380 case PCI_QLOGIC_ISP2322:
381 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter");
382 break;
346 { 0, 0 }
347};
348static void isp_pci_intr(void *);
349
350static driver_t isp_pci_driver = {
351 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc)
352};
353static devclass_t isp_devclass;

--- 40 unchanged lines hidden (view full) ---

394 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter");
395 break;
396 case PCI_QLOGIC_ISP2312:
397 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter");
398 break;
399 case PCI_QLOGIC_ISP2322:
400 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter");
401 break;
383#if 0
384 case PCI_QLOGIC_ISP2422:
385 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter");
386 break;
402 case PCI_QLOGIC_ISP2422:
403 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter");
404 break;
387#endif
388 case PCI_QLOGIC_ISP6312:
389 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter");
390 break;
391 case PCI_QLOGIC_ISP6322:
392 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter");
393 break;
394 default:
395 return (ENXIO);

--- 86 unchanged lines hidden (view full) ---

482 isp->isp_dblev = bitmap;
483 } else {
484 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
485 }
486 if (bootverbose) {
487 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
488 }
489
405 case PCI_QLOGIC_ISP6312:
406 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter");
407 break;
408 case PCI_QLOGIC_ISP6322:
409 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter");
410 break;
411 default:
412 return (ENXIO);

--- 86 unchanged lines hidden (view full) ---

499 isp->isp_dblev = bitmap;
500 } else {
501 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
502 }
503 if (bootverbose) {
504 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
505 }
506
507 bitmap = 0;
508 (void) getenv_int("isp_fabric_hysteresis", &bitmap);
509 if (bitmap >= 0 && bitmap < 256) {
510 isp->isp_osinfo.hysteresis = bitmap;
511 } else {
512 isp->isp_osinfo.hysteresis = isp_fabric_hysteresis;
513 }
514
515 bitmap = 0;
516 (void) getenv_int("isp_loop_down_limit", &bitmap);
517 if (bitmap >= 0 && bitmap < 0xffff) {
518 isp->isp_osinfo.loop_down_limit = bitmap;
519 } else {
520 isp->isp_osinfo.loop_down_limit = isp_loop_down_limit;
521 }
522
523
490#ifdef ISP_FW_CRASH_DUMP
491 bitmap = 0;
492 if (getenv_int("isp_fw_dump_enable", &bitmap)) {
493 if (bitmap & (1 << unit) {
494 size_t amt = 0;
495 if (IS_2200(isp)) {
496 amt = QLA2200_RISC_IMAGE_DUMP_SIZE;
497 } else if (IS_23XX(isp)) {

--- 187 unchanged lines hidden (view full) ---

685 isp->isp_dblev = tval;
686 } else {
687 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
688 }
689 if (bootverbose) {
690 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
691 }
692
524#ifdef ISP_FW_CRASH_DUMP
525 bitmap = 0;
526 if (getenv_int("isp_fw_dump_enable", &bitmap)) {
527 if (bitmap & (1 << unit) {
528 size_t amt = 0;
529 if (IS_2200(isp)) {
530 amt = QLA2200_RISC_IMAGE_DUMP_SIZE;
531 } else if (IS_23XX(isp)) {

--- 187 unchanged lines hidden (view full) ---

719 isp->isp_dblev = tval;
720 } else {
721 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
722 }
723 if (bootverbose) {
724 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
725 }
726
727 tval = 0;
728 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
729 "hysteresis", &tval);
730 if (tval >= 0 && tval < 256) {
731 isp->isp_osinfo.hysteresis = tval;
732 } else {
733 isp->isp_osinfo.hysteresis = isp_fabric_hysteresis;
734 }
735
736 tval = 0;
737 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
738 "loop_down_limit", &tval);
739 if (tval >= 0 && tval < 0xffff) {
740 isp->isp_osinfo.loop_down_limit = tval;
741 } else {
742 isp->isp_osinfo.loop_down_limit = isp_loop_down_limit;
743 }
744
693}
694
695static void
696isp_get_pci_options(device_t dev, int *m1, int *m2)
697{
698 int tval;
699 /*
700 * Which we should try first - memory mapping or i/o mapping?

--- 180 unchanged lines hidden (view full) ---

881 pci_get_devid(dev) == PCI_QLOGIC_ISP6322) {
882 mdvp = &mdvec_2300;
883 basetype = ISP_HA_FC_2322;
884 psize = sizeof (fcparam);
885 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
886 PCI_MBOX_REGS2300_OFF;
887 }
888 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2422) {
745}
746
747static void
748isp_get_pci_options(device_t dev, int *m1, int *m2)
749{
750 int tval;
751 /*
752 * Which we should try first - memory mapping or i/o mapping?

--- 180 unchanged lines hidden (view full) ---

933 pci_get_devid(dev) == PCI_QLOGIC_ISP6322) {
934 mdvp = &mdvec_2300;
935 basetype = ISP_HA_FC_2322;
936 psize = sizeof (fcparam);
937 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
938 PCI_MBOX_REGS2300_OFF;
939 }
940 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2422) {
889 mdvp = &mdvec_2300;
890 basetype = ISP_HA_FC_2422;
941 mdvp = &mdvec_2400;
942 basetype = ISP_HA_FC_2400;
891 psize = sizeof (fcparam);
892 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
943 psize = sizeof (fcparam);
944 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
893 PCI_MBOX_REGS2300_OFF;
945 PCI_MBOX_REGS2400_OFF;
894 }
895 isp = &pcs->pci_isp;
896 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO);
897 if (isp->isp_param == NULL) {
898 device_printf(dev, "cannot allocate parameter data\n");
899 goto bad;
900 }
901 isp->isp_mdvec = mdvp;

--- 25 unchanged lines hidden (view full) ---

927 break;
928 case PCI_PRODUCT_QLOGIC_ISP6312:
929 case PCI_PRODUCT_QLOGIC_ISP2312:
930 did = 0x2300;
931 break;
932 case PCI_PRODUCT_QLOGIC_ISP6322:
933 did = 0x2322;
934 break;
946 }
947 isp = &pcs->pci_isp;
948 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO);
949 if (isp->isp_param == NULL) {
950 device_printf(dev, "cannot allocate parameter data\n");
951 goto bad;
952 }
953 isp->isp_mdvec = mdvp;

--- 25 unchanged lines hidden (view full) ---

979 break;
980 case PCI_PRODUCT_QLOGIC_ISP6312:
981 case PCI_PRODUCT_QLOGIC_ISP2312:
982 did = 0x2300;
983 break;
984 case PCI_PRODUCT_QLOGIC_ISP6322:
985 did = 0x2322;
986 break;
987 case PCI_PRODUCT_QLOGIC_ISP2422:
988 did = 0x2400;
989 break;
935 default:
936 break;
937 }
938
939 isp->isp_osinfo.fw = NULL;
940 if (isp->isp_role & ISP_ROLE_TARGET) {
941 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did);
942 isp->isp_osinfo.fw = firmware_get(fwname);

--- 28 unchanged lines hidden (view full) ---

971 */
972 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN |
973 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
974
975 if (IS_2300(isp)) { /* per QLogic errata */
976 cmd &= ~PCIM_CMD_INVEN;
977 }
978
990 default:
991 break;
992 }
993
994 isp->isp_osinfo.fw = NULL;
995 if (isp->isp_role & ISP_ROLE_TARGET) {
996 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did);
997 isp->isp_osinfo.fw = firmware_get(fwname);

--- 28 unchanged lines hidden (view full) ---

1026 */
1027 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN |
1028 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
1029
1030 if (IS_2300(isp)) { /* per QLogic errata */
1031 cmd &= ~PCIM_CMD_INVEN;
1032 }
1033
979 if (IS_23XX(isp)) {
980 /*
981 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command.
982 */
983 isp->isp_touched = 1;
984
1034 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
1035 cmd &= ~PCIM_CMD_INTX_DISABLE;
985 }
986
1036 }
1037
987 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
1038 if (IS_24XX(isp)) {
1039 int reg;
1040
988 cmd &= ~PCIM_CMD_INTX_DISABLE;
1041 cmd &= ~PCIM_CMD_INTX_DISABLE;
1042
1043 /*
1044 * Is this a PCI-X card? If so, set max read byte count.
1045 */
1046 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
1047 uint16_t pxcmd;
1048 reg += 2;
1049
1050 pxcmd = pci_read_config(dev, reg, 2);
1051 pxcmd &= ~0xc;
1052 pxcmd |= 0x8;
1053 pci_write_config(dev, reg, 2, pxcmd);
1054 }
1055
1056 /*
1057 * Is this a PCI Express card? If so, set max read byte count.
1058 */
1059 if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
1060 uint16_t pectl;
1061
1062 reg += 0x8;
1063 pectl = pci_read_config(dev, reg, 2);
1064 pectl &= ~0x7000;
1065 pectl |= 0x4000;
1066 pci_write_config(dev, reg, 2, pectl);
1067 }
989 }
990
991 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
992
993 /*
994 * Make sure the Cache Line Size register is set sensibly.
995 */
996 data = pci_read_config(dev, PCIR_CACHELNSZ, 1);

--- 37 unchanged lines hidden (view full) ---

1034 if (bus_setup_intr(dev, irq, ISP_IFLAGS, isp_pci_intr, isp, &pcs->ih)) {
1035 device_printf(dev, "could not setup interrupt\n");
1036 goto bad;
1037 }
1038
1039 /*
1040 * Last minute checks...
1041 */
1068 }
1069
1070 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
1071
1072 /*
1073 * Make sure the Cache Line Size register is set sensibly.
1074 */
1075 data = pci_read_config(dev, PCIR_CACHELNSZ, 1);

--- 37 unchanged lines hidden (view full) ---

1113 if (bus_setup_intr(dev, irq, ISP_IFLAGS, isp_pci_intr, isp, &pcs->ih)) {
1114 device_printf(dev, "could not setup interrupt\n");
1115 goto bad;
1116 }
1117
1118 /*
1119 * Last minute checks...
1120 */
1042 if (IS_23XX(isp)) {
1121 if (IS_23XX(isp) || IS_24XX(isp)) {
1043 isp->isp_port = pci_get_function(dev);
1044 }
1045
1122 isp->isp_port = pci_get_function(dev);
1123 }
1124
1125 if (IS_23XX(isp)) {
1126 /*
1127 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command.
1128 */
1129 isp->isp_touched = 1;
1130 }
1131
1046 /*
1047 * Make sure we're in reset state.
1048 */
1049 ISP_LOCK(isp);
1050 isp_reset(isp);
1051 if (isp->isp_state != ISP_RESETSTATE) {
1052 ISP_UNLOCK(isp);
1053 goto bad;

--- 10 unchanged lines hidden (view full) ---

1064 ISP_UNLOCK(isp);
1065 goto bad;
1066 }
1067 /*
1068 * XXXX: Here is where we might unload the f/w module
1069 * XXXX: (or decrease the reference count to it).
1070 */
1071 ISP_UNLOCK(isp);
1132 /*
1133 * Make sure we're in reset state.
1134 */
1135 ISP_LOCK(isp);
1136 isp_reset(isp);
1137 if (isp->isp_state != ISP_RESETSTATE) {
1138 ISP_UNLOCK(isp);
1139 goto bad;

--- 10 unchanged lines hidden (view full) ---

1150 ISP_UNLOCK(isp);
1151 goto bad;
1152 }
1153 /*
1154 * XXXX: Here is where we might unload the f/w module
1155 * XXXX: (or decrease the reference count to it).
1156 */
1157 ISP_UNLOCK(isp);
1158
1072 return (0);
1073
1074bad:
1075
1076 if (pcs && pcs->ih) {
1077 (void) bus_teardown_intr(dev, irq, pcs->ih);
1078 }
1079

--- 25 unchanged lines hidden (view full) ---

1105
1106 /*
1107 * XXXX: Here is where we might unload the f/w module
1108 * XXXX: (or decrease the reference count to it).
1109 */
1110 return (ENXIO);
1111}
1112
1159 return (0);
1160
1161bad:
1162
1163 if (pcs && pcs->ih) {
1164 (void) bus_teardown_intr(dev, irq, pcs->ih);
1165 }
1166

--- 25 unchanged lines hidden (view full) ---

1192
1193 /*
1194 * XXXX: Here is where we might unload the f/w module
1195 * XXXX: (or decrease the reference count to it).
1196 */
1197 return (ENXIO);
1198}
1199
1200static int
1201isp_pci_detach(device_t dev)
1202{
1203 struct isp_pcisoftc *pcs;
1204 ispsoftc_t *isp;
1205
1206 pcs = device_get_softc(dev);
1207 if (pcs == NULL) {
1208 return (ENXIO);
1209 }
1210 isp = (ispsoftc_t *) pcs;
1211 ISP_DISABLE_INTS(isp);
1212 return (0);
1213}
1214
1113static void
1114isp_pci_intr(void *arg)
1115{
1116 ispsoftc_t *isp = arg;
1215static void
1216isp_pci_intr(void *arg)
1217{
1218 ispsoftc_t *isp = arg;
1117 uint16_t isr, sema, mbox;
1219 uint32_t isr;
1220 uint16_t sema, mbox;
1118
1119 ISP_LOCK(isp);
1120 isp->isp_intcnt++;
1121 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) {
1122 isp->isp_intbogus++;
1123 } else {
1221
1222 ISP_LOCK(isp);
1223 isp->isp_intcnt++;
1224 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) {
1225 isp->isp_intbogus++;
1226 } else {
1124 int iok = isp->isp_osinfo.intsok;
1125 isp->isp_osinfo.intsok = 0;
1126 isp_intr(isp, isr, sema, mbox);
1227 isp_intr(isp, isr, sema, mbox);
1127 isp->isp_osinfo.intsok = iok;
1128 }
1129 ISP_UNLOCK(isp);
1130}
1131
1132
1133#define IspVirt2Off(a, x) \
1134 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
1135 _BLK_REG_SHFT] + ((x) & 0xfff))
1136
1137#define BXR2(pcs, off) \
1138 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off)
1139#define BXW2(pcs, off, v) \
1140 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v)
1228 }
1229 ISP_UNLOCK(isp);
1230}
1231
1232
1233#define IspVirt2Off(a, x) \
1234 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
1235 _BLK_REG_SHFT] + ((x) & 0xfff))
1236
1237#define BXR2(pcs, off) \
1238 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off)
1239#define BXW2(pcs, off, v) \
1240 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v)
1241#define BXR4(pcs, off) \
1242 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off)
1243#define BXW4(pcs, off, v) \
1244 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v)
1141
1142
1143static __inline int
1144isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
1145{
1146 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1245
1246
1247static __inline int
1248isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
1249{
1250 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1147 uint16_t val0, val1;
1251 uint32_t val0, val1;
1148 int i = 0;
1149
1150 do {
1151 val0 = BXR2(pcs, IspVirt2Off(isp, off));
1152 val1 = BXR2(pcs, IspVirt2Off(isp, off));
1153 } while (val0 != val1 && ++i < 1000);
1154 if (val0 != val1) {
1155 return (1);
1156 }
1157 *rp = val0;
1158 return (0);
1159}
1160
1161static int
1252 int i = 0;
1253
1254 do {
1255 val0 = BXR2(pcs, IspVirt2Off(isp, off));
1256 val1 = BXR2(pcs, IspVirt2Off(isp, off));
1257 } while (val0 != val1 && ++i < 1000);
1258 if (val0 != val1) {
1259 return (1);
1260 }
1261 *rp = val0;
1262 return (0);
1263}
1264
1265static int
1162isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp,
1266isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp,
1163 uint16_t *semap, uint16_t *mbp)
1164{
1165 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1166 uint16_t isr, sema;
1167
1168 if (IS_2100(isp)) {
1169 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
1170 return (0);

--- 20 unchanged lines hidden (view full) ---

1191 } else {
1192 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0));
1193 }
1194 }
1195 return (1);
1196}
1197
1198static int
1267 uint16_t *semap, uint16_t *mbp)
1268{
1269 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1270 uint16_t isr, sema;
1271
1272 if (IS_2100(isp)) {
1273 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
1274 return (0);

--- 20 unchanged lines hidden (view full) ---

1295 } else {
1296 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0));
1297 }
1298 }
1299 return (1);
1300}
1301
1302static int
1199isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp,
1303isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp,
1200 uint16_t *semap, uint16_t *mbox0p)
1201{
1202 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1304 uint16_t *semap, uint16_t *mbox0p)
1305{
1306 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1203 uint16_t hccr;
1307 uint32_t hccr;
1204 uint32_t r2hisr;
1205
1206 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) {
1207 *isrp = 0;
1208 return (0);
1209 }
1308 uint32_t r2hisr;
1309
1310 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) {
1311 *isrp = 0;
1312 return (0);
1313 }
1210 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh,
1211 IspVirt2Off(pcs, BIU_R2HSTSLO));
1314 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU_R2HSTSLO));
1212 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1213 if ((r2hisr & BIU_R2HST_INTR) == 0) {
1214 *isrp = 0;
1215 return (0);
1216 }
1217 switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
1218 case ISPR2HST_ROM_MBX_OK:
1219 case ISPR2HST_ROM_MBX_FAIL:

--- 27 unchanged lines hidden (view full) ---

1247 default:
1248 hccr = ISP_READ(isp, HCCR);
1249 if (hccr & HCCR_PAUSE) {
1250 ISP_WRITE(isp, HCCR, HCCR_RESET);
1251 isp_prt(isp, ISP_LOGERR,
1252 "RISC paused at interrupt (%x->%x\n", hccr,
1253 ISP_READ(isp, HCCR));
1254 } else {
1315 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1316 if ((r2hisr & BIU_R2HST_INTR) == 0) {
1317 *isrp = 0;
1318 return (0);
1319 }
1320 switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
1321 case ISPR2HST_ROM_MBX_OK:
1322 case ISPR2HST_ROM_MBX_FAIL:

--- 27 unchanged lines hidden (view full) ---

1350 default:
1351 hccr = ISP_READ(isp, HCCR);
1352 if (hccr & HCCR_PAUSE) {
1353 ISP_WRITE(isp, HCCR, HCCR_RESET);
1354 isp_prt(isp, ISP_LOGERR,
1355 "RISC paused at interrupt (%x->%x\n", hccr,
1356 ISP_READ(isp, HCCR));
1357 } else {
1255 isp_prt(isp, ISP_LOGERR, "unknown interrerupt 0x%x\n",
1358 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n",
1256 r2hisr);
1257 }
1258 return (0);
1259 }
1260}
1261
1359 r2hisr);
1360 }
1361 return (0);
1362 }
1363}
1364
1262static uint16_t
1365static int
1366isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp,
1367 uint16_t *semap, uint16_t *mbox0p)
1368{
1369 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1370 uint32_t r2hisr;
1371
1372 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO));
1373 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1374 if ((r2hisr & BIU2400_R2HST_INTR) == 0) {
1375 *isrp = 0;
1376 return (0);
1377 }
1378 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) {
1379 case ISP2400R2HST_ROM_MBX_OK:
1380 case ISP2400R2HST_ROM_MBX_FAIL:
1381 case ISP2400R2HST_MBX_OK:
1382 case ISP2400R2HST_MBX_FAIL:
1383 case ISP2400R2HST_ASYNC_EVENT:
1384 *isrp = r2hisr & 0xffff;
1385 *mbox0p = (r2hisr >> 16);
1386 *semap = 1;
1387 return (1);
1388 case ISP2400R2HST_RSPQ_UPDATE:
1389 case ISP2400R2HST_ATIO_RSPQ_UPDATE:
1390 case ISP2400R2HST_ATIO_RQST_UPDATE:
1391 *isrp = r2hisr & 0xffff;
1392 *mbox0p = 0;
1393 *semap = 0;
1394 return (1);
1395 default:
1396 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
1397 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1398 return (0);
1399 }
1400}
1401
1402static uint32_t
1263isp_pci_rd_reg(ispsoftc_t *isp, int regoff)
1264{
1403isp_pci_rd_reg(ispsoftc_t *isp, int regoff)
1404{
1265 uint16_t rv;
1405 uint32_t rv;
1266 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1267 int oldconf = 0;
1268
1269 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1270 /*
1271 * We will assume that someone has paused the RISC processor.
1272 */
1273 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1274 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1275 oldconf | BIU_PCI_CONF1_SXP);
1276 }
1277 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1278 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1279 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1280 }
1281 return (rv);
1282}
1283
1284static void
1406 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1407 int oldconf = 0;
1408
1409 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1410 /*
1411 * We will assume that someone has paused the RISC processor.
1412 */
1413 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1414 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1415 oldconf | BIU_PCI_CONF1_SXP);
1416 }
1417 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1418 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1419 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1420 }
1421 return (rv);
1422}
1423
1424static void
1285isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint16_t val)
1425isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val)
1286{
1287 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1288 int oldconf = 0;
1426{
1427 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1428 int oldconf = 0;
1429 volatile int junk;
1289
1290 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1291 /*
1292 * We will assume that someone has paused the RISC processor.
1293 */
1294 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1295 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1296 oldconf | BIU_PCI_CONF1_SXP);
1430
1431 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1432 /*
1433 * We will assume that someone has paused the RISC processor.
1434 */
1435 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1436 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1437 oldconf | BIU_PCI_CONF1_SXP);
1438 junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1297 }
1298 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1439 }
1440 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1441 junk = BXR2(pcs, IspVirt2Off(isp, regoff));
1299 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1300 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1442 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1443 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1444 junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1301 }
1302}
1303
1445 }
1446}
1447
1304static uint16_t
1448static uint32_t
1305isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff)
1306{
1449isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff)
1450{
1307 uint16_t rv, oc = 0;
1451 uint32_t rv, oc = 0;
1308 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1309
1310 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1311 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1452 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1453
1454 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1455 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1312 uint16_t tc;
1456 uint32_t tc;
1313 /*
1314 * We will assume that someone has paused the RISC processor.
1315 */
1316 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1317 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1318 if (regoff & SXP_BANK1_SELECT)
1319 tc |= BIU_PCI1080_CONF1_SXP1;
1320 else

--- 7 unchanged lines hidden (view full) ---

1328 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1329 if (oc) {
1330 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1331 }
1332 return (rv);
1333}
1334
1335static void
1457 /*
1458 * We will assume that someone has paused the RISC processor.
1459 */
1460 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1461 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1462 if (regoff & SXP_BANK1_SELECT)
1463 tc |= BIU_PCI1080_CONF1_SXP1;
1464 else

--- 7 unchanged lines hidden (view full) ---

1472 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1473 if (oc) {
1474 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1475 }
1476 return (rv);
1477}
1478
1479static void
1336isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint16_t val)
1480isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val)
1337{
1338 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1339 int oc = 0;
1481{
1482 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1483 int oc = 0;
1484 volatile int junk;
1340
1341 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1342 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1485
1486 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1487 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1343 uint16_t tc;
1488 uint32_t tc;
1344 /*
1345 * We will assume that someone has paused the RISC processor.
1346 */
1347 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1348 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1349 if (regoff & SXP_BANK1_SELECT)
1350 tc |= BIU_PCI1080_CONF1_SXP1;
1351 else
1352 tc |= BIU_PCI1080_CONF1_SXP0;
1353 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1489 /*
1490 * We will assume that someone has paused the RISC processor.
1491 */
1492 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1493 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1494 if (regoff & SXP_BANK1_SELECT)
1495 tc |= BIU_PCI1080_CONF1_SXP1;
1496 else
1497 tc |= BIU_PCI1080_CONF1_SXP0;
1498 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1499 junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1354 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1355 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1356 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1357 oc | BIU_PCI1080_CONF1_DMA);
1500 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1501 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1502 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1503 oc | BIU_PCI1080_CONF1_DMA);
1504 junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1358 }
1359 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1505 }
1506 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1507 junk = BXR2(pcs, IspVirt2Off(isp, regoff));
1360 if (oc) {
1361 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1508 if (oc) {
1509 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1510 junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1362 }
1363}
1364
1511 }
1512}
1513
1514static uint32_t
1515isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
1516{
1517 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1518 uint32_t rv;
1519 int block = regoff & _BLK_REG_MASK;
1365
1520
1521 switch (block) {
1522 case BIU_BLOCK:
1523 break;
1524 case MBOX_BLOCK:
1525 return (BXR2(pcs, IspVirt2Off(pcs, regoff)));
1526 case SXP_BLOCK:
1527 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
1528 return (0xffffffff);
1529 case RISC_BLOCK:
1530 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
1531 return (0xffffffff);
1532 case DMA_BLOCK:
1533 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
1534 return (0xffffffff);
1535 default:
1536 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
1537 return (0xffffffff);
1538 }
1539
1540
1541 switch (regoff) {
1542 case BIU2400_FLASH_ADDR:
1543 case BIU2400_FLASH_DATA:
1544 case BIU2400_ICR:
1545 case BIU2400_ISR:
1546 case BIU2400_CSR:
1547 case BIU2400_REQINP:
1548 case BIU2400_REQOUTP:
1549 case BIU2400_RSPINP:
1550 case BIU2400_RSPOUTP:
1551 case BIU2400_PRI_RQINP:
1552 case BIU2400_PRI_RSPINP:
1553 case BIU2400_ATIO_RSPINP:
1554 case BIU2400_ATIO_REQINP:
1555 case BIU2400_HCCR:
1556 case BIU2400_GPIOD:
1557 case BIU2400_GPIOE:
1558 case BIU2400_HSEMA:
1559 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1560 break;
1561 case BIU2400_R2HSTSLO:
1562 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1563 break;
1564 case BIU2400_R2HSTSHI:
1565 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16;
1566 break;
1567 default:
1568 isp_prt(isp, ISP_LOGERR,
1569 "isp_pci_rd_reg_2400: unknown offset %x", regoff);
1570 rv = 0xffffffff;
1571 break;
1572 }
1573 return (rv);
1574}
1575
1576static void
1577isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1578{
1579 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1580 int block = regoff & _BLK_REG_MASK;
1581 volatile int junk;
1582
1583 switch (block) {
1584 case BIU_BLOCK:
1585 break;
1586 case MBOX_BLOCK:
1587 BXW2(pcs, IspVirt2Off(pcs, regoff), val);
1588 junk = BXR2(pcs, IspVirt2Off(pcs, regoff));
1589 return;
1590 case SXP_BLOCK:
1591 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
1592 return;
1593 case RISC_BLOCK:
1594 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
1595 return;
1596 case DMA_BLOCK:
1597 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
1598 return;
1599 default:
1600 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
1601 regoff);
1602 break;
1603 }
1604
1605 switch (regoff) {
1606 case BIU2400_FLASH_ADDR:
1607 case BIU2400_FLASH_DATA:
1608 case BIU2400_ICR:
1609 case BIU2400_ISR:
1610 case BIU2400_CSR:
1611 case BIU2400_REQINP:
1612 case BIU2400_REQOUTP:
1613 case BIU2400_RSPINP:
1614 case BIU2400_RSPOUTP:
1615 case BIU2400_PRI_RQINP:
1616 case BIU2400_PRI_RSPINP:
1617 case BIU2400_ATIO_RSPINP:
1618 case BIU2400_ATIO_REQINP:
1619 case BIU2400_HCCR:
1620 case BIU2400_GPIOD:
1621 case BIU2400_GPIOE:
1622 case BIU2400_HSEMA:
1623 BXW4(pcs, IspVirt2Off(pcs, regoff), val);
1624 junk = BXR4(pcs, IspVirt2Off(pcs, regoff));
1625 break;
1626 default:
1627 isp_prt(isp, ISP_LOGERR,
1628 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
1629 break;
1630 }
1631}
1632
1633
1366struct imush {
1367 ispsoftc_t *isp;
1368 int error;
1369};
1370
1371static void imc(void *, bus_dma_segment_t *, int, int);
1372
1373static void

--- 51 unchanged lines hidden (view full) ---

1425
1426 /*
1427 * Already been here? If so, leave...
1428 */
1429 if (isp->isp_rquest) {
1430 return (0);
1431 }
1432
1634struct imush {
1635 ispsoftc_t *isp;
1636 int error;
1637};
1638
1639static void imc(void *, bus_dma_segment_t *, int, int);
1640
1641static void

--- 51 unchanged lines hidden (view full) ---

1693
1694 /*
1695 * Already been here? If so, leave...
1696 */
1697 if (isp->isp_rquest) {
1698 return (0);
1699 }
1700
1701 if (isp->isp_maxcmds == 0) {
1702 isp_prt(isp, ISP_LOGERR, "maxcmds not set");
1703 return (1);
1704 }
1705
1433 hlim = BUS_SPACE_MAXADDR;
1434 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) {
1435 slim = (bus_size_t) (1ULL << 32);
1436 llim = BUS_SPACE_MAXADDR;
1437 } else {
1438 llim = BUS_SPACE_MAXADDR_32BIT;
1439 slim = (1 << 24);
1440 }

--- 130 unchanged lines hidden (view full) ---

1571 isp->isp_rquest = NULL;
1572 return (1);
1573}
1574
1575typedef struct {
1576 ispsoftc_t *isp;
1577 void *cmd_token;
1578 void *rq;
1706 hlim = BUS_SPACE_MAXADDR;
1707 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) {
1708 slim = (bus_size_t) (1ULL << 32);
1709 llim = BUS_SPACE_MAXADDR;
1710 } else {
1711 llim = BUS_SPACE_MAXADDR_32BIT;
1712 slim = (1 << 24);
1713 }

--- 130 unchanged lines hidden (view full) ---

1844 isp->isp_rquest = NULL;
1845 return (1);
1846}
1847
1848typedef struct {
1849 ispsoftc_t *isp;
1850 void *cmd_token;
1851 void *rq;
1579 uint16_t *nxtip;
1580 uint16_t optr;
1852 uint32_t *nxtip;
1853 uint32_t optr;
1581 int error;
1582} mush_t;
1583
1584#define MUSHERR_NOQENTRIES -2
1585
1586#ifdef ISP_TARGET_MODE
1587/*
1588 * We need to handle DMA for target mode differently from initiator mode.

--- 21 unchanged lines hidden (view full) ---

1610{
1611 mush_t *mp;
1612 struct ccb_scsiio *csio;
1613 ispsoftc_t *isp;
1614 struct isp_pcisoftc *pcs;
1615 bus_dmamap_t *dp;
1616 ct_entry_t *cto, *qe;
1617 uint8_t scsi_status;
1854 int error;
1855} mush_t;
1856
1857#define MUSHERR_NOQENTRIES -2
1858
1859#ifdef ISP_TARGET_MODE
1860/*
1861 * We need to handle DMA for target mode differently from initiator mode.

--- 21 unchanged lines hidden (view full) ---

1883{
1884 mush_t *mp;
1885 struct ccb_scsiio *csio;
1886 ispsoftc_t *isp;
1887 struct isp_pcisoftc *pcs;
1888 bus_dmamap_t *dp;
1889 ct_entry_t *cto, *qe;
1890 uint8_t scsi_status;
1618 uint16_t curi, nxti, handle;
1891 uint32_t curi, nxti, handle;
1619 uint32_t sflags;
1620 int32_t resid;
1621 int nth_ctio, nctios, send_status;
1622
1623 mp = (mush_t *) arg;
1624 if (error) {
1625 mp->error = error;
1626 return;

--- 223 unchanged lines hidden (view full) ---

1850
1851static void
1852tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1853{
1854 mush_t *mp;
1855 struct ccb_scsiio *csio;
1856 ispsoftc_t *isp;
1857 ct2_entry_t *cto, *qe;
1892 uint32_t sflags;
1893 int32_t resid;
1894 int nth_ctio, nctios, send_status;
1895
1896 mp = (mush_t *) arg;
1897 if (error) {
1898 mp->error = error;
1899 return;

--- 223 unchanged lines hidden (view full) ---

2123
2124static void
2125tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2126{
2127 mush_t *mp;
2128 struct ccb_scsiio *csio;
2129 ispsoftc_t *isp;
2130 ct2_entry_t *cto, *qe;
1858 uint16_t curi, nxti;
2131 uint32_t curi, nxti;
1859 ispds_t *ds;
1860 ispds64_t *ds64;
1861 int segcnt, seglim;
1862
1863 mp = (mush_t *) arg;
1864 if (error) {
1865 mp->error = error;
1866 return;

--- 22 unchanged lines hidden (view full) ---

1889 cto->ct_header.rqs_seqno = 1;
1890 cto->ct_seg_count = 0;
1891 cto->ct_reloff = 0;
1892 isp_prt(isp, ISP_LOGTDEBUG1,
1893 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts "
1894 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun,
1895 cto->ct_iid, cto->ct_flags, cto->ct_status,
1896 cto->rsp.m1.ct_scsi_status, cto->ct_resid);
2132 ispds_t *ds;
2133 ispds64_t *ds64;
2134 int segcnt, seglim;
2135
2136 mp = (mush_t *) arg;
2137 if (error) {
2138 mp->error = error;
2139 return;

--- 22 unchanged lines hidden (view full) ---

2162 cto->ct_header.rqs_seqno = 1;
2163 cto->ct_seg_count = 0;
2164 cto->ct_reloff = 0;
2165 isp_prt(isp, ISP_LOGTDEBUG1,
2166 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts "
2167 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun,
2168 cto->ct_iid, cto->ct_flags, cto->ct_status,
2169 cto->rsp.m1.ct_scsi_status, cto->ct_resid);
1897 if (IS_2KLOGIN(isp)) {
2170 if (FCPARAM(isp)->isp_2klogin) {
1898 isp_put_ctio2e(isp,
1899 (ct2e_entry_t *)cto, (ct2e_entry_t *)qe);
1900 } else {
1901 isp_put_ctio2(isp, cto, qe);
1902 }
1903 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe);
1904 return;
1905 }

--- 22 unchanged lines hidden (view full) ---

1928 if (addr >= 0x100000000LL) {
1929 break;
1930 }
1931 }
1932 }
1933 if (segcnt != nseg) {
1934 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO3;
1935 seglim = ISP_RQDSEG_T3;
2171 isp_put_ctio2e(isp,
2172 (ct2e_entry_t *)cto, (ct2e_entry_t *)qe);
2173 } else {
2174 isp_put_ctio2(isp, cto, qe);
2175 }
2176 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe);
2177 return;
2178 }

--- 22 unchanged lines hidden (view full) ---

2201 if (addr >= 0x100000000LL) {
2202 break;
2203 }
2204 }
2205 }
2206 if (segcnt != nseg) {
2207 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO3;
2208 seglim = ISP_RQDSEG_T3;
1936 ds64 = &cto->rsp.m0.ct_dataseg64[0];
2209 ds64 = &cto->rsp.m0.u.ct_dataseg64[0];
1937 ds = NULL;
1938 } else {
1939 seglim = ISP_RQDSEG_T2;
1940 ds64 = NULL;
2210 ds = NULL;
2211 } else {
2212 seglim = ISP_RQDSEG_T2;
2213 ds64 = NULL;
1941 ds = &cto->rsp.m0.ct_dataseg[0];
2214 ds = &cto->rsp.m0.u.ct_dataseg[0];
1942 }
1943 cto->ct_seg_count = 0;
1944
1945 /*
1946 * Set up the CTIO2 data segments.
1947 */
1948 for (segcnt = 0; cto->ct_seg_count < seglim && segcnt < nseg;
1949 cto->ct_seg_count++, segcnt++) {

--- 18 unchanged lines hidden (view full) ---

1968 isp_prt(isp, ISP_LOGTDEBUG1,
1969 "isp_send_ctio2: ent0[%d]0x%jx:%ju",
1970 cto->ct_seg_count, (uintmax_t)dm_segs[segcnt].ds_addr,
1971 (uintmax_t)dm_segs[segcnt].ds_len);
1972#endif
1973 }
1974
1975 while (segcnt < nseg) {
2215 }
2216 cto->ct_seg_count = 0;
2217
2218 /*
2219 * Set up the CTIO2 data segments.
2220 */
2221 for (segcnt = 0; cto->ct_seg_count < seglim && segcnt < nseg;
2222 cto->ct_seg_count++, segcnt++) {

--- 18 unchanged lines hidden (view full) ---

2241 isp_prt(isp, ISP_LOGTDEBUG1,
2242 "isp_send_ctio2: ent0[%d]0x%jx:%ju",
2243 cto->ct_seg_count, (uintmax_t)dm_segs[segcnt].ds_addr,
2244 (uintmax_t)dm_segs[segcnt].ds_len);
2245#endif
2246 }
2247
2248 while (segcnt < nseg) {
1976 uint16_t curip;
2249 uint32_t curip;
1977 int seg;
1978 ispcontreq_t local, *crq = &local, *qep;
1979
1980 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti);
1981 curip = nxti;
1982 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp));
1983 if (nxti == mp->optr) {
1984 ISP_UNLOCK(isp);

--- 54 unchanged lines hidden (view full) ---

2039 * No do final twiddling for the CTIO itself.
2040 */
2041 cto->ct_header.rqs_seqno = 1;
2042 isp_prt(isp, ISP_LOGTDEBUG1,
2043 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d",
2044 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid,
2045 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status,
2046 cto->ct_resid);
2250 int seg;
2251 ispcontreq_t local, *crq = &local, *qep;
2252
2253 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti);
2254 curip = nxti;
2255 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp));
2256 if (nxti == mp->optr) {
2257 ISP_UNLOCK(isp);

--- 54 unchanged lines hidden (view full) ---

2312 * No do final twiddling for the CTIO itself.
2313 */
2314 cto->ct_header.rqs_seqno = 1;
2315 isp_prt(isp, ISP_LOGTDEBUG1,
2316 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d",
2317 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid,
2318 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status,
2319 cto->ct_resid);
2047 if (IS_2KLOGIN(isp))
2320 if (FCPARAM(isp)->isp_2klogin) {
2048 isp_put_ctio2e(isp, (ct2e_entry_t *)cto, (ct2e_entry_t *)qe);
2321 isp_put_ctio2e(isp, (ct2e_entry_t *)cto, (ct2e_entry_t *)qe);
2049 else
2322 } else {
2050 isp_put_ctio2(isp, cto, qe);
2323 isp_put_ctio2(isp, cto, qe);
2324 }
2051 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe);
2052 *mp->nxtip = nxti;
2053}
2054#endif
2055
2325 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe);
2326 *mp->nxtip = nxti;
2327}
2328#endif
2329
2330static void dma_2400(void *, bus_dma_segment_t *, int, int);
2056static void dma2_a64(void *, bus_dma_segment_t *, int, int);
2057static void dma2(void *, bus_dma_segment_t *, int, int);
2058
2059static void
2331static void dma2_a64(void *, bus_dma_segment_t *, int, int);
2332static void dma2(void *, bus_dma_segment_t *, int, int);
2333
2334static void
2335dma_2400(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2336{
2337 mush_t *mp;
2338 ispsoftc_t *isp;
2339 struct ccb_scsiio *csio;
2340 struct isp_pcisoftc *pcs;
2341 bus_dmamap_t *dp;
2342 bus_dma_segment_t *eseg;
2343 ispreqt7_t *rq;
2344 int seglim, datalen;
2345 uint32_t nxti;
2346
2347 mp = (mush_t *) arg;
2348 if (error) {
2349 mp->error = error;
2350 return;
2351 }
2352
2353 if (nseg < 1) {
2354 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg);
2355 mp->error = EFAULT;
2356 return;
2357 }
2358
2359 csio = mp->cmd_token;
2360 isp = mp->isp;
2361 rq = mp->rq;
2362 pcs = (struct isp_pcisoftc *)mp->isp;
2363 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)];
2364 nxti = *mp->nxtip;
2365
2366 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
2367 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD);
2368 } else {
2369 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE);
2370 }
2371 datalen = XS_XFRLEN(csio);
2372
2373 /*
2374 * We're passed an initial partially filled in entry that
2375 * has most fields filled in except for data transfer
2376 * related values.
2377 *
2378 * Our job is to fill in the initial request queue entry and
2379 * then to start allocating and filling in continuation entries
2380 * until we've covered the entire transfer.
2381 */
2382
2383 rq->req_header.rqs_entry_type = RQSTYPE_T7RQS;
2384 rq->req_dl = datalen;
2385 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
2386 rq->req_alen_datadir = 0x2;
2387 } else {
2388 rq->req_alen_datadir = 0x1;
2389 }
2390
2391 eseg = dm_segs + nseg;
2392
2393 rq->req_dataseg.ds_base = DMA_LO32(dm_segs->ds_addr);
2394 rq->req_dataseg.ds_basehi = DMA_HI32(dm_segs->ds_addr);
2395 rq->req_dataseg.ds_count = dm_segs->ds_len;
2396
2397 datalen -= dm_segs->ds_len;
2398
2399 dm_segs++;
2400 rq->req_seg_count++;
2401
2402 while (datalen > 0 && dm_segs != eseg) {
2403 uint32_t onxti;
2404 ispcontreq64_t local, *crq = &local, *cqe;
2405
2406 cqe = (ispcontreq64_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti);
2407 onxti = nxti;
2408 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp));
2409 if (nxti == mp->optr) {
2410 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++");
2411 mp->error = MUSHERR_NOQENTRIES;
2412 return;
2413 }
2414 rq->req_header.rqs_entry_count++;
2415 MEMZERO((void *)crq, sizeof (*crq));
2416 crq->req_header.rqs_entry_count = 1;
2417 crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT;
2418
2419 seglim = 0;
2420 while (datalen > 0 && seglim < ISP_CDSEG64 && dm_segs != eseg) {
2421 crq->req_dataseg[seglim].ds_base =
2422 DMA_LO32(dm_segs->ds_addr);
2423 crq->req_dataseg[seglim].ds_basehi =
2424 DMA_HI32(dm_segs->ds_addr);
2425 crq->req_dataseg[seglim].ds_count =
2426 dm_segs->ds_len;
2427 rq->req_seg_count++;
2428 dm_segs++;
2429 seglim++;
2430 datalen -= dm_segs->ds_len;
2431 }
2432 if (isp->isp_dblev & ISP_LOGDEBUG1) {
2433 isp_print_bytes(isp, "Continuation", QENTRY_LEN, crq);
2434 }
2435 isp_put_cont64_req(isp, crq, cqe);
2436 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN);
2437 }
2438 *mp->nxtip = nxti;
2439}
2440
2441static void
2060dma2_a64(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2061{
2062 mush_t *mp;
2063 ispsoftc_t *isp;
2064 struct ccb_scsiio *csio;
2065 struct isp_pcisoftc *pcs;
2066 bus_dmamap_t *dp;
2067 bus_dma_segment_t *eseg;
2068 ispreq64_t *rq;
2069 int seglim, datalen;
2442dma2_a64(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2443{
2444 mush_t *mp;
2445 ispsoftc_t *isp;
2446 struct ccb_scsiio *csio;
2447 struct isp_pcisoftc *pcs;
2448 bus_dmamap_t *dp;
2449 bus_dma_segment_t *eseg;
2450 ispreq64_t *rq;
2451 int seglim, datalen;
2070 uint16_t nxti;
2452 uint32_t nxti;
2071
2072 mp = (mush_t *) arg;
2073 if (error) {
2074 mp->error = error;
2075 return;
2076 }
2077
2078 if (nseg < 1) {

--- 68 unchanged lines hidden (view full) ---

2147 dm_segs->ds_len;
2148 }
2149 datalen -= dm_segs->ds_len;
2150 rq->req_seg_count++;
2151 dm_segs++;
2152 }
2153
2154 while (datalen > 0 && dm_segs != eseg) {
2453
2454 mp = (mush_t *) arg;
2455 if (error) {
2456 mp->error = error;
2457 return;
2458 }
2459
2460 if (nseg < 1) {

--- 68 unchanged lines hidden (view full) ---

2529 dm_segs->ds_len;
2530 }
2531 datalen -= dm_segs->ds_len;
2532 rq->req_seg_count++;
2533 dm_segs++;
2534 }
2535
2536 while (datalen > 0 && dm_segs != eseg) {
2155 uint16_t onxti;
2537 uint32_t onxti;
2156 ispcontreq64_t local, *crq = &local, *cqe;
2157
2158 cqe = (ispcontreq64_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti);
2159 onxti = nxti;
2160 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp));
2161 if (nxti == mp->optr) {
2162 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++");
2163 mp->error = MUSHERR_NOQENTRIES;

--- 12 unchanged lines hidden (view full) ---

2176 DMA_HI32(dm_segs->ds_addr);
2177 crq->req_dataseg[seglim].ds_count =
2178 dm_segs->ds_len;
2179 rq->req_seg_count++;
2180 dm_segs++;
2181 seglim++;
2182 datalen -= dm_segs->ds_len;
2183 }
2538 ispcontreq64_t local, *crq = &local, *cqe;
2539
2540 cqe = (ispcontreq64_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti);
2541 onxti = nxti;
2542 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp));
2543 if (nxti == mp->optr) {
2544 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++");
2545 mp->error = MUSHERR_NOQENTRIES;

--- 12 unchanged lines hidden (view full) ---

2558 DMA_HI32(dm_segs->ds_addr);
2559 crq->req_dataseg[seglim].ds_count =
2560 dm_segs->ds_len;
2561 rq->req_seg_count++;
2562 dm_segs++;
2563 seglim++;
2564 datalen -= dm_segs->ds_len;
2565 }
2566 if (isp->isp_dblev & ISP_LOGDEBUG1) {
2567 isp_print_bytes(isp, "Continuation", QENTRY_LEN, crq);
2568 }
2184 isp_put_cont64_req(isp, crq, cqe);
2185 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN);
2186 }
2187 *mp->nxtip = nxti;
2188}
2189
2190static void
2191dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2192{
2193 mush_t *mp;
2194 ispsoftc_t *isp;
2195 struct ccb_scsiio *csio;
2196 struct isp_pcisoftc *pcs;
2197 bus_dmamap_t *dp;
2198 bus_dma_segment_t *eseg;
2199 ispreq_t *rq;
2200 int seglim, datalen;
2569 isp_put_cont64_req(isp, crq, cqe);
2570 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN);
2571 }
2572 *mp->nxtip = nxti;
2573}
2574
2575static void
2576dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2577{
2578 mush_t *mp;
2579 ispsoftc_t *isp;
2580 struct ccb_scsiio *csio;
2581 struct isp_pcisoftc *pcs;
2582 bus_dmamap_t *dp;
2583 bus_dma_segment_t *eseg;
2584 ispreq_t *rq;
2585 int seglim, datalen;
2201 uint16_t nxti;
2586 uint32_t nxti;
2202
2203 mp = (mush_t *) arg;
2204 if (error) {
2205 mp->error = error;
2206 return;
2207 }
2208
2209 if (nseg < 1) {

--- 63 unchanged lines hidden (view full) ---

2273 dm_segs->ds_len;
2274 }
2275 datalen -= dm_segs->ds_len;
2276 rq->req_seg_count++;
2277 dm_segs++;
2278 }
2279
2280 while (datalen > 0 && dm_segs != eseg) {
2587
2588 mp = (mush_t *) arg;
2589 if (error) {
2590 mp->error = error;
2591 return;
2592 }
2593
2594 if (nseg < 1) {

--- 63 unchanged lines hidden (view full) ---

2658 dm_segs->ds_len;
2659 }
2660 datalen -= dm_segs->ds_len;
2661 rq->req_seg_count++;
2662 dm_segs++;
2663 }
2664
2665 while (datalen > 0 && dm_segs != eseg) {
2281 uint16_t onxti;
2666 uint32_t onxti;
2282 ispcontreq_t local, *crq = &local, *cqe;
2283
2284 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti);
2285 onxti = nxti;
2286 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp));
2287 if (nxti == mp->optr) {
2288 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++");
2289 mp->error = MUSHERR_NOQENTRIES;

--- 10 unchanged lines hidden (view full) ---

2300 DMA_LO32(dm_segs->ds_addr);
2301 crq->req_dataseg[seglim].ds_count =
2302 dm_segs->ds_len;
2303 rq->req_seg_count++;
2304 dm_segs++;
2305 seglim++;
2306 datalen -= dm_segs->ds_len;
2307 }
2667 ispcontreq_t local, *crq = &local, *cqe;
2668
2669 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti);
2670 onxti = nxti;
2671 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp));
2672 if (nxti == mp->optr) {
2673 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++");
2674 mp->error = MUSHERR_NOQENTRIES;

--- 10 unchanged lines hidden (view full) ---

2685 DMA_LO32(dm_segs->ds_addr);
2686 crq->req_dataseg[seglim].ds_count =
2687 dm_segs->ds_len;
2688 rq->req_seg_count++;
2689 dm_segs++;
2690 seglim++;
2691 datalen -= dm_segs->ds_len;
2692 }
2693 if (isp->isp_dblev & ISP_LOGDEBUG1) {
2694 isp_print_bytes(isp, "Continuation", QENTRY_LEN, crq);
2695 }
2308 isp_put_cont_req(isp, crq, cqe);
2309 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN);
2310 }
2311 *mp->nxtip = nxti;
2312}
2313
2314/*
2315 * We enter with ISP_LOCK held
2316 */
2317static int
2318isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, ispreq_t *rq,
2696 isp_put_cont_req(isp, crq, cqe);
2697 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN);
2698 }
2699 *mp->nxtip = nxti;
2700}
2701
2702/*
2703 * We enter with ISP_LOCK held
2704 */
2705static int
2706isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, ispreq_t *rq,
2319 uint16_t *nxtip, uint16_t optr)
2707 uint32_t *nxtip, uint32_t optr)
2320{
2321 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2322 ispreq_t *qep;
2323 bus_dmamap_t *dp = NULL;
2324 mush_t mush, *mp;
2325 void (*eptr)(void *, bus_dma_segment_t *, int, int);
2326
2327 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx);

--- 15 unchanged lines hidden (view full) ---

2343 mp->error = 0;
2344 ISPLOCK_2_CAMLOCK(isp);
2345 (*eptr)(mp, NULL, 0, 0);
2346 CAMLOCK_2_ISPLOCK(isp);
2347 goto mbxsync;
2348 }
2349 } else
2350#endif
2708{
2709 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2710 ispreq_t *qep;
2711 bus_dmamap_t *dp = NULL;
2712 mush_t mush, *mp;
2713 void (*eptr)(void *, bus_dma_segment_t *, int, int);
2714
2715 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx);

--- 15 unchanged lines hidden (view full) ---

2731 mp->error = 0;
2732 ISPLOCK_2_CAMLOCK(isp);
2733 (*eptr)(mp, NULL, 0, 0);
2734 CAMLOCK_2_ISPLOCK(isp);
2735 goto mbxsync;
2736 }
2737 } else
2738#endif
2351 if (sizeof (bus_addr_t) > 4) {
2739 if (IS_24XX(isp)) {
2740 eptr = dma_2400;
2741 } else if (sizeof (bus_addr_t) > 4) {
2352 eptr = dma2_a64;
2353 } else {
2354 eptr = dma2;
2355 }
2356
2357
2358 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE ||
2359 (csio->dxfer_len == 0)) {

--- 68 unchanged lines hidden (view full) ---

2428 } else if (mp->error == EINVAL) {
2429 XS_SETERR(csio, CAM_REQ_INVALID);
2430 } else {
2431 XS_SETERR(csio, CAM_UNREC_HBA_ERROR);
2432 }
2433 return (retval);
2434 }
2435mbxsync:
2742 eptr = dma2_a64;
2743 } else {
2744 eptr = dma2;
2745 }
2746
2747
2748 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE ||
2749 (csio->dxfer_len == 0)) {

--- 68 unchanged lines hidden (view full) ---

2818 } else if (mp->error == EINVAL) {
2819 XS_SETERR(csio, CAM_REQ_INVALID);
2820 } else {
2821 XS_SETERR(csio, CAM_UNREC_HBA_ERROR);
2822 }
2823 return (retval);
2824 }
2825mbxsync:
2826 if (isp->isp_dblev & ISP_LOGDEBUG1) {
2827 isp_print_bytes(isp, "Request Queue Entry", QENTRY_LEN, rq);
2828 }
2436 switch (rq->req_header.rqs_entry_type) {
2437 case RQSTYPE_REQUEST:
2438 isp_put_request(isp, rq, qep);
2439 break;
2440 case RQSTYPE_CMDONLY:
2441 isp_put_extended_request(isp, (ispextreq_t *)rq,
2442 (ispextreq_t *)qep);
2443 break;
2444 case RQSTYPE_T2RQS:
2445 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep);
2446 break;
2447 case RQSTYPE_A64:
2448 case RQSTYPE_T3RQS:
2449 isp_put_request_t3(isp, (ispreqt3_t *) rq, (ispreqt3_t *) qep);
2450 break;
2829 switch (rq->req_header.rqs_entry_type) {
2830 case RQSTYPE_REQUEST:
2831 isp_put_request(isp, rq, qep);
2832 break;
2833 case RQSTYPE_CMDONLY:
2834 isp_put_extended_request(isp, (ispextreq_t *)rq,
2835 (ispextreq_t *)qep);
2836 break;
2837 case RQSTYPE_T2RQS:
2838 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep);
2839 break;
2840 case RQSTYPE_A64:
2841 case RQSTYPE_T3RQS:
2842 isp_put_request_t3(isp, (ispreqt3_t *) rq, (ispreqt3_t *) qep);
2843 break;
2844 case RQSTYPE_T7RQS:
2845 isp_put_request_t7(isp, (ispreqt7_t *) rq, (ispreqt7_t *) qep);
2846 break;
2451 }
2452 return (CMD_QUEUED);
2453}
2454
2455static void
2847 }
2848 return (CMD_QUEUED);
2849}
2850
2851static void
2456isp_pci_dmateardown(ispsoftc_t *isp, XS_T *xs, uint16_t handle)
2852isp_pci_dmateardown(ispsoftc_t *isp, XS_T *xs, uint32_t handle)
2457{
2458 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2459 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)];
2460 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
2461 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD);
2462 } else {
2463 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE);
2464 }
2465 bus_dmamap_unload(pcs->dmat, *dp);
2466}
2467
2468
2469static void
2470isp_pci_reset1(ispsoftc_t *isp)
2471{
2853{
2854 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2855 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)];
2856 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
2857 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD);
2858 } else {
2859 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE);
2860 }
2861 bus_dmamap_unload(pcs->dmat, *dp);
2862}
2863
2864
2865static void
2866isp_pci_reset1(ispsoftc_t *isp)
2867{
2472 /* Make sure the BIOS is disabled */
2473 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
2868 if (!IS_24XX(isp)) {
2869 /* Make sure the BIOS is disabled */
2870 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
2871 }
2474 /* and enable interrupts */
2872 /* and enable interrupts */
2475 ENABLE_INTS(isp);
2873 ISP_ENABLE_INTS(isp);
2476}
2477
2478static void
2479isp_pci_dumpregs(ispsoftc_t *isp, const char *msg)
2480{
2481 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2482 if (msg)
2483 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg);

--- 32 unchanged lines hidden --- 		2874}
2875
2876static void
2877isp_pci_dumpregs(ispsoftc_t *isp, const char *msg)
2878{
2879 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2880 if (msg)
2881 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg);

--- 32 unchanged lines hidden ---