Deleted Added
sdiff udiff text old ( 200669 ) new ( 206089 )
full compact
hwpmc_intel.c (200669) hwpmc_intel.c (206089)
1/*-
2 * Copyright (c) 2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * SUCH DAMAGE.
25 */
26
27/*
28 * Common code for handling Intel CPUs.
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * SUCH DAMAGE.
25 */
26
27/*
28 * Common code for handling Intel CPUs.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 200669 2009-12-18 15:01:46Z jkoshy $");
32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 206089 2010-04-02 13:23:49Z fabient $");
33
34#include <sys/param.h>
35#include <sys/pmc.h>
36#include <sys/pmckern.h>
37#include <sys/systm.h>
38
39#include <machine/cpu.h>
40#include <machine/cputypes.h>

--- 87 unchanged lines hidden (view full) ---

128 break;
129 case 0x1C: /* Per Intel document 320047-002. */
130 cputype = PMC_CPU_INTEL_ATOM;
131 nclasses = 3;
132 break;
133 case 0x1A:
134 case 0x1E: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
135 case 0x1F: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
33
34#include <sys/param.h>
35#include <sys/pmc.h>
36#include <sys/pmckern.h>
37#include <sys/systm.h>
38
39#include <machine/cpu.h>
40#include <machine/cputypes.h>

--- 87 unchanged lines hidden (view full) ---

128 break;
129 case 0x1C: /* Per Intel document 320047-002. */
130 cputype = PMC_CPU_INTEL_ATOM;
131 nclasses = 3;
132 break;
133 case 0x1A:
134 case 0x1E: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
135 case 0x1F: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
136 case 0x2E:
136 cputype = PMC_CPU_INTEL_COREI7;
137 cputype = PMC_CPU_INTEL_COREI7;
137 nclasses = 3;
138 nclasses = 5;
138 break;
139 break;
140 case 0x25: /* Per Intel document 253669-033US 12/2009. */
141 case 0x2C: /* Per Intel document 253669-033US 12/2009. */
142 cputype = PMC_CPU_INTEL_WESTMERE;
143 nclasses = 5;
144 break;
139 }
140 break;
141#if defined(__i386__) || defined(__amd64__)
142 case 0xF00: /* P4 */
143 if (model >= 0 && model <= 6) /* known models */
144 cputype = PMC_CPU_INTEL_PIV;
145 break;
146 }

--- 24 unchanged lines hidden (view full) ---

171 /*
172 * Intel Core, Core 2 and Atom processors.
173 */
174 case PMC_CPU_INTEL_ATOM:
175 case PMC_CPU_INTEL_CORE:
176 case PMC_CPU_INTEL_CORE2:
177 case PMC_CPU_INTEL_CORE2EXTREME:
178 case PMC_CPU_INTEL_COREI7:
145 }
146 break;
147#if defined(__i386__) || defined(__amd64__)
148 case 0xF00: /* P4 */
149 if (model >= 0 && model <= 6) /* known models */
150 cputype = PMC_CPU_INTEL_PIV;
151 break;
152 }

--- 24 unchanged lines hidden (view full) ---

177 /*
178 * Intel Core, Core 2 and Atom processors.
179 */
180 case PMC_CPU_INTEL_ATOM:
181 case PMC_CPU_INTEL_CORE:
182 case PMC_CPU_INTEL_CORE2:
183 case PMC_CPU_INTEL_CORE2EXTREME:
184 case PMC_CPU_INTEL_COREI7:
185 case PMC_CPU_INTEL_WESTMERE:
179 error = pmc_core_initialize(pmc_mdep, ncpus);
180 break;
181
182 /*
183 * Intel Pentium 4 Processors, and P4/EMT64 processors.
184 */
185
186 case PMC_CPU_INTEL_PIV:

--- 34 unchanged lines hidden (view full) ---

221 pmc_mdep->pmd_npmc));
222 break;
223#endif
224
225 default:
226 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
227 }
228
186 error = pmc_core_initialize(pmc_mdep, ncpus);
187 break;
188
189 /*
190 * Intel Pentium 4 Processors, and P4/EMT64 processors.
191 */
192
193 case PMC_CPU_INTEL_PIV:

--- 34 unchanged lines hidden (view full) ---

228 pmc_mdep->pmd_npmc));
229 break;
230#endif
231
232 default:
233 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
234 }
235
236 /*
237 * Init the uncore class.
238 */
239#if defined(__i386__) || defined(__amd64__)
240 switch (cputype) {
241 /*
242 * Intel Corei7 and Westmere processors.
243 */
244 case PMC_CPU_INTEL_COREI7:
245 case PMC_CPU_INTEL_WESTMERE:
246 error = pmc_uncore_initialize(pmc_mdep, ncpus);
247 break;
248 default:
249 break;
250 }
251#endif
229
230 error:
231 if (error) {
232 free(pmc_mdep, M_PMC);
233 pmc_mdep = NULL;
234 }
235
236 return (pmc_mdep);

--- 5 unchanged lines hidden (view full) ---

242 pmc_tsc_finalize(md);
243
244 switch (md->pmd_cputype) {
245#if defined(__i386__) || defined(__amd64__)
246 case PMC_CPU_INTEL_ATOM:
247 case PMC_CPU_INTEL_CORE:
248 case PMC_CPU_INTEL_CORE2:
249 case PMC_CPU_INTEL_CORE2EXTREME:
252
253 error:
254 if (error) {
255 free(pmc_mdep, M_PMC);
256 pmc_mdep = NULL;
257 }
258
259 return (pmc_mdep);

--- 5 unchanged lines hidden (view full) ---

265 pmc_tsc_finalize(md);
266
267 switch (md->pmd_cputype) {
268#if defined(__i386__) || defined(__amd64__)
269 case PMC_CPU_INTEL_ATOM:
270 case PMC_CPU_INTEL_CORE:
271 case PMC_CPU_INTEL_CORE2:
272 case PMC_CPU_INTEL_CORE2EXTREME:
273 case PMC_CPU_INTEL_COREI7:
274 case PMC_CPU_INTEL_WESTMERE:
250 pmc_core_finalize(md);
251 break;
252
253 case PMC_CPU_INTEL_PIV:
254 pmc_p4_finalize(md);
255 break;
256#endif
257#if defined(__i386__)

--- 6 unchanged lines hidden (view full) ---

264 break;
265 case PMC_CPU_INTEL_P5:
266 pmc_p5_finalize(md);
267 break;
268#endif
269 default:
270 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
271 }
275 pmc_core_finalize(md);
276 break;
277
278 case PMC_CPU_INTEL_PIV:
279 pmc_p4_finalize(md);
280 break;
281#endif
282#if defined(__i386__)

--- 6 unchanged lines hidden (view full) ---

289 break;
290 case PMC_CPU_INTEL_P5:
291 pmc_p5_finalize(md);
292 break;
293#endif
294 default:
295 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
296 }
297
298 /*
299 * Uncore.
300 */
301#if defined(__i386__) || defined(__amd64__)
302 switch (md->pmd_cputype) {
303 case PMC_CPU_INTEL_COREI7:
304 case PMC_CPU_INTEL_WESTMERE:
305 pmc_uncore_finalize(md);
306 break;
307 default:
308 break;
309 }
310#endif
272}
311}