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fwohcireg.h (258780) fwohcireg.h (272214)
1/*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
1/*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 258780 2013-11-30 22:17:27Z eadler $
34 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 272214 2014-09-27 16:50:21Z kan $
35 *
36 */
37#define PCI_CBMEM PCIR_BAR(0)
38
39#define FW_VENDORID_NATSEMI 0x100B
40#define FW_VENDORID_NEC 0x1033
41#define FW_VENDORID_SIS 0x1039
42#define FW_VENDORID_TI 0x104c

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179#define FWOHCIEV_ACKBSA 0x15
180#define FWOHCIEV_ACKBSB 0x16
181#define FWOHCIEV_ACKTARD 0x1b
182#define FWOHCIEV_ACKDERR 0x1d
183#define FWOHCIEV_ACKTERR 0x1e
184
185#define FWOHCIEV_MASK 0x1f
186
35 *
36 */
37#define PCI_CBMEM PCIR_BAR(0)
38
39#define FW_VENDORID_NATSEMI 0x100B
40#define FW_VENDORID_NEC 0x1033
41#define FW_VENDORID_SIS 0x1039
42#define FW_VENDORID_TI 0x104c

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179#define FWOHCIEV_ACKBSA 0x15
180#define FWOHCIEV_ACKBSB 0x16
181#define FWOHCIEV_ACKTARD 0x1b
182#define FWOHCIEV_ACKDERR 0x1d
183#define FWOHCIEV_ACKTERR 0x1e
184
185#define FWOHCIEV_MASK 0x1f
186
187struct ohci_dma{
187struct ohci_dma {
188 fwohcireg_t cntl;
189
190#define OHCI_CNTL_CYCMATCH_S (0x1 << 31)
191
192#define OHCI_CNTL_BUFFIL (0x1 << 31)
193#define OHCI_CNTL_ISOHDR (0x1 << 30)
194#define OHCI_CNTL_CYCMATCH_R (0x1 << 29)
195#define OHCI_CNTL_MULTICH (0x1 << 28)

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206 fwohcireg_t dummy0;
207 fwohcireg_t cmd;
208 fwohcireg_t match;
209 fwohcireg_t dummy1;
210 fwohcireg_t dummy2;
211 fwohcireg_t dummy3;
212};
213
188 fwohcireg_t cntl;
189
190#define OHCI_CNTL_CYCMATCH_S (0x1 << 31)
191
192#define OHCI_CNTL_BUFFIL (0x1 << 31)
193#define OHCI_CNTL_ISOHDR (0x1 << 30)
194#define OHCI_CNTL_CYCMATCH_R (0x1 << 29)
195#define OHCI_CNTL_MULTICH (0x1 << 28)

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206 fwohcireg_t dummy0;
207 fwohcireg_t cmd;
208 fwohcireg_t match;
209 fwohcireg_t dummy1;
210 fwohcireg_t dummy2;
211 fwohcireg_t dummy3;
212};
213
214struct ohci_itdma{
214struct ohci_itdma {
215 fwohcireg_t cntl;
216 fwohcireg_t cntl_clr;
217 fwohcireg_t dummy0;
218 fwohcireg_t cmd;
219};
220
221struct ohci_registers {
222 fwohcireg_t ver; /* Version No. 0x0 */

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232#define FWOHCIGUID_H 0x24
233#define FWOHCIGUID_L 0x28
234 fwohcireg_t guid_hi; /* GUID hi 0x24 */
235 fwohcireg_t guid_lo; /* GUID lo 0x28 */
236 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
237 fwohcireg_t config_rom; /* config ROM map 0x34 */
238 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
239 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
215 fwohcireg_t cntl;
216 fwohcireg_t cntl_clr;
217 fwohcireg_t dummy0;
218 fwohcireg_t cmd;
219};
220
221struct ohci_registers {
222 fwohcireg_t ver; /* Version No. 0x0 */

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232#define FWOHCIGUID_H 0x24
233#define FWOHCIGUID_L 0x28
234 fwohcireg_t guid_hi; /* GUID hi 0x24 */
235 fwohcireg_t guid_lo; /* GUID lo 0x28 */
236 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
237 fwohcireg_t config_rom; /* config ROM map 0x34 */
238 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
239 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
240 fwohcireg_t vender; /* vender ID 0x40 */
240 fwohcireg_t vendor; /* vendor ID 0x40 */
241 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
242 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
243 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
244#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */
245#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */
246#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */
247#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */
248#define OHCI_HCC_LPS (1 << 19) /* LPS */

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303 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
304 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
305 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
306 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
307
308 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
309
310 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */
241 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
242 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
243 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
244#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */
245#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */
246#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */
247#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */
248#define OHCI_HCC_LPS (1 << 19) /* LPS */

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303 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
304 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
305 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
306 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
307
308 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
309
310 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */
311
311
312 /* 0x180, 0x184, 0x188, 0x18c */
313 /* 0x190, 0x194, 0x198, 0x19c */
314 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */
315 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */
316 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */
317 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */
318 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */
319 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */
320 struct ohci_dma dma_ch[0x4];
321
322 /* 0x200, 0x204, 0x208, 0x20c */
323 /* 0x210, 0x204, 0x208, 0x20c */
324 struct ohci_itdma dma_itch[0x20];
325
326 /* 0x400, 0x404, 0x408, 0x40c */
327 /* 0x410, 0x404, 0x408, 0x40c */
328 struct ohci_dma dma_irch[0x20];
329};
330
312 /* 0x180, 0x184, 0x188, 0x18c */
313 /* 0x190, 0x194, 0x198, 0x19c */
314 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */
315 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */
316 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */
317 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */
318 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */
319 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */
320 struct ohci_dma dma_ch[0x4];
321
322 /* 0x200, 0x204, 0x208, 0x20c */
323 /* 0x210, 0x204, 0x208, 0x20c */
324 struct ohci_itdma dma_itch[0x20];
325
326 /* 0x400, 0x404, 0x408, 0x40c */
327 /* 0x410, 0x404, 0x408, 0x40c */
328 struct ohci_dma dma_irch[0x20];
329};
330
331struct fwohcidb_tr{
331struct fwohcidb_tr {
332 STAILQ_ENTRY(fwohcidb_tr) link;
333 struct fw_xfer *xfer;
334 struct fwohcidb *db;
335 bus_dmamap_t dma_map;
336 caddr_t buf;
337 bus_addr_t bus_addr;
338 int dbcnt;
339};
340
341/*
342 * OHCI info structure.
343 */
332 STAILQ_ENTRY(fwohcidb_tr) link;
333 struct fw_xfer *xfer;
334 struct fwohcidb *db;
335 bus_dmamap_t dma_map;
336 caddr_t buf;
337 bus_addr_t bus_addr;
338 int dbcnt;
339};
340
341/*
342 * OHCI info structure.
343 */
344struct fwohci_txpkthdr{
345 union{
344struct fwohci_txpkthdr {
345 union {
346 uint32_t ld[4];
347 struct {
348#if BYTE_ORDER == BIG_ENDIAN
349 uint32_t spd:16, /* XXX include reserved field */
350 :8,
351 tcode:4,
352 :4;
353#else

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371 tcode:4,
372 tlrt:8,
373 spd:3,
374 :4,
375 srcbus:1,
376 :8;
377#endif
378 BIT16x2(dst, );
346 uint32_t ld[4];
347 struct {
348#if BYTE_ORDER == BIG_ENDIAN
349 uint32_t spd:16, /* XXX include reserved field */
350 :8,
351 tcode:4,
352 :4;
353#else

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371 tcode:4,
372 tlrt:8,
373 spd:3,
374 :4,
375 srcbus:1,
376 :8;
377#endif
378 BIT16x2(dst, );
379 }asycomm;
379 } asycomm;
380 struct {
381#if BYTE_ORDER == BIG_ENDIAN
382 uint32_t :13,
383 spd:3,
384 chtag:8,
385 tcode:4,
386 sy:4;
387#else
388 uint32_t sy:4,
389 tcode:4,
390 chtag:8,
391 spd:3,
392 :13;
393#endif
394 BIT16x2(len, );
380 struct {
381#if BYTE_ORDER == BIG_ENDIAN
382 uint32_t :13,
383 spd:3,
384 chtag:8,
385 tcode:4,
386 sy:4;
387#else
388 uint32_t sy:4,
389 tcode:4,
390 chtag:8,
391 spd:3,
392 :13;
393#endif
394 BIT16x2(len, );
395 }stream;
396 }mode;
395 } stream;
396 } mode;
397};
397};
398struct fwohci_trailer{
398
399struct fwohci_trailer {
399#if BYTE_ORDER == BIG_ENDIAN
400 uint32_t stat:16,
400#if BYTE_ORDER == BIG_ENDIAN
401 uint32_t stat:16,
401 time:16;
402 time:16;
402#else
403 uint32_t time:16,
403#else
404 uint32_t time:16,
404 stat:16;
405 stat:16;
405#endif
406};
407
408#define OHCI_CNTL_CYCSRC (0x1 << 22)
409#define OHCI_CNTL_CYCMTR (0x1 << 21)
410#define OHCI_CNTL_CYCTIMER (0x1 << 20)
411#define OHCI_CNTL_PHYPKT (0x1 << 10)
412#define OHCI_CNTL_SID (0x1 << 9)
413
414/*
406#endif
407};
408
409#define OHCI_CNTL_CYCSRC (0x1 << 22)
410#define OHCI_CNTL_CYCMTR (0x1 << 21)
411#define OHCI_CNTL_CYCTIMER (0x1 << 20)
412#define OHCI_CNTL_PHYPKT (0x1 << 10)
413#define OHCI_CNTL_SID (0x1 << 9)
414
415/*
415 * defined in OHCI 1.1
416 * defined in OHCI 1.1
416 * chapter 6.1
417 */
418#define OHCI_INT_DMA_ATRQ (0x1 << 0)
419#define OHCI_INT_DMA_ATRS (0x1 << 1)
420#define OHCI_INT_DMA_ARRQ (0x1 << 2)
421#define OHCI_INT_DMA_ARRS (0x1 << 3)
422#define OHCI_INT_DMA_PRRQ (0x1 << 4)
423#define OHCI_INT_DMA_PRRS (0x1 << 5)

--- 24 unchanged lines hidden --- 		417 * chapter 6.1
418 */
419#define OHCI_INT_DMA_ATRQ (0x1 << 0)
420#define OHCI_INT_DMA_ATRS (0x1 << 1)
421#define OHCI_INT_DMA_ARRQ (0x1 << 2)
422#define OHCI_INT_DMA_ARRS (0x1 << 3)
423#define OHCI_INT_DMA_PRRQ (0x1 << 4)
424#define OHCI_INT_DMA_PRRS (0x1 << 5)

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