| fwohcireg.h (119155) | fwohcireg.h (120660) |
|---|---|
| 1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * | 1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * |
| 34 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 119155 2003-08-20 03:11:37Z simokawa $ | 34 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 120660 2003-10-02 04:06:56Z simokawa $ |
| 35 * 36 */ 37#define PCI_CBMEM 0x10 38 39#define FW_VENDORID_NEC 0x1033 40#define FW_VENDORID_TI 0x104c 41#define FW_VENDORID_SONY 0x104d 42#define FW_VENDORID_VIA 0x1106 --- 28 unchanged lines hidden (view full) --- 71#define FW_OHCI_BASE_REG 0x10 72 73#define OHCI_DMA_ITCH 0x20 74#define OHCI_DMA_IRCH 0x20 75 76#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 77 78 | 35 * 36 */ 37#define PCI_CBMEM 0x10 38 39#define FW_VENDORID_NEC 0x1033 40#define FW_VENDORID_TI 0x104c 41#define FW_VENDORID_SONY 0x104d 42#define FW_VENDORID_VIA 0x1106 --- 28 unchanged lines hidden (view full) --- 71#define FW_OHCI_BASE_REG 0x10 72 73#define OHCI_DMA_ITCH 0x20 74#define OHCI_DMA_IRCH 0x20 75 76#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 77 78 |
| 79typedef volatile u_int32_t fwohcireg_t; | 79typedef u_int32_t fwohcireg_t; |
| 80 81/* for PCI */ 82#if BYTE_ORDER == BIG_ENDIAN 83#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) 84#define FWOHCI_DMA_READ(x) le32toh(x) 85#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) 86#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) 87#else 88#define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) 89#define FWOHCI_DMA_READ(x) (x) 90#define FWOHCI_DMA_SET(x, y) ((x) |= (y)) 91#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) 92#endif 93 94struct fwohcidb { 95 union { 96 struct { | 80 81/* for PCI */ 82#if BYTE_ORDER == BIG_ENDIAN 83#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) 84#define FWOHCI_DMA_READ(x) le32toh(x) 85#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) 86#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) 87#else 88#define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) 89#define FWOHCI_DMA_READ(x) (x) 90#define FWOHCI_DMA_SET(x, y) ((x) |= (y)) 91#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) 92#endif 93 94struct fwohcidb { 95 union { 96 struct { |
| 97 volatile u_int32_t cmd; 98 volatile u_int32_t addr; 99 volatile u_int32_t depend; 100 volatile u_int32_t res; | 97 u_int32_t cmd; 98 u_int32_t addr; 99 u_int32_t depend; 100 u_int32_t res; |
| 101 } desc; | 101 } desc; |
| 102 volatile u_int32_t immed[4]; | 102 u_int32_t immed[4]; |
| 103 } db; 104#define OHCI_STATUS_SHIFT 16 105#define OHCI_COUNT_MASK 0xffff 106#define OHCI_OUTPUT_MORE (0 << 28) 107#define OHCI_OUTPUT_LAST (1 << 28) 108#define OHCI_INPUT_MORE (2 << 28) 109#define OHCI_INPUT_LAST (3 << 28) 110#define OHCI_STORE_QUAD (4 << 28) --- 201 unchanged lines hidden (view full) --- 312 /* 0x410, 0x404, 0x408, 0x40c */ 313 314 struct ohci_dma dma_irch[0x20]; 315}; 316 317struct fwohcidb_tr{ 318 STAILQ_ENTRY(fwohcidb_tr) link; 319 struct fw_xfer *xfer; | 103 } db; 104#define OHCI_STATUS_SHIFT 16 105#define OHCI_COUNT_MASK 0xffff 106#define OHCI_OUTPUT_MORE (0 << 28) 107#define OHCI_OUTPUT_LAST (1 << 28) 108#define OHCI_INPUT_MORE (2 << 28) 109#define OHCI_INPUT_LAST (3 << 28) 110#define OHCI_STORE_QUAD (4 << 28) --- 201 unchanged lines hidden (view full) --- 312 /* 0x410, 0x404, 0x408, 0x40c */ 313 314 struct ohci_dma dma_irch[0x20]; 315}; 316 317struct fwohcidb_tr{ 318 STAILQ_ENTRY(fwohcidb_tr) link; 319 struct fw_xfer *xfer; |
| 320 volatile struct fwohcidb *db; | 320 struct fwohcidb *db; |
| 321 bus_dmamap_t dma_map; 322 caddr_t buf; 323 bus_addr_t bus_addr; 324 int dbcnt; 325}; 326 327/* 328 * OHCI info structure. --- 101 unchanged lines hidden --- | 321 bus_dmamap_t dma_map; 322 caddr_t buf; 323 bus_addr_t bus_addr; 324 int dbcnt; 325}; 326 327/* 328 * OHCI info structure. --- 101 unchanged lines hidden --- |