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fwohci.c (178915) fwohci.c (187993)
1/*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
1/*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 178915 2008-05-10 13:40:42Z simokawa $
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 187993 2009-02-01 23:28:52Z sbruno $
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

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998 for (i = 2; i < db_tr->dbcnt; i++)
999 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1000 OHCI_OUTPUT_MORE);
1001#endif
1002 }
1003 if (maxdesc < db_tr->dbcnt) {
1004 maxdesc = db_tr->dbcnt;
1005 if (firewire_debug)
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

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998 for (i = 2; i < db_tr->dbcnt; i++)
999 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1000 OHCI_OUTPUT_MORE);
1001#endif
1002 }
1003 if (maxdesc < db_tr->dbcnt) {
1004 maxdesc = db_tr->dbcnt;
1005 if (firewire_debug)
1006 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
1006 device_printf(sc->fc.dev, "%s: maxdesc %d\n", __func__, maxdesc);
1007 }
1008 /* last db */
1009 LAST_DB(db_tr, db);
1010 FWOHCI_DMA_SET(db->db.desc.cmd,
1011 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1012 FWOHCI_DMA_WRITE(db->db.desc.depend,
1013 STAILQ_NEXT(db_tr, link)->bus_addr);
1014

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1837}
1838#endif
1839static void
1840fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1841{
1842 struct firewire_comm *fc = (struct firewire_comm *)sc;
1843 uint32_t node_id, plen;
1844
1007 }
1008 /* last db */
1009 LAST_DB(db_tr, db);
1010 FWOHCI_DMA_SET(db->db.desc.cmd,
1011 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1012 FWOHCI_DMA_WRITE(db->db.desc.depend,
1013 STAILQ_NEXT(db_tr, link)->bus_addr);
1014

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1837}
1838#endif
1839static void
1840fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1841{
1842 struct firewire_comm *fc = (struct firewire_comm *)sc;
1843 uint32_t node_id, plen;
1844
1845 FW_GLOCK_ASSERT(fc);
1845 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1846 fc->status = FWBUSRESET;
1847 /* Disable bus reset interrupt until sid recv. */
1848 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1849
1850 device_printf(fc->dev, "BUS reset\n");
1851 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1852 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);

--- 26 unchanged lines hidden (view full) ---

1879 /*
1880 * Checking whether the node is root or not. If root, turn on
1881 * cycle master.
1882 */
1883 node_id = OREAD(sc, FWOHCI_NODEID);
1884 plen = OREAD(sc, OHCI_SID_CNT);
1885
1886 fc->nodeid = node_id & 0x3f;
1846 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1847 fc->status = FWBUSRESET;
1848 /* Disable bus reset interrupt until sid recv. */
1849 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1850
1851 device_printf(fc->dev, "BUS reset\n");
1852 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1853 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);

--- 26 unchanged lines hidden (view full) ---

1880 /*
1881 * Checking whether the node is root or not. If root, turn on
1882 * cycle master.
1883 */
1884 node_id = OREAD(sc, FWOHCI_NODEID);
1885 plen = OREAD(sc, OHCI_SID_CNT);
1886
1887 fc->nodeid = node_id & 0x3f;
1887 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1888 node_id, (plen >> 16) & 0xff);
1888 device_printf(fc->dev, "node_id=0x%08x, SelfID Count=%d, ",
1889 fc->nodeid, (plen >> 16) & 0xff);
1889 if (!(node_id & OHCI_NODE_VALID)) {
1890 printf("Bus reset failure\n");
1891 goto sidout;
1892 }
1893
1894 /* cycle timer */
1895 sc->cycle_lost = 0;
1896 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST);

--- 94 unchanged lines hidden (view full) ---

1991 return;
1992}
1993
1994static void
1995fwohci_task_busreset(void *arg, int pending)
1996{
1997 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1998
1890 if (!(node_id & OHCI_NODE_VALID)) {
1891 printf("Bus reset failure\n");
1892 goto sidout;
1893 }
1894
1895 /* cycle timer */
1896 sc->cycle_lost = 0;
1897 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST);

--- 94 unchanged lines hidden (view full) ---

1992 return;
1993}
1994
1995static void
1996fwohci_task_busreset(void *arg, int pending)
1997{
1998 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1999
2000 FW_GLOCK(&sc->fc);
1999 fw_busreset(&sc->fc, FWBUSRESET);
2000 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2001 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2001 fw_busreset(&sc->fc, FWBUSRESET);
2002 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2003 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2004 FW_GUNLOCK(&sc->fc);
2002}
2003
2004static void
2005fwohci_task_sid(void *arg, int pending)
2006{
2007 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2008 struct firewire_comm *fc = &sc->fc;
2009 uint32_t *buf;
2010 int i, plen;
2011
2012
2005}
2006
2007static void
2008fwohci_task_sid(void *arg, int pending)
2009{
2010 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2011 struct firewire_comm *fc = &sc->fc;
2012 uint32_t *buf;
2013 int i, plen;
2014
2015
2016 /*
2017 * We really should have locking
2018 * here. Not sure why it's not
2019 */
2013 plen = OREAD(sc, OHCI_SID_CNT);
2014
2015 if (plen & OHCI_SID_ERR) {
2016 device_printf(fc->dev, "SID Error\n");
2017 return;
2018 }
2019 plen &= OHCI_SID_CNT_MASK;
2020 if (plen < 4 || plen > OHCI_SIDSIZE) {
2021 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2022 return;
2023 }
2024 plen -= 4; /* chop control info */
2025 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2026 if (buf == NULL) {
2027 device_printf(fc->dev, "malloc failed\n");
2028 return;
2029 }
2030 for (i = 0; i < plen / 4; i ++)
2031 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2020 plen = OREAD(sc, OHCI_SID_CNT);
2021
2022 if (plen & OHCI_SID_ERR) {
2023 device_printf(fc->dev, "SID Error\n");
2024 return;
2025 }
2026 plen &= OHCI_SID_CNT_MASK;
2027 if (plen < 4 || plen > OHCI_SIDSIZE) {
2028 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2029 return;
2030 }
2031 plen -= 4; /* chop control info */
2032 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2033 if (buf == NULL) {
2034 device_printf(fc->dev, "malloc failed\n");
2035 return;
2036 }
2037 for (i = 0; i < plen / 4; i ++)
2038 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2032#if 1 /* XXX needed?? */
2039
2033 /* pending all pre-bus_reset packets */
2034 fwohci_txd(sc, &sc->atrq);
2035 fwohci_txd(sc, &sc->atrs);
2036 fwohci_arcv(sc, &sc->arrs, -1);
2037 fwohci_arcv(sc, &sc->arrq, -1);
2038 fw_drain_txq(fc);
2040 /* pending all pre-bus_reset packets */
2041 fwohci_txd(sc, &sc->atrq);
2042 fwohci_txd(sc, &sc->atrs);
2043 fwohci_arcv(sc, &sc->arrs, -1);
2044 fwohci_arcv(sc, &sc->arrq, -1);
2045 fw_drain_txq(fc);
2039#endif
2040 fw_sidrcv(fc, buf, plen);
2041 free(buf, M_FW);
2042}
2043
2044static void
2045fwohci_task_dma(void *arg, int pending)
2046{
2047 struct fwohci_softc *sc = (struct fwohci_softc *)arg;

--- 8 unchanged lines hidden (view full) ---

2056 goto again;
2057}
2058
2059static int
2060fwohci_check_stat(struct fwohci_softc *sc)
2061{
2062 uint32_t stat, irstat, itstat;
2063
2046 fw_sidrcv(fc, buf, plen);
2047 free(buf, M_FW);
2048}
2049
2050static void
2051fwohci_task_dma(void *arg, int pending)
2052{
2053 struct fwohci_softc *sc = (struct fwohci_softc *)arg;

--- 8 unchanged lines hidden (view full) ---

2062 goto again;
2063}
2064
2065static int
2066fwohci_check_stat(struct fwohci_softc *sc)
2067{
2068 uint32_t stat, irstat, itstat;
2069
2070 FW_GLOCK_ASSERT(&sc->fc);
2064 stat = OREAD(sc, FWOHCI_INTSTAT);
2065 if (stat == 0xffffffff) {
2066 device_printf(sc->fc.dev,
2067 "device physically ejected?\n");
2068 return (FILTER_STRAY);
2069 }
2070 if (stat)
2071 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);

--- 13 unchanged lines hidden (view full) ---

2085 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2086 atomic_set_int(&sc->itstat, itstat);
2087 }
2088
2089 fwohci_intr_core(sc, stat, -1);
2090 return (FILTER_HANDLED);
2091}
2092
2071 stat = OREAD(sc, FWOHCI_INTSTAT);
2072 if (stat == 0xffffffff) {
2073 device_printf(sc->fc.dev,
2074 "device physically ejected?\n");
2075 return (FILTER_STRAY);
2076 }
2077 if (stat)
2078 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);

--- 13 unchanged lines hidden (view full) ---

2092 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2093 atomic_set_int(&sc->itstat, itstat);
2094 }
2095
2096 fwohci_intr_core(sc, stat, -1);
2097 return (FILTER_HANDLED);
2098}
2099
2093int
2094fwohci_filt(void *arg)
2100void
2101fwohci_intr(void *arg)
2095{
2096 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2097
2102{
2103 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2104
2098 if (!(sc->intmask & OHCI_INT_EN)) {
2099 /* polling mode */
2100 return (FILTER_STRAY);
2101 }
2102 return (fwohci_check_stat(sc));
2105 FW_GLOCK(&sc->fc);
2106 fwohci_check_stat(sc);
2107 FW_GUNLOCK(&sc->fc);
2103}
2104
2105void
2108}
2109
2110void
2106fwohci_intr(void *arg)
2107{
2108 fwohci_filt(arg);
2109}
2110
2111void
2112fwohci_poll(struct firewire_comm *fc, int quick, int count)
2113{
2114 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2111fwohci_poll(struct firewire_comm *fc, int quick, int count)
2112{
2113 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2114
2115 FW_GLOCK(fc);
2115 fwohci_check_stat(sc);
2116 fwohci_check_stat(sc);
2117 FW_GUNLOCK(fc);
2116}
2117
2118static void
2119fwohci_set_intr(struct firewire_comm *fc, int enable)
2120{
2121 struct fwohci_softc *sc;
2122
2123 sc = (struct fwohci_softc *)fc;

--- 337 unchanged lines hidden (view full) ---

2461fwohci_ibr(struct firewire_comm *fc)
2462{
2463 struct fwohci_softc *sc;
2464 uint32_t fun;
2465
2466 device_printf(fc->dev, "Initiate bus reset\n");
2467 sc = (struct fwohci_softc *)fc;
2468
2118}
2119
2120static void
2121fwohci_set_intr(struct firewire_comm *fc, int enable)
2122{
2123 struct fwohci_softc *sc;
2124
2125 sc = (struct fwohci_softc *)fc;

--- 337 unchanged lines hidden (view full) ---

2463fwohci_ibr(struct firewire_comm *fc)
2464{
2465 struct fwohci_softc *sc;
2466 uint32_t fun;
2467
2468 device_printf(fc->dev, "Initiate bus reset\n");
2469 sc = (struct fwohci_softc *)fc;
2470
2471 FW_GLOCK(fc);
2469 /*
2470 * Make sure our cached values from the config rom are
2471 * initialised.
2472 */
2473 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2474 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2475
2476 /*

--- 4 unchanged lines hidden (view full) ---

2481 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2482 fun |= FW_PHY_IBR | FW_PHY_RHB;
2483 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2484#else /* Short bus reset */
2485 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2486 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2487 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2488#endif
2472 /*
2473 * Make sure our cached values from the config rom are
2474 * initialised.
2475 */
2476 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2477 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2478
2479 /*

--- 4 unchanged lines hidden (view full) ---

2484 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2485 fun |= FW_PHY_IBR | FW_PHY_RHB;
2486 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2487#else /* Short bus reset */
2488 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2489 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2490 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2491#endif
2492 FW_GUNLOCK(fc);
2489}
2490
2491void
2492fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2493{
2494 struct fwohcidb_tr *db_tr, *fdb_tr;
2495 struct fwohci_dbch *dbch;
2496 struct fwohcidb *db;

--- 486 unchanged lines hidden --- 		2493}
2494
2495void
2496fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2497{
2498 struct fwohcidb_tr *db_tr, *fdb_tr;
2499 struct fwohci_dbch *dbch;
2500 struct fwohcidb *db;

--- 486 unchanged lines hidden ---