| fwohci.c (170427) | fwohci.c (178911) |
|---|---|
| 1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * | 1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * |
| 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 170427 2007-06-08 09:04:30Z simokawa $ | 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 178911 2008-05-10 09:22:06Z simokawa $ |
| 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 --- 1697 unchanged lines hidden (view full) --- 1740 return err; 1741} 1742 1743int 1744fwohci_stop(struct fwohci_softc *sc, device_t dev) 1745{ 1746 u_int i; 1747 | 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 --- 1697 unchanged lines hidden (view full) --- 1740 return err; 1741} 1742 1743int 1744fwohci_stop(struct fwohci_softc *sc, device_t dev) 1745{ 1746 u_int i; 1747 |
| 1748 fwohci_set_intr(&sc->fc, 0); 1749 |
|
| 1748/* Now stopping all DMA channel */ 1749 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1750 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1751 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1752 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1753 1754 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1755 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); --- 840 unchanged lines hidden (view full) --- 2596 struct fwohcidb *db = db_tr->db; 2597 struct fw_xferq *ir; 2598 int i, ldesc; 2599 bus_addr_t dbuf[2]; 2600 int dsiz[2]; 2601 2602 ir = &dbch->xferq; 2603 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { | 1750/* Now stopping all DMA channel */ 1751 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1752 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1753 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1754 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1755 1756 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1757 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); --- 840 unchanged lines hidden (view full) --- 2598 struct fwohcidb *db = db_tr->db; 2599 struct fw_xferq *ir; 2600 int i, ldesc; 2601 bus_addr_t dbuf[2]; 2602 int dsiz[2]; 2603 2604 ir = &dbch->xferq; 2605 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { |
| 2604 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2605 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2606 if (db_tr->buf == NULL) 2607 return(ENOMEM); | 2606 if (db_tr->buf == NULL) { 2607 db_tr->buf = fwdma_malloc_size(dbch->dmat, 2608 &db_tr->dma_map, ir->psize, &dbuf[0], 2609 BUS_DMA_NOWAIT); 2610 if (db_tr->buf == NULL) 2611 return(ENOMEM); 2612 } |
| 2608 db_tr->dbcnt = 1; 2609 dsiz[0] = ir->psize; 2610 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2611 BUS_DMASYNC_PREREAD); 2612 } else { 2613 db_tr->dbcnt = 0; 2614 if (dummy_dma != NULL) { 2615 dsiz[db_tr->dbcnt] = sizeof(uint32_t); --- 365 unchanged lines hidden --- | 2613 db_tr->dbcnt = 1; 2614 dsiz[0] = ir->psize; 2615 bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2616 BUS_DMASYNC_PREREAD); 2617 } else { 2618 db_tr->dbcnt = 0; 2619 if (dummy_dma != NULL) { 2620 dsiz[db_tr->dbcnt] = sizeof(uint32_t); --- 365 unchanged lines hidden --- |