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fwohci.c (169132) fwohci.c (170374)
1/*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
1/*-
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 169132 2007-04-30 14:06:30Z simokawa $
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 170374 2007-06-06 14:31:36Z simokawa $
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

--- 4 unchanged lines hidden (view full) ---

47#include <sys/mbuf.h>
48#include <sys/malloc.h>
49#include <sys/sockio.h>
50#include <sys/sysctl.h>
51#include <sys/bus.h>
52#include <sys/kernel.h>
53#include <sys/conf.h>
54#include <sys/endian.h>
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

--- 4 unchanged lines hidden (view full) ---

47#include <sys/mbuf.h>
48#include <sys/malloc.h>
49#include <sys/sockio.h>
50#include <sys/sysctl.h>
51#include <sys/bus.h>
52#include <sys/kernel.h>
53#include <sys/conf.h>
54#include <sys/endian.h>
55#include <sys/kdb.h>
55
56#include <machine/bus.h>
57
58#if defined(__DragonFly__) || __FreeBSD_version < 500000
59#include <machine/clock.h> /* for DELAY() */
60#endif
61
62#ifdef __DragonFly__

--- 22 unchanged lines hidden (view full) ---

85static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
86 "STOR","LOAD","NOP ","STOP",};
87
88static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
89 "UNDEF","REG","SYS","DEV"};
90static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
91char fwohcicode[32][0x20]={
92 "No stat","Undef","long","miss Ack err",
56
57#include <machine/bus.h>
58
59#if defined(__DragonFly__) || __FreeBSD_version < 500000
60#include <machine/clock.h> /* for DELAY() */
61#endif
62
63#ifdef __DragonFly__

--- 22 unchanged lines hidden (view full) ---

86static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
87 "STOR","LOAD","NOP ","STOP",};
88
89static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
90 "UNDEF","REG","SYS","DEV"};
91static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
92char fwohcicode[32][0x20]={
93 "No stat","Undef","long","miss Ack err",
93 "underrun","overrun","desc err", "data read err",
94 "FIFO underrun","FIFO overrun","desc err", "data read err",
94 "data write err","bus reset","timeout","tcode err",
95 "Undef","Undef","unknown event","flushed",
96 "Undef","ack complete","ack pend","Undef",
97 "ack busy_X","ack busy_A","ack busy_B","Undef",
98 "Undef","Undef","Undef","ack tardy",
99 "Undef","ack data_err","ack type_err",""};
100
101#define MAX_SPEED 3
102extern char *linkspeed[];
103uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
104
105static struct tcode_info tinfo[] = {
95 "data write err","bus reset","timeout","tcode err",
96 "Undef","Undef","unknown event","flushed",
97 "Undef","ack complete","ack pend","Undef",
98 "ack busy_X","ack busy_A","ack busy_B","Undef",
99 "Undef","Undef","Undef","ack tardy",
100 "Undef","ack data_err","ack type_err",""};
101
102#define MAX_SPEED 3
103extern char *linkspeed[];
104uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
105
106static struct tcode_info tinfo[] = {
106/* hdr_len block flag*/
107/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
108/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
109/* 2 WRES */ {12, FWTI_RES},
110/* 3 XXX */ { 0, 0},
111/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
112/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
113/* 6 RRESQ */ {16, FWTI_RES},
114/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
115/* 8 CYCS */ { 0, 0},
116/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
117/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
118/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
119/* c XXX */ { 0, 0},
120/* d XXX */ { 0, 0},
121/* e PHY */ {12, FWTI_REQ},
122/* f XXX */ { 0, 0}
107/* hdr_len block flag valid_response */
108/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_WRES},
109/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_WRES},
110/* 2 WRES */ {12, FWTI_RES, 0xff},
111/* 3 XXX */ { 0, 0, 0xff},
112/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESQ},
113/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL, FWTCODE_RRESB},
114/* 6 RRESQ */ {16, FWTI_RES, 0xff},
115/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff},
116/* 8 CYCS */ { 0, 0, 0xff},
117/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY, FWTCODE_LRES},
118/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR, 0xff},
119/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY, 0xff},
120/* c XXX */ { 0, 0, 0xff},
121/* d XXX */ { 0, 0, 0xff},
122/* e PHY */ {12, FWTI_REQ, 0xff},
123/* f XXX */ { 0, 0, 0xff}
123};
124
125#define OHCI_WRITE_SIGMASK 0xffff0000
126#define OHCI_READ_SIGMASK 0xffff0000
127
128#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
129#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
130

--- 23 unchanged lines hidden (view full) ---

154static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
155static void dump_db (struct fwohci_softc *, uint32_t);
156static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
157static void dump_dma (struct fwohci_softc *, uint32_t);
158static uint32_t fwohci_cyctimer (struct firewire_comm *);
159static void fwohci_rbuf_update (struct fwohci_softc *, int);
160static void fwohci_tbuf_update (struct fwohci_softc *, int);
161void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
124};
125
126#define OHCI_WRITE_SIGMASK 0xffff0000
127#define OHCI_READ_SIGMASK 0xffff0000
128
129#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
130#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
131

--- 23 unchanged lines hidden (view full) ---

155static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
156static void dump_db (struct fwohci_softc *, uint32_t);
157static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
158static void dump_dma (struct fwohci_softc *, uint32_t);
159static uint32_t fwohci_cyctimer (struct firewire_comm *);
160static void fwohci_rbuf_update (struct fwohci_softc *, int);
161static void fwohci_tbuf_update (struct fwohci_softc *, int);
162void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
162#if FWOHCI_TASKQUEUE
163static void fwohci_complete(void *, int);
164#endif
163static void fwohci_task_busreset(void *, int);
164static void fwohci_task_sid(void *, int);
165static void fwohci_task_dma(void *, int);
165
166/*
167 * memory allocated for DMA programs
168 */
169#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
170
171#define NDB FWMAXQUEUE
172

--- 86 unchanged lines hidden (view full) ---

259#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
260#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
261
262d_ioctl_t fwohci_ioctl;
263
264/*
265 * Communication with PHY device
266 */
166
167/*
168 * memory allocated for DMA programs
169 */
170#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
171
172#define NDB FWMAXQUEUE
173

--- 86 unchanged lines hidden (view full) ---

260#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
261#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
262
263d_ioctl_t fwohci_ioctl;
264
265/*
266 * Communication with PHY device
267 */
268/* XXX need lock for phy access */
267static uint32_t
268fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
269{
270 uint32_t fun;
271
272 addr &= 0xf;
273 data &= 0xff;
274

--- 309 unchanged lines hidden (view full) ---

584 }
585 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
586 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
587 db_tr->xfer = NULL;
588 }
589
590
591 /* Enable interrupts */
269static uint32_t
270fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
271{
272 uint32_t fun;
273
274 addr &= 0xf;
275 data &= 0xff;
276

--- 309 unchanged lines hidden (view full) ---

586 }
587 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
588 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
589 db_tr->xfer = NULL;
590 }
591
592
593 /* Enable interrupts */
592 OWRITE(sc, FWOHCI_INTMASK,
593 OHCI_INT_ERR | OHCI_INT_PHY_SID
594 sc->intmask = (OHCI_INT_ERR | OHCI_INT_PHY_SID
594 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
595 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
596 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
595 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
596 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
597 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
598 sc->intmask |= OHCI_INT_DMA_IR | OHCI_INT_DMA_IT;
599 sc->intmask |= OHCI_INT_CYC_LOST | OHCI_INT_PHY_INT;
600 OWRITE(sc, FWOHCI_INTMASK, sc->intmask);
597 fwohci_set_intr(&sc->fc, 1);
598
599}
600
601int
602fwohci_init(struct fwohci_softc *sc, device_t dev)
603{
604 int i, mver;
605 uint32_t reg;
606 uint8_t ui[8];
607
601 fwohci_set_intr(&sc->fc, 1);
602
603}
604
605int
606fwohci_init(struct fwohci_softc *sc, device_t dev)
607{
608 int i, mver;
609 uint32_t reg;
610 uint8_t ui[8];
611
608#if FWOHCI_TASKQUEUE
609 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
610#endif
611
612/* OHCI version */
613 reg = OREAD(sc, OHCI_VERSION);
614 mver = (reg >> 16) & 0xff;
615 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
616 mver, reg & 0xff, (reg>>24) & 1);
617 if (mver < 1 || mver > 9) {
618 device_printf(dev, "invalid OHCI version\n");
619 return (ENXIO);

--- 136 unchanged lines hidden (view full) ---

756#endif
757 sc->fc.itx_post = NULL;
758 sc->fc.timeout = fwohci_timeout;
759 sc->fc.poll = fwohci_poll;
760 sc->fc.set_intr = fwohci_set_intr;
761
762 sc->intmask = sc->irstat = sc->itstat = 0;
763
612/* OHCI version */
613 reg = OREAD(sc, OHCI_VERSION);
614 mver = (reg >> 16) & 0xff;
615 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
616 mver, reg & 0xff, (reg>>24) & 1);
617 if (mver < 1 || mver > 9) {
618 device_printf(dev, "invalid OHCI version\n");
619 return (ENXIO);

--- 136 unchanged lines hidden (view full) ---

756#endif
757 sc->fc.itx_post = NULL;
758 sc->fc.timeout = fwohci_timeout;
759 sc->fc.poll = fwohci_poll;
760 sc->fc.set_intr = fwohci_set_intr;
761
762 sc->intmask = sc->irstat = sc->itstat = 0;
763
764 /* Init task queue */
765 sc->fc.taskqueue = taskqueue_create_fast("fw_taskq", M_WAITOK,
766 taskqueue_thread_enqueue, &sc->fc.taskqueue);
767 taskqueue_start_threads(&sc->fc.taskqueue, 1, PI_NET, "fw%d_taskq",
768 device_get_unit(dev));
769 TASK_INIT(&sc->fwohci_task_busreset, 2, fwohci_task_busreset, sc);
770 TASK_INIT(&sc->fwohci_task_sid, 1, fwohci_task_sid, sc);
771 TASK_INIT(&sc->fwohci_task_dma, 0, fwohci_task_dma, sc);
772
764 fw_init(&sc->fc);
765 fwohci_reset(sc, dev);
766
767 return 0;
768}
769
770void
771fwohci_timeout(void *arg)

--- 25 unchanged lines hidden (view full) ---

797
798 fwohci_db_free(&sc->atrq);
799 fwohci_db_free(&sc->atrs);
800
801 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
802 fwohci_db_free(&sc->it[i]);
803 fwohci_db_free(&sc->ir[i]);
804 }
773 fw_init(&sc->fc);
774 fwohci_reset(sc, dev);
775
776 return 0;
777}
778
779void
780fwohci_timeout(void *arg)

--- 25 unchanged lines hidden (view full) ---

806
807 fwohci_db_free(&sc->atrq);
808 fwohci_db_free(&sc->atrs);
809
810 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
811 fwohci_db_free(&sc->it[i]);
812 fwohci_db_free(&sc->ir[i]);
813 }
814 if (sc->fc.taskqueue != NULL) {
815 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_busreset);
816 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_sid);
817 taskqueue_drain(sc->fc.taskqueue, &sc->fwohci_task_dma);
818 taskqueue_drain(sc->fc.taskqueue, &sc->fc.task_timeout);
819 taskqueue_free(sc->fc.taskqueue);
820 sc->fc.taskqueue = NULL;
821 }
805
806 return 0;
807}
808
809#define LAST_DB(dbtr, db) do { \
810 struct fwohcidb_tr *_dbtr = (dbtr); \
811 int _cnt = _dbtr->dbcnt; \
812 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \

--- 42 unchanged lines hidden (view full) ---

855 struct fw_pkt *fp;
856 struct fwohci_txpkthdr *ohcifp;
857 struct fwohcidb_tr *db_tr;
858 struct fwohcidb *db;
859 uint32_t *ld;
860 struct tcode_info *info;
861 static int maxdesc=0;
862
822
823 return 0;
824}
825
826#define LAST_DB(dbtr, db) do { \
827 struct fwohcidb_tr *_dbtr = (dbtr); \
828 int _cnt = _dbtr->dbcnt; \
829 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \

--- 42 unchanged lines hidden (view full) ---

872 struct fw_pkt *fp;
873 struct fwohci_txpkthdr *ohcifp;
874 struct fwohcidb_tr *db_tr;
875 struct fwohcidb *db;
876 uint32_t *ld;
877 struct tcode_info *info;
878 static int maxdesc=0;
879
880 FW_GLOCK_ASSERT(&sc->fc);
881
863 if(&sc->atrq == dbch){
864 off = OHCI_ATQOFF;
865 }else if(&sc->atrs == dbch){
866 off = OHCI_ATSOFF;
867 }else{
868 return;
869 }
870
871 if (dbch->flags & FWOHCI_DBCH_FULL)
872 return;
873
874 s = splfw();
875 db_tr = dbch->top;
876txloop:
877 xfer = STAILQ_FIRST(&dbch->xferq.q);
878 if(xfer == NULL){
879 goto kick;
880 }
882 if(&sc->atrq == dbch){
883 off = OHCI_ATQOFF;
884 }else if(&sc->atrs == dbch){
885 off = OHCI_ATSOFF;
886 }else{
887 return;
888 }
889
890 if (dbch->flags & FWOHCI_DBCH_FULL)
891 return;
892
893 s = splfw();
894 db_tr = dbch->top;
895txloop:
896 xfer = STAILQ_FIRST(&dbch->xferq.q);
897 if(xfer == NULL){
898 goto kick;
899 }
900#if 0
881 if(dbch->xferq.queued == 0 ){
882 device_printf(sc->fc.dev, "TX queue empty\n");
883 }
901 if(dbch->xferq.queued == 0 ){
902 device_printf(sc->fc.dev, "TX queue empty\n");
903 }
904#endif
884 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
885 db_tr->xfer = xfer;
905 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
906 db_tr->xfer = xfer;
886 xfer->state = FWXF_START;
907 xfer->flag = FWXF_START;
887
888 fp = &xfer->send.hdr;
889 tcode = fp->mode.common.tcode;
890
891 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
892 info = &tinfo[tcode];
893 hdr_len = pl_off = info->hdr_len;
894

--- 93 unchanged lines hidden (view full) ---

988 STAILQ_NEXT(db_tr, link)->bus_addr);
989
990 if(fsegment == -1 )
991 fsegment = db_tr->dbcnt;
992 if (dbch->pdb_tr != NULL) {
993 LAST_DB(dbch->pdb_tr, db);
994 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
995 }
908
909 fp = &xfer->send.hdr;
910 tcode = fp->mode.common.tcode;
911
912 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
913 info = &tinfo[tcode];
914 hdr_len = pl_off = info->hdr_len;
915

--- 93 unchanged lines hidden (view full) ---

1009 STAILQ_NEXT(db_tr, link)->bus_addr);
1010
1011 if(fsegment == -1 )
1012 fsegment = db_tr->dbcnt;
1013 if (dbch->pdb_tr != NULL) {
1014 LAST_DB(dbch->pdb_tr, db);
1015 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1016 }
1017 dbch->xferq.queued ++;
996 dbch->pdb_tr = db_tr;
997 db_tr = STAILQ_NEXT(db_tr, link);
998 if(db_tr != dbch->bottom){
999 goto txloop;
1000 } else {
1001 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1002 dbch->flags |= FWOHCI_DBCH_FULL;
1003 }

--- 17 unchanged lines hidden (view full) ---

1021 splx(s);
1022 return;
1023}
1024
1025static void
1026fwohci_start_atq(struct firewire_comm *fc)
1027{
1028 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1018 dbch->pdb_tr = db_tr;
1019 db_tr = STAILQ_NEXT(db_tr, link);
1020 if(db_tr != dbch->bottom){
1021 goto txloop;
1022 } else {
1023 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1024 dbch->flags |= FWOHCI_DBCH_FULL;
1025 }

--- 17 unchanged lines hidden (view full) ---

1043 splx(s);
1044 return;
1045}
1046
1047static void
1048fwohci_start_atq(struct firewire_comm *fc)
1049{
1050 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1051 FW_GLOCK(&sc->fc);
1029 fwohci_start( sc, &(sc->atrq));
1052 fwohci_start( sc, &(sc->atrq));
1053 FW_GUNLOCK(&sc->fc);
1030 return;
1031}
1032
1033static void
1034fwohci_start_ats(struct firewire_comm *fc)
1035{
1036 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1054 return;
1055}
1056
1057static void
1058fwohci_start_ats(struct firewire_comm *fc)
1059{
1060 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1061 FW_GLOCK(&sc->fc);
1037 fwohci_start( sc, &(sc->atrs));
1062 fwohci_start( sc, &(sc->atrs));
1063 FW_GUNLOCK(&sc->fc);
1038 return;
1039}
1040
1041void
1042fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1043{
1044 int s, ch, err = 0;
1045 struct fwohcidb_tr *tr;

--- 71 unchanged lines hidden (view full) ---

1117 default:
1118 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1119 stat, fwohcicode[stat]);
1120 err = EINVAL;
1121 break;
1122 }
1123 if (tr->xfer != NULL) {
1124 xfer = tr->xfer;
1064 return;
1065}
1066
1067void
1068fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1069{
1070 int s, ch, err = 0;
1071 struct fwohcidb_tr *tr;

--- 71 unchanged lines hidden (view full) ---

1143 default:
1144 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1145 stat, fwohcicode[stat]);
1146 err = EINVAL;
1147 break;
1148 }
1149 if (tr->xfer != NULL) {
1150 xfer = tr->xfer;
1125 if (xfer->state == FWXF_RCVD) {
1151 if (xfer->flag & FWXF_RCVD) {
1126#if 0
1127 if (firewire_debug)
1128 printf("already rcvd\n");
1129#endif
1130 fw_xfer_done(xfer);
1131 } else {
1152#if 0
1153 if (firewire_debug)
1154 printf("already rcvd\n");
1155#endif
1156 fw_xfer_done(xfer);
1157 } else {
1132 xfer->state = FWXF_SENT;
1158 xfer->flag = FWXF_SENT;
1133 if (err == EBUSY && fc->status != FWBUSRESET) {
1159 if (err == EBUSY && fc->status != FWBUSRESET) {
1134 xfer->state = FWXF_BUSY;
1160 xfer->flag = FWXF_BUSY;
1135 xfer->resp = err;
1136 xfer->recv.pay_len = 0;
1137 fw_xfer_done(xfer);
1138 } else if (stat != FWOHCIEV_ACKPEND) {
1139 if (stat != FWOHCIEV_ACKCOMPL)
1161 xfer->resp = err;
1162 xfer->recv.pay_len = 0;
1163 fw_xfer_done(xfer);
1164 } else if (stat != FWOHCIEV_ACKPEND) {
1165 if (stat != FWOHCIEV_ACKCOMPL)
1140 xfer->state = FWXF_SENTERR;
1166 xfer->flag = FWXF_SENTERR;
1141 xfer->resp = err;
1142 xfer->recv.pay_len = 0;
1143 fw_xfer_done(xfer);
1144 }
1145 }
1146 /*
1147 * The watchdog timer takes care of split
1148 * transcation timeout for ACKPEND case.
1149 */
1150 } else {
1151 printf("this shouldn't happen\n");
1152 }
1167 xfer->resp = err;
1168 xfer->recv.pay_len = 0;
1169 fw_xfer_done(xfer);
1170 }
1171 }
1172 /*
1173 * The watchdog timer takes care of split
1174 * transcation timeout for ACKPEND case.
1175 */
1176 } else {
1177 printf("this shouldn't happen\n");
1178 }
1179 FW_GLOCK(fc);
1153 dbch->xferq.queued --;
1180 dbch->xferq.queued --;
1181 FW_GUNLOCK(fc);
1154 tr->xfer = NULL;
1155
1156 packets ++;
1157 tr = STAILQ_NEXT(tr, link);
1158 dbch->bottom = tr;
1159 if (dbch->bottom == dbch->top) {
1160 /* we reaches the end of context program */
1161 if (firewire_debug && dbch->xferq.queued > 0)
1162 printf("queued > 0\n");
1163 break;
1164 }
1165 }
1166out:
1167 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1168 printf("make free slot\n");
1169 dbch->flags &= ~FWOHCI_DBCH_FULL;
1182 tr->xfer = NULL;
1183
1184 packets ++;
1185 tr = STAILQ_NEXT(tr, link);
1186 dbch->bottom = tr;
1187 if (dbch->bottom == dbch->top) {
1188 /* we reaches the end of context program */
1189 if (firewire_debug && dbch->xferq.queued > 0)
1190 printf("queued > 0\n");
1191 break;
1192 }
1193 }
1194out:
1195 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1196 printf("make free slot\n");
1197 dbch->flags &= ~FWOHCI_DBCH_FULL;
1198 FW_GLOCK(fc);
1170 fwohci_start(sc, dbch);
1199 fwohci_start(sc, dbch);
1200 FW_GUNLOCK(fc);
1171 }
1172 splx(s);
1173}
1174
1175static void
1176fwohci_db_free(struct fwohci_dbch *dbch)
1177{
1178 struct fwohcidb_tr *db_tr;

--- 37 unchanged lines hidden (view full) ---

1216 /*highaddr*/ BUS_SPACE_MAXADDR,
1217 /*filter*/NULL, /*filterarg*/NULL,
1218 /*maxsize*/ dbch->xferq.psize,
1219 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1220 /*maxsegsz*/ MAX_REQCOUNT,
1221 /*flags*/ 0,
1222#if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1223 /*lockfunc*/busdma_lock_mutex,
1201 }
1202 splx(s);
1203}
1204
1205static void
1206fwohci_db_free(struct fwohci_dbch *dbch)
1207{
1208 struct fwohcidb_tr *db_tr;

--- 37 unchanged lines hidden (view full) ---

1246 /*highaddr*/ BUS_SPACE_MAXADDR,
1247 /*filter*/NULL, /*filterarg*/NULL,
1248 /*maxsize*/ dbch->xferq.psize,
1249 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1250 /*maxsegsz*/ MAX_REQCOUNT,
1251 /*flags*/ 0,
1252#if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1253 /*lockfunc*/busdma_lock_mutex,
1224 /*lockarg*/&Giant,
1254 /*lockarg*/FW_GMTX(&sc->fc),
1225#endif
1226 &dbch->dmat))
1227 return;
1228
1229 /* allocate DB entries and attach one to each DMA channels */
1230 /* DB entry must start at 16 bytes bounary. */
1231 STAILQ_INIT(&dbch->db_trq);
1232 db_tr = (struct fwohcidb_tr *)

--- 270 unchanged lines hidden (view full) ---

1503 tag = (it->flag >> 6) & 3;
1504 ich = it->flag & 0x3f;
1505 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1506 dbch->ndb = it->bnpacket * it->bnchunk;
1507 dbch->ndesc = 3;
1508 fwohci_db_init(sc, dbch);
1509 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1510 return ENOMEM;
1255#endif
1256 &dbch->dmat))
1257 return;
1258
1259 /* allocate DB entries and attach one to each DMA channels */
1260 /* DB entry must start at 16 bytes bounary. */
1261 STAILQ_INIT(&dbch->db_trq);
1262 db_tr = (struct fwohcidb_tr *)

--- 270 unchanged lines hidden (view full) ---

1533 tag = (it->flag >> 6) & 3;
1534 ich = it->flag & 0x3f;
1535 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1536 dbch->ndb = it->bnpacket * it->bnchunk;
1537 dbch->ndesc = 3;
1538 fwohci_db_init(sc, dbch);
1539 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1540 return ENOMEM;
1541
1511 err = fwohci_tx_enable(sc, dbch);
1512 }
1513 if(err)
1514 return err;
1515
1516 ldesc = dbch->ndesc - 1;
1517 s = splfw();
1542 err = fwohci_tx_enable(sc, dbch);
1543 }
1544 if(err)
1545 return err;
1546
1547 ldesc = dbch->ndesc - 1;
1548 s = splfw();
1549 FW_GLOCK(fc);
1518 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1519 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1520 struct fwohcidb *db;
1521
1522 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1523 BUS_DMASYNC_PREWRITE);
1524 fwohci_txbufdb(sc, dmach, chunk);
1525 if (prev != NULL) {

--- 10 unchanged lines hidden (view full) ---

1536 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1537 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1538#endif
1539 }
1540 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1541 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1542 prev = chunk;
1543 }
1550 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1551 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1552 struct fwohcidb *db;
1553
1554 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1555 BUS_DMASYNC_PREWRITE);
1556 fwohci_txbufdb(sc, dmach, chunk);
1557 if (prev != NULL) {

--- 10 unchanged lines hidden (view full) ---

1568 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1569 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1570#endif
1571 }
1572 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1573 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1574 prev = chunk;
1575 }
1576 FW_GUNLOCK(fc);
1544 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1545 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1546 splx(s);
1547 stat = OREAD(sc, OHCI_ITCTL(dmach));
1548 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1549 printf("stat 0x%x\n", stat);
1550
1551 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))

--- 85 unchanged lines hidden (view full) ---

1637 first = STAILQ_FIRST(&ir->stfree);
1638 if (first == NULL) {
1639 device_printf(fc->dev, "IR DMA no free chunk\n");
1640 return 0;
1641 }
1642
1643 ldesc = dbch->ndesc - 1;
1644 s = splfw();
1577 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1578 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1579 splx(s);
1580 stat = OREAD(sc, OHCI_ITCTL(dmach));
1581 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1582 printf("stat 0x%x\n", stat);
1583
1584 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))

--- 85 unchanged lines hidden (view full) ---

1670 first = STAILQ_FIRST(&ir->stfree);
1671 if (first == NULL) {
1672 device_printf(fc->dev, "IR DMA no free chunk\n");
1673 return 0;
1674 }
1675
1676 ldesc = dbch->ndesc - 1;
1677 s = splfw();
1678 if ((ir->flag & FWXFERQ_HANDLER) == 0)
1679 FW_GLOCK(fc);
1645 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1646 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1647 struct fwohcidb *db;
1648
1649#if 1 /* XXX for if_fwe */
1650 if (chunk->mbuf != NULL) {
1651 db_tr = (struct fwohcidb_tr *)(chunk->start);
1652 db_tr->dbcnt = 1;

--- 11 unchanged lines hidden (view full) ---

1664 if (prev != NULL) {
1665 db = ((struct fwohcidb_tr *)(prev->end))->db;
1666 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1667 }
1668 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1669 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1670 prev = chunk;
1671 }
1680 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1681 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1682 struct fwohcidb *db;
1683
1684#if 1 /* XXX for if_fwe */
1685 if (chunk->mbuf != NULL) {
1686 db_tr = (struct fwohcidb_tr *)(chunk->start);
1687 db_tr->dbcnt = 1;

--- 11 unchanged lines hidden (view full) ---

1699 if (prev != NULL) {
1700 db = ((struct fwohcidb_tr *)(prev->end))->db;
1701 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1702 }
1703 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1704 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1705 prev = chunk;
1706 }
1707 if ((ir->flag & FWXFERQ_HANDLER) == 0)
1708 FW_GUNLOCK(fc);
1672 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1673 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1674 splx(s);
1675 stat = OREAD(sc, OHCI_IRCTL(dmach));
1676 if (stat & OHCI_CNTL_DMA_ACTIVE)
1677 return 0;
1678 if (stat & OHCI_CNTL_DMA_RUN) {
1679 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);

--- 29 unchanged lines hidden (view full) ---

1709 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1710 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1711
1712 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1713 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1714 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1715 }
1716
1709 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1710 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1711 splx(s);
1712 stat = OREAD(sc, OHCI_IRCTL(dmach));
1713 if (stat & OHCI_CNTL_DMA_ACTIVE)
1714 return 0;
1715 if (stat & OHCI_CNTL_DMA_RUN) {
1716 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);

--- 29 unchanged lines hidden (view full) ---

1746 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1747 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1748
1749 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1750 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1751 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1752 }
1753
1717/* FLUSH FIFO and reset Transmitter/Reciever */
1718 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1754 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1755 fw_drain_txq(&sc->fc);
1719
1756
1757#if 0 /* Let dcons(4) be accessed */
1720/* Stop interrupt */
1721 OWRITE(sc, FWOHCI_INTMASKCLR,
1722 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1723 | OHCI_INT_PHY_INT
1724 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1725 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1726 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1727 | OHCI_INT_PHY_BUS_R);
1728
1758/* Stop interrupt */
1759 OWRITE(sc, FWOHCI_INTMASKCLR,
1760 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1761 | OHCI_INT_PHY_INT
1762 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1763 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1764 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1765 | OHCI_INT_PHY_BUS_R);
1766
1729 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1730 fw_drain_txq(&sc->fc);
1767/* FLUSH FIFO and reset Transmitter/Reciever */
1768 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1769#endif
1731
1732/* XXX Link down? Bus reset? */
1733 return 0;
1734}
1735
1736int
1737fwohci_resume(struct fwohci_softc *sc, device_t dev)
1738{

--- 18 unchanged lines hidden (view full) ---

1757 }
1758 }
1759
1760 bus_generic_resume(dev);
1761 sc->fc.ibr(&sc->fc);
1762 return 0;
1763}
1764
1770
1771/* XXX Link down? Bus reset? */
1772 return 0;
1773}
1774
1775int
1776fwohci_resume(struct fwohci_softc *sc, device_t dev)
1777{

--- 18 unchanged lines hidden (view full) ---

1796 }
1797 }
1798
1799 bus_generic_resume(dev);
1800 sc->fc.ibr(&sc->fc);
1801 return 0;
1802}
1803
1765#define ACK_ALL
1804#ifdef OHCI_DEBUG
1766static void
1805static void
1767fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
1806fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
1768{
1807{
1769 uint32_t irstat, itstat;
1770 u_int i;
1771 struct firewire_comm *fc = (struct firewire_comm *)sc;
1772
1773#ifdef OHCI_DEBUG
1774 if(stat & OREAD(sc, FWOHCI_INTMASK))
1775 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1776 stat & OHCI_INT_EN ? "DMA_EN ":"",
1777 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1778 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1779 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1780 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1781 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",

--- 9 unchanged lines hidden (view full) ---

1791 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1792 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1793 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1794 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1795 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1796 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1797 stat, OREAD(sc, FWOHCI_INTMASK)
1798 );
1808 if(stat & OREAD(sc, FWOHCI_INTMASK))
1809 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1810 stat & OHCI_INT_EN ? "DMA_EN ":"",
1811 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1812 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1813 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1814 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1815 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",

--- 9 unchanged lines hidden (view full) ---

1825 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1826 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1827 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1828 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1829 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1830 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1831 stat, OREAD(sc, FWOHCI_INTMASK)
1832 );
1833}
1799#endif
1834#endif
1800/* Bus reset */
1801 if(stat & OHCI_INT_PHY_BUS_R ){
1802 if (fc->status == FWBUSRESET)
1803 goto busresetout;
1835static void
1836fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1837{
1838 struct firewire_comm *fc = (struct firewire_comm *)sc;
1839 uint32_t node_id, plen;
1840
1841 if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1842 fc->status = FWBUSRESET;
1804 /* Disable bus reset interrupt until sid recv. */
1805 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1806
1807 device_printf(fc->dev, "BUS reset\n");
1808 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1809 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1810
1811 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1812 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1813 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1814 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1815
1843 /* Disable bus reset interrupt until sid recv. */
1844 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1845
1846 device_printf(fc->dev, "BUS reset\n");
1847 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1848 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1849
1850 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1851 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1852 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1853 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1854
1816#ifndef ACK_ALL
1855 if (!kdb_active)
1856 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_busreset);
1857 }
1858 if (stat & OHCI_INT_PHY_SID) {
1859 /* Enable bus reset interrupt */
1817 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1860 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1818#endif
1819 fw_busreset(fc, FWBUSRESET);
1820 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1821 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
1861 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1862
1863 /* Allow async. request to us */
1864 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1865 /* XXX insecure ?? */
1866 /* allow from all nodes */
1867 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1868 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1869 /* 0 to 4GB regison */
1870 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1871 /* Set ATRetries register */
1872 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1873
1874 /*
1875 * Checking whether the node is root or not. If root, turn on
1876 * cycle master.
1877 */
1878 node_id = OREAD(sc, FWOHCI_NODEID);
1879 plen = OREAD(sc, OHCI_SID_CNT);
1880
1881 fc->nodeid = node_id & 0x3f;
1882 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1883 node_id, (plen >> 16) & 0xff);
1884 if (!(node_id & OHCI_NODE_VALID)) {
1885 printf("Bus reset failure\n");
1886 goto sidout;
1887 }
1888
1889 /* cycle timer */
1890 sc->cycle_lost = 0;
1891 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST);
1892 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) {
1893 printf("CYCLEMASTER mode\n");
1894 OWRITE(sc, OHCI_LNKCTL,
1895 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1896 } else {
1897 printf("non CYCLEMASTER mode\n");
1898 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1899 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1900 }
1901
1902 fc->status = FWBUSINIT;
1903
1904 if (!kdb_active)
1905 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_sid);
1822 }
1906 }
1823busresetout:
1824 if((stat & OHCI_INT_DMA_IR )){
1825#ifndef ACK_ALL
1826 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1827#endif
1828#if defined(__DragonFly__) || __FreeBSD_version < 500000
1829 irstat = sc->irstat;
1830 sc->irstat = 0;
1831#else
1907sidout:
1908 if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active))
1909 taskqueue_enqueue(sc->fc.taskqueue, &sc->fwohci_task_dma);
1910}
1911
1912static void
1913fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count)
1914{
1915 uint32_t irstat, itstat;
1916 u_int i;
1917 struct firewire_comm *fc = (struct firewire_comm *)sc;
1918
1919 if (stat & OHCI_INT_DMA_IR) {
1832 irstat = atomic_readandclear_int(&sc->irstat);
1920 irstat = atomic_readandclear_int(&sc->irstat);
1833#endif
1834 for(i = 0; i < fc->nisodma ; i++){
1835 struct fwohci_dbch *dbch;
1836
1837 if((irstat & (1 << i)) != 0){
1838 dbch = &sc->ir[i];
1839 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1840 device_printf(sc->fc.dev,
1841 "dma(%d) not active\n", i);
1842 continue;
1843 }
1844 fwohci_rbuf_update(sc, i);
1845 }
1846 }
1847 }
1921 for(i = 0; i < fc->nisodma ; i++){
1922 struct fwohci_dbch *dbch;
1923
1924 if((irstat & (1 << i)) != 0){
1925 dbch = &sc->ir[i];
1926 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1927 device_printf(sc->fc.dev,
1928 "dma(%d) not active\n", i);
1929 continue;
1930 }
1931 fwohci_rbuf_update(sc, i);
1932 }
1933 }
1934 }
1848 if((stat & OHCI_INT_DMA_IT )){
1849#ifndef ACK_ALL
1850 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1851#endif
1852#if defined(__DragonFly__) || __FreeBSD_version < 500000
1853 itstat = sc->itstat;
1854 sc->itstat = 0;
1855#else
1935 if (stat & OHCI_INT_DMA_IT) {
1856 itstat = atomic_readandclear_int(&sc->itstat);
1936 itstat = atomic_readandclear_int(&sc->itstat);
1857#endif
1858 for(i = 0; i < fc->nisodma ; i++){
1859 if((itstat & (1 << i)) != 0){
1860 fwohci_tbuf_update(sc, i);
1861 }
1862 }
1863 }
1937 for(i = 0; i < fc->nisodma ; i++){
1938 if((itstat & (1 << i)) != 0){
1939 fwohci_tbuf_update(sc, i);
1940 }
1941 }
1942 }
1864 if((stat & OHCI_INT_DMA_PRRS )){
1865#ifndef ACK_ALL
1866 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1867#endif
1943 if (stat & OHCI_INT_DMA_PRRS) {
1868#if 0
1869 dump_dma(sc, ARRS_CH);
1870 dump_db(sc, ARRS_CH);
1871#endif
1872 fwohci_arcv(sc, &sc->arrs, count);
1873 }
1944#if 0
1945 dump_dma(sc, ARRS_CH);
1946 dump_db(sc, ARRS_CH);
1947#endif
1948 fwohci_arcv(sc, &sc->arrs, count);
1949 }
1874 if((stat & OHCI_INT_DMA_PRRQ )){
1875#ifndef ACK_ALL
1876 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1877#endif
1950 if (stat & OHCI_INT_DMA_PRRQ) {
1878#if 0
1879 dump_dma(sc, ARRQ_CH);
1880 dump_db(sc, ARRQ_CH);
1881#endif
1882 fwohci_arcv(sc, &sc->arrq, count);
1883 }
1884 if (stat & OHCI_INT_CYC_LOST) {
1885 if (sc->cycle_lost >= 0)
1886 sc->cycle_lost ++;
1887 if (sc->cycle_lost > 10) {
1888 sc->cycle_lost = -1;
1889#if 0
1890 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER);
1891#endif
1892 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1893 device_printf(fc->dev, "too many cycle lost, "
1894 "no cycle master presents?\n");
1895 }
1896 }
1951#if 0
1952 dump_dma(sc, ARRQ_CH);
1953 dump_db(sc, ARRQ_CH);
1954#endif
1955 fwohci_arcv(sc, &sc->arrq, count);
1956 }
1957 if (stat & OHCI_INT_CYC_LOST) {
1958 if (sc->cycle_lost >= 0)
1959 sc->cycle_lost ++;
1960 if (sc->cycle_lost > 10) {
1961 sc->cycle_lost = -1;
1962#if 0
1963 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER);
1964#endif
1965 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1966 device_printf(fc->dev, "too many cycle lost, "
1967 "no cycle master presents?\n");
1968 }
1969 }
1897 if(stat & OHCI_INT_PHY_SID){
1898 uint32_t *buf, node_id;
1899 int plen;
1900
1901#ifndef ACK_ALL
1902 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1903#endif
1904 /* Enable bus reset interrupt */
1905 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1906 /* Allow async. request to us */
1907 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1908 /* XXX insecure ?? */
1909 /* allow from all nodes */
1910 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1911 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1912 /* 0 to 4GB regison */
1913 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1914 /* Set ATRetries register */
1915 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1916/*
1917** Checking whether the node is root or not. If root, turn on
1918** cycle master.
1919*/
1920 node_id = OREAD(sc, FWOHCI_NODEID);
1921 plen = OREAD(sc, OHCI_SID_CNT);
1922
1923 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1924 node_id, (plen >> 16) & 0xff);
1925 if (!(node_id & OHCI_NODE_VALID)) {
1926 printf("Bus reset failure\n");
1927 goto sidout;
1928 }
1929
1930 /* cycle timer */
1931 sc->cycle_lost = 0;
1932 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST);
1933 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) {
1934 printf("CYCLEMASTER mode\n");
1935 OWRITE(sc, OHCI_LNKCTL,
1936 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1937 } else {
1938 printf("non CYCLEMASTER mode\n");
1939 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1940 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1941 }
1942
1943 fc->nodeid = node_id & 0x3f;
1944
1945 if (plen & OHCI_SID_ERR) {
1946 device_printf(fc->dev, "SID Error\n");
1947 goto sidout;
1948 }
1949 plen &= OHCI_SID_CNT_MASK;
1950 if (plen < 4 || plen > OHCI_SIDSIZE) {
1951 device_printf(fc->dev, "invalid SID len = %d\n", plen);
1952 goto sidout;
1953 }
1954 plen -= 4; /* chop control info */
1955 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
1956 if (buf == NULL) {
1957 device_printf(fc->dev, "malloc failed\n");
1958 goto sidout;
1959 }
1960 for (i = 0; i < plen / 4; i ++)
1961 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1962#if 1 /* XXX needed?? */
1963 /* pending all pre-bus_reset packets */
1964 fwohci_txd(sc, &sc->atrq);
1965 fwohci_txd(sc, &sc->atrs);
1966 fwohci_arcv(sc, &sc->arrs, -1);
1967 fwohci_arcv(sc, &sc->arrq, -1);
1968 fw_drain_txq(fc);
1969#endif
1970 fw_sidrcv(fc, buf, plen);
1971 free(buf, M_FW);
1972 }
1973sidout:
1974 if((stat & OHCI_INT_DMA_ATRQ )){
1975#ifndef ACK_ALL
1976 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1977#endif
1970 if (stat & OHCI_INT_DMA_ATRQ) {
1978 fwohci_txd(sc, &(sc->atrq));
1979 }
1971 fwohci_txd(sc, &(sc->atrq));
1972 }
1980 if((stat & OHCI_INT_DMA_ATRS )){
1981#ifndef ACK_ALL
1982 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1983#endif
1973 if (stat & OHCI_INT_DMA_ATRS) {
1984 fwohci_txd(sc, &(sc->atrs));
1985 }
1974 fwohci_txd(sc, &(sc->atrs));
1975 }
1986 if((stat & OHCI_INT_PW_ERR )){
1987#ifndef ACK_ALL
1988 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1989#endif
1976 if (stat & OHCI_INT_PW_ERR) {
1990 device_printf(fc->dev, "posted write error\n");
1991 }
1977 device_printf(fc->dev, "posted write error\n");
1978 }
1992 if((stat & OHCI_INT_ERR )){
1993#ifndef ACK_ALL
1994 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1995#endif
1979 if (stat & OHCI_INT_ERR) {
1996 device_printf(fc->dev, "unrecoverable error\n");
1997 }
1980 device_printf(fc->dev, "unrecoverable error\n");
1981 }
1998 if((stat & OHCI_INT_PHY_INT)) {
1999#ifndef ACK_ALL
2000 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
2001#endif
1982 if (stat & OHCI_INT_PHY_INT) {
2002 device_printf(fc->dev, "phy int\n");
2003 }
2004
2005 return;
2006}
2007
1983 device_printf(fc->dev, "phy int\n");
1984 }
1985
1986 return;
1987}
1988
2008#if FWOHCI_TASKQUEUE
2009static void
1989static void
2010fwohci_complete(void *arg, int pending)
1990fwohci_task_busreset(void *arg, int pending)
2011{
2012 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1991{
1992 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1993
1994 fw_busreset(&sc->fc, FWBUSRESET);
1995 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1996 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
1997}
1998
1999static void
2000fwohci_task_sid(void *arg, int pending)
2001{
2002 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2003 struct firewire_comm *fc = &sc->fc;
2004 uint32_t *buf;
2005 int i, plen;
2006
2007
2008 plen = OREAD(sc, OHCI_SID_CNT);
2009
2010 if (plen & OHCI_SID_ERR) {
2011 device_printf(fc->dev, "SID Error\n");
2012 return;
2013 }
2014 plen &= OHCI_SID_CNT_MASK;
2015 if (plen < 4 || plen > OHCI_SIDSIZE) {
2016 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2017 return;
2018 }
2019 plen -= 4; /* chop control info */
2020 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2021 if (buf == NULL) {
2022 device_printf(fc->dev, "malloc failed\n");
2023 return;
2024 }
2025 for (i = 0; i < plen / 4; i ++)
2026 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2027#if 1 /* XXX needed?? */
2028 /* pending all pre-bus_reset packets */
2029 fwohci_txd(sc, &sc->atrq);
2030 fwohci_txd(sc, &sc->atrs);
2031 fwohci_arcv(sc, &sc->arrs, -1);
2032 fwohci_arcv(sc, &sc->arrq, -1);
2033 fw_drain_txq(fc);
2034#endif
2035 fw_sidrcv(fc, buf, plen);
2036 free(buf, M_FW);
2037}
2038
2039static void
2040fwohci_task_dma(void *arg, int pending)
2041{
2042 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2013 uint32_t stat;
2014
2015again:
2016 stat = atomic_readandclear_int(&sc->intstat);
2017 if (stat)
2043 uint32_t stat;
2044
2045again:
2046 stat = atomic_readandclear_int(&sc->intstat);
2047 if (stat)
2018 fwohci_intr_body(sc, stat, -1);
2048 fwohci_intr_dma(sc, stat, -1);
2019 else
2020 return;
2021 goto again;
2022}
2049 else
2050 return;
2051 goto again;
2052}
2023#endif
2024
2053
2025static uint32_t
2026fwochi_check_stat(struct fwohci_softc *sc)
2054static int
2055fwohci_check_stat(struct fwohci_softc *sc)
2027{
2028 uint32_t stat, irstat, itstat;
2029
2030 stat = OREAD(sc, FWOHCI_INTSTAT);
2031 if (stat == 0xffffffff) {
2032 device_printf(sc->fc.dev,
2033 "device physically ejected?\n");
2056{
2057 uint32_t stat, irstat, itstat;
2058
2059 stat = OREAD(sc, FWOHCI_INTSTAT);
2060 if (stat == 0xffffffff) {
2061 device_printf(sc->fc.dev,
2062 "device physically ejected?\n");
2034 return(stat);
2063 return (FILTER_STRAY);
2035 }
2064 }
2036#ifdef ACK_ALL
2037 if (stat)
2065 if (stat)
2038 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
2039#endif
2066 OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
2067
2068 stat &= sc->intmask;
2069 if (stat == 0)
2070 return (FILTER_STRAY);
2071
2072 atomic_set_int(&sc->intstat, stat);
2040 if (stat & OHCI_INT_DMA_IR) {
2041 irstat = OREAD(sc, OHCI_IR_STAT);
2042 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2043 atomic_set_int(&sc->irstat, irstat);
2044 }
2045 if (stat & OHCI_INT_DMA_IT) {
2046 itstat = OREAD(sc, OHCI_IT_STAT);
2047 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2048 atomic_set_int(&sc->itstat, itstat);
2049 }
2073 if (stat & OHCI_INT_DMA_IR) {
2074 irstat = OREAD(sc, OHCI_IR_STAT);
2075 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2076 atomic_set_int(&sc->irstat, irstat);
2077 }
2078 if (stat & OHCI_INT_DMA_IT) {
2079 itstat = OREAD(sc, OHCI_IT_STAT);
2080 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2081 atomic_set_int(&sc->itstat, itstat);
2082 }
2050 return(stat);
2083
2084 fwohci_intr_core(sc, stat, -1);
2085 return (FILTER_HANDLED);
2051}
2052
2086}
2087
2053void
2054fwohci_intr(void *arg)
2088int
2089fwohci_filt(void *arg)
2055{
2056 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2090{
2091 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2057 uint32_t stat;
2058#if !FWOHCI_TASKQUEUE
2059 uint32_t bus_reset = 0;
2060#endif
2061
2062 if (!(sc->intmask & OHCI_INT_EN)) {
2063 /* polling mode */
2092
2093 if (!(sc->intmask & OHCI_INT_EN)) {
2094 /* polling mode */
2064 return;
2095 return (FILTER_STRAY);
2065 }
2096 }
2097 return (fwohci_check_stat(sc));
2098}
2066
2099
2067#if !FWOHCI_TASKQUEUE
2068again:
2069#endif
2070 stat = fwochi_check_stat(sc);
2071 if (stat == 0 || stat == 0xffffffff)
2072 return;
2073#if FWOHCI_TASKQUEUE
2074 atomic_set_int(&sc->intstat, stat);
2075 /* XXX mask bus reset intr. during bus reset phase */
2076 if (stat)
2077 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete);
2078#else
2079 /* We cannot clear bus reset event during bus reset phase */
2080 if ((stat & ~bus_reset) == 0)
2081 return;
2082 bus_reset = stat & OHCI_INT_PHY_BUS_R;
2083 fwohci_intr_body(sc, stat, -1);
2084 goto again;
2085#endif
2100void
2101fwohci_intr(void *arg)
2102{
2103 fwohci_filt(arg);
2086}
2087
2088void
2089fwohci_poll(struct firewire_comm *fc, int quick, int count)
2090{
2104}
2105
2106void
2107fwohci_poll(struct firewire_comm *fc, int quick, int count)
2108{
2091 int s;
2092 uint32_t stat;
2093 struct fwohci_softc *sc;
2094
2095
2096 sc = (struct fwohci_softc *)fc;
2097 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2098 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2099 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2100#if 0
2101 if (!quick) {
2102#else
2103 if (1) {
2104#endif
2105 stat = fwochi_check_stat(sc);
2106 if (stat == 0 || stat == 0xffffffff)
2107 return;
2108 }
2109 s = splfw();
2110 fwohci_intr_body(sc, stat, count);
2111 splx(s);
2109 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
2110 fwohci_check_stat(sc);
2112}
2113
2114static void
2115fwohci_set_intr(struct firewire_comm *fc, int enable)
2116{
2117 struct fwohci_softc *sc;
2118
2119 sc = (struct fwohci_softc *)fc;

--- 16 unchanged lines hidden (view full) ---

2136 struct fw_bulkxfer *chunk;
2137 struct fw_xferq *it;
2138 uint32_t stat, count;
2139 int s, w=0, ldesc;
2140
2141 it = fc->it[dmach];
2142 ldesc = sc->it[dmach].ndesc - 1;
2143 s = splfw(); /* unnecessary ? */
2111}
2112
2113static void
2114fwohci_set_intr(struct firewire_comm *fc, int enable)
2115{
2116 struct fwohci_softc *sc;
2117
2118 sc = (struct fwohci_softc *)fc;

--- 16 unchanged lines hidden (view full) ---

2135 struct fw_bulkxfer *chunk;
2136 struct fw_xferq *it;
2137 uint32_t stat, count;
2138 int s, w=0, ldesc;
2139
2140 it = fc->it[dmach];
2141 ldesc = sc->it[dmach].ndesc - 1;
2142 s = splfw(); /* unnecessary ? */
2143 FW_GLOCK(fc);
2144 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2145 if (firewire_debug)
2146 dump_db(sc, ITX_CH + dmach);
2147 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2148 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2149 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2150 >> OHCI_STATUS_SHIFT;
2151 db = ((struct fwohcidb_tr *)(chunk->start))->db;

--- 12 unchanged lines hidden (view full) ---

2164 default:
2165 device_printf(fc->dev,
2166 "Isochronous transmit err %02x(%s)\n",
2167 stat, fwohcicode[stat & 0x1f]);
2168 }
2169 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2170 w++;
2171 }
2144 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2145 if (firewire_debug)
2146 dump_db(sc, ITX_CH + dmach);
2147 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2148 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2149 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2150 >> OHCI_STATUS_SHIFT;
2151 db = ((struct fwohcidb_tr *)(chunk->start))->db;

--- 12 unchanged lines hidden (view full) ---

2164 default:
2165 device_printf(fc->dev,
2166 "Isochronous transmit err %02x(%s)\n",
2167 stat, fwohcicode[stat & 0x1f]);
2168 }
2169 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2170 w++;
2171 }
2172 FW_GUNLOCK(fc);
2172 splx(s);
2173 if (w)
2174 wakeup(it);
2175}
2176
2177static void
2178fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2179{
2180 struct firewire_comm *fc = &sc->fc;
2181 struct fwohcidb_tr *db_tr;
2182 struct fw_bulkxfer *chunk;
2183 struct fw_xferq *ir;
2184 uint32_t stat;
2173 splx(s);
2174 if (w)
2175 wakeup(it);
2176}
2177
2178static void
2179fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2180{
2181 struct firewire_comm *fc = &sc->fc;
2182 struct fwohcidb_tr *db_tr;
2183 struct fw_bulkxfer *chunk;
2184 struct fw_xferq *ir;
2185 uint32_t stat;
2185 int s, w=0, ldesc;
2186 int s, w = 0, ldesc;
2186
2187 ir = fc->ir[dmach];
2188 ldesc = sc->ir[dmach].ndesc - 1;
2187
2188 ir = fc->ir[dmach];
2189 ldesc = sc->ir[dmach].ndesc - 1;
2190
2189#if 0
2190 dump_db(sc, dmach);
2191#endif
2192 s = splfw();
2191#if 0
2192 dump_db(sc, dmach);
2193#endif
2194 s = splfw();
2195 if ((ir->flag & FWXFERQ_HANDLER) == 0)
2196 FW_GLOCK(fc);
2193 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2194 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2195 db_tr = (struct fwohcidb_tr *)chunk->end;
2196 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2197 >> OHCI_STATUS_SHIFT;
2198 if (stat == 0)
2199 break;
2200

--- 18 unchanged lines hidden (view full) ---

2219 default:
2220 chunk->resp = EINVAL;
2221 device_printf(fc->dev,
2222 "Isochronous receive err %02x(%s)\n",
2223 stat, fwohcicode[stat & 0x1f]);
2224 }
2225 w++;
2226 }
2197 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2198 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2199 db_tr = (struct fwohcidb_tr *)chunk->end;
2200 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2201 >> OHCI_STATUS_SHIFT;
2202 if (stat == 0)
2203 break;
2204

--- 18 unchanged lines hidden (view full) ---

2223 default:
2224 chunk->resp = EINVAL;
2225 device_printf(fc->dev,
2226 "Isochronous receive err %02x(%s)\n",
2227 stat, fwohcicode[stat & 0x1f]);
2228 }
2229 w++;
2230 }
2231 if ((ir->flag & FWXFERQ_HANDLER) == 0)
2232 FW_GUNLOCK(fc);
2227 splx(s);
2233 splx(s);
2228 if (w) {
2229 if (ir->flag & FWXFERQ_HANDLER)
2230 ir->hand(ir);
2231 else
2232 wakeup(ir);
2233 }
2234 if (w == 0)
2235 return;
2236
2237 if (ir->flag & FWXFERQ_HANDLER)
2238 ir->hand(ir);
2239 else
2240 wakeup(ir);
2234}
2235
2236void
2237dump_dma(struct fwohci_softc *sc, uint32_t ch)
2238{
2239 uint32_t off, cntl, stat, cmd, match;
2240
2241 if(ch == 0){

--- 240 unchanged lines hidden (view full) ---

2482 struct fwohcidb_tr *db_tr, *fdb_tr;
2483 struct fwohci_dbch *dbch;
2484 struct fwohcidb *db;
2485 struct fw_pkt *fp;
2486 struct fwohci_txpkthdr *ohcifp;
2487 unsigned short chtag;
2488 int idb;
2489
2241}
2242
2243void
2244dump_dma(struct fwohci_softc *sc, uint32_t ch)
2245{
2246 uint32_t off, cntl, stat, cmd, match;
2247
2248 if(ch == 0){

--- 240 unchanged lines hidden (view full) ---

2489 struct fwohcidb_tr *db_tr, *fdb_tr;
2490 struct fwohci_dbch *dbch;
2491 struct fwohcidb *db;
2492 struct fw_pkt *fp;
2493 struct fwohci_txpkthdr *ohcifp;
2494 unsigned short chtag;
2495 int idb;
2496
2497 FW_GLOCK_ASSERT(&sc->fc);
2498
2490 dbch = &sc->it[dmach];
2491 chtag = sc->it[dmach].xferq.flag & 0xff;
2492
2493 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2494 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2495/*
2496device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2497*/

--- 467 unchanged lines hidden --- 		2499 dbch = &sc->it[dmach];
2500 chtag = sc->it[dmach].xferq.flag & 0xff;
2501
2502 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2503 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2504/*
2505device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2506*/

--- 467 unchanged lines hidden ---