| fwohci.c (144263) | fwohci.c (167086) |
|---|---|
| 1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * | 1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 17 unchanged lines hidden (view full) --- 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * |
| 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 144263 2005-03-29 01:44:59Z sam $ | 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 167086 2007-02-27 17:23:29Z jhb $ |
| 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 --- 1232 unchanged lines hidden (view full) --- 1275 dbch->bottom = dbch->top; 1276 dbch->flags = FWOHCI_DBCH_INIT; 1277} 1278 1279static int 1280fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1281{ 1282 struct fwohci_softc *sc = (struct fwohci_softc *)fc; | 35 * 36 */ 37 38#define ATRQ_CH 0 39#define ATRS_CH 1 40#define ARRQ_CH 2 41#define ARRS_CH 3 42#define ITX_CH 4 --- 1232 unchanged lines hidden (view full) --- 1275 dbch->bottom = dbch->top; 1276 dbch->flags = FWOHCI_DBCH_INIT; 1277} 1278 1279static int 1280fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1281{ 1282 struct fwohci_softc *sc = (struct fwohci_softc *)fc; |
| 1283 int sleepch; | |
| 1284 1285 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1286 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1287 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1288 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1289 /* XXX we cannot free buffers until the DMA really stops */ | 1283 1284 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1285 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1286 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1287 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1288 /* XXX we cannot free buffers until the DMA really stops */ |
| 1290 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); | 1289 pause("fwitxd", hz); |
| 1291 fwohci_db_free(&sc->it[dmach]); 1292 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1293 return 0; 1294} 1295 1296static int 1297fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1298{ 1299 struct fwohci_softc *sc = (struct fwohci_softc *)fc; | 1290 fwohci_db_free(&sc->it[dmach]); 1291 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1292 return 0; 1293} 1294 1295static int 1296fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1297{ 1298 struct fwohci_softc *sc = (struct fwohci_softc *)fc; |
| 1300 int sleepch; | |
| 1301 1302 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1303 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1304 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1305 /* XXX we cannot free buffers until the DMA really stops */ | 1299 1300 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1301 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1302 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1303 /* XXX we cannot free buffers until the DMA really stops */ |
| 1306 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); | 1304 pause("fwirxd", hz); |
| 1307 fwohci_db_free(&sc->ir[dmach]); 1308 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1309 return 0; 1310} 1311 1312#if BYTE_ORDER == BIG_ENDIAN 1313static void 1314fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) --- 1592 unchanged lines hidden --- | 1305 fwohci_db_free(&sc->ir[dmach]); 1306 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1307 return 0; 1308} 1309 1310#if BYTE_ORDER == BIG_ENDIAN 1311static void 1312fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) --- 1592 unchanged lines hidden --- |