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fwohci.c (119120) fwohci.c (119155)
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 119120 2003-08-19 08:59:07Z simokawa $
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 119155 2003-08-20 03:11:37Z simokawa $
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

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834 int tcode, hdr_len, pl_off, pl_len;
835 int fsegment = -1;
836 u_int32_t off;
837 struct fw_xfer *xfer;
838 struct fw_pkt *fp;
839 volatile struct fwohci_txpkthdr *ohcifp;
840 struct fwohcidb_tr *db_tr;
841 volatile struct fwohcidb *db;
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

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834 int tcode, hdr_len, pl_off, pl_len;
835 int fsegment = -1;
836 u_int32_t off;
837 struct fw_xfer *xfer;
838 struct fw_pkt *fp;
839 volatile struct fwohci_txpkthdr *ohcifp;
840 struct fwohcidb_tr *db_tr;
841 volatile struct fwohcidb *db;
842 volatile u_int32_t *ld;
842 struct tcode_info *info;
843 static int maxdesc=0;
844
845 if(&sc->atrq == dbch){
846 off = OHCI_ATQOFF;
847 }else if(&sc->atrs == dbch){
848 off = OHCI_ATSOFF;
849 }else{

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868 xfer->state = FWXF_START;
869
870 fp = (struct fw_pkt *)xfer->send.buf;
871 tcode = fp->mode.common.tcode;
872
873 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
874 info = &tinfo[tcode];
875 hdr_len = pl_off = info->hdr_len;
843 struct tcode_info *info;
844 static int maxdesc=0;
845
846 if(&sc->atrq == dbch){
847 off = OHCI_ATQOFF;
848 }else if(&sc->atrs == dbch){
849 off = OHCI_ATSOFF;
850 }else{

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869 xfer->state = FWXF_START;
870
871 fp = (struct fw_pkt *)xfer->send.buf;
872 tcode = fp->mode.common.tcode;
873
874 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
875 info = &tinfo[tcode];
876 hdr_len = pl_off = info->hdr_len;
876 for( i = 0 ; i < pl_off ; i+= 4){
877 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4];
878 }
879 ohcifp->mode.common.spd = xfer->spd;
877
878 ld = &ohcifp->mode.ld[0];
879 ld[0] = ld[1] = ld[2] = ld[3] = 0;
880 for( i = 0 ; i < pl_off ; i+= 4)
881 ld[i/4] = fp->mode.ld[i/4];
882
883 ohcifp->mode.common.spd = xfer->spd & 0x7;
880 if (tcode == FWTCODE_STREAM ){
881 hdr_len = 8;
882 ohcifp->mode.stream.len = fp->mode.stream.len;
883 } else if (tcode == FWTCODE_PHY) {
884 hdr_len = 12;
884 if (tcode == FWTCODE_STREAM ){
885 hdr_len = 8;
886 ohcifp->mode.stream.len = fp->mode.stream.len;
887 } else if (tcode == FWTCODE_PHY) {
888 hdr_len = 12;
885 ohcifp->mode.ld[1] = fp->mode.ld[1];
886 ohcifp->mode.ld[2] = fp->mode.ld[2];
889 ld[1] = fp->mode.ld[1];
890 ld[2] = fp->mode.ld[2];
887 ohcifp->mode.common.spd = 0;
888 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
889 } else {
890 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
891 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
892 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
893 }
894 db = &db_tr->db[0];
895 FWOHCI_DMA_WRITE(db->db.desc.cmd,
896 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
891 ohcifp->mode.common.spd = 0;
892 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
893 } else {
894 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
895 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
896 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
897 }
898 db = &db_tr->db[0];
899 FWOHCI_DMA_WRITE(db->db.desc.cmd,
900 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
901 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
897 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
898/* Specify bound timer of asy. responce */
899 if(&sc->atrs == dbch){
900 FWOHCI_DMA_WRITE(db->db.desc.res,
901 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
902 }
903#if BYTE_ORDER == BIG_ENDIAN
904 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
905 hdr_len = 12;
906 for (i = 0; i < hdr_len/4; i ++)
902 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
903/* Specify bound timer of asy. responce */
904 if(&sc->atrs == dbch){
905 FWOHCI_DMA_WRITE(db->db.desc.res,
906 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
907 }
908#if BYTE_ORDER == BIG_ENDIAN
909 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
910 hdr_len = 12;
911 for (i = 0; i < hdr_len/4; i ++)
907 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]);
912 FWOHCI_DMA_WRITE(ld[i], ld[i]);
908#endif
909
910again:
911 db_tr->dbcnt = 2;
912 db = &db_tr->db[db_tr->dbcnt];
913 pl_len = xfer->send.len - pl_off;
914 if (pl_len > 0) {
915 int err;

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1052 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1053 if (fc->status != FWBUSRESET)
1054 /* maybe out of order?? */
1055 goto out;
1056 }
1057 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1058 BUS_DMASYNC_POSTWRITE);
1059 bus_dmamap_unload(dbch->dmat, tr->dma_map);
913#endif
914
915again:
916 db_tr->dbcnt = 2;
917 db = &db_tr->db[db_tr->dbcnt];
918 pl_len = xfer->send.len - pl_off;
919 if (pl_len > 0) {
920 int err;

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1057 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1058 if (fc->status != FWBUSRESET)
1059 /* maybe out of order?? */
1060 goto out;
1061 }
1062 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1063 BUS_DMASYNC_POSTWRITE);
1064 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1060#if 0
1061 dump_db(sc, ch);
1065#if 1
1066 if (firewire_debug)
1067 dump_db(sc, ch);
1062#endif
1063 if(status & OHCI_CNTL_DMA_DEAD) {
1064 /* Stop DMA */
1065 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1066 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1067 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1068 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1069 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);

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2101 struct fw_xferq *it;
2102 u_int32_t stat, count;
2103 int s, w=0, ldesc;
2104
2105 it = fc->it[dmach];
2106 ldesc = sc->it[dmach].ndesc - 1;
2107 s = splfw(); /* unnecessary ? */
2108 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
1068#endif
1069 if(status & OHCI_CNTL_DMA_DEAD) {
1070 /* Stop DMA */
1071 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1072 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1073 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1074 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1075 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);

--- 1031 unchanged lines hidden (view full) ---

2107 struct fw_xferq *it;
2108 u_int32_t stat, count;
2109 int s, w=0, ldesc;
2110
2111 it = fc->it[dmach];
2112 ldesc = sc->it[dmach].ndesc - 1;
2113 s = splfw(); /* unnecessary ? */
2114 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2115 if (firewire_debug)
2116 dump_db(sc, ITX_CH + dmach);
2109 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2110 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2111 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2112 >> OHCI_STATUS_SHIFT;
2113 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2117 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2118 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2119 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2120 >> OHCI_STATUS_SHIFT;
2121 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2122 /* timestamp */
2114 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2115 & OHCI_COUNT_MASK;
2116 if (stat == 0)
2117 break;
2118 STAILQ_REMOVE_HEAD(&it->stdma, link);
2119 switch (stat & FWOHCIEV_MASK){
2120 case FWOHCIEV_ACKCOMPL:
2121#if 0

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2449/*
2450device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2451*/
2452 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2453 db = db_tr->db;
2454 fp = (struct fw_pkt *)db_tr->buf;
2455 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed;
2456 ohcifp->mode.ld[0] = fp->mode.ld[0];
2123 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2124 & OHCI_COUNT_MASK;
2125 if (stat == 0)
2126 break;
2127 STAILQ_REMOVE_HEAD(&it->stdma, link);
2128 switch (stat & FWOHCIEV_MASK){
2129 case FWOHCIEV_ACKCOMPL:
2130#if 0

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2458/*
2459device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2460*/
2461 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2462 db = db_tr->db;
2463 fp = (struct fw_pkt *)db_tr->buf;
2464 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed;
2465 ohcifp->mode.ld[0] = fp->mode.ld[0];
2466 ohcifp->mode.common.spd = 0 & 0x7;
2457 ohcifp->mode.stream.len = fp->mode.stream.len;
2458 ohcifp->mode.stream.chtag = chtag;
2459 ohcifp->mode.stream.tcode = 0xa;
2467 ohcifp->mode.stream.len = fp->mode.stream.len;
2468 ohcifp->mode.stream.chtag = chtag;
2469 ohcifp->mode.stream.tcode = 0xa;
2460 ohcifp->mode.stream.spd = 0;
2461#if BYTE_ORDER == BIG_ENDIAN
2462 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2463 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2464#endif
2465
2466 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2467 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2468 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);

--- 40 unchanged lines hidden (view full) ---

2509 err = EINVAL;
2510 return err;
2511 }
2512 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2513 db_tr->dbcnt = 3;
2514
2515 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2516 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2470#if BYTE_ORDER == BIG_ENDIAN
2471 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2472 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2473#endif
2474
2475 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2476 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2477 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);

--- 40 unchanged lines hidden (view full) ---

2518 err = EINVAL;
2519 return err;
2520 }
2521 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2522 db_tr->dbcnt = 3;
2523
2524 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2525 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2526 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2527 bzero((void *)(uintptr_t)(volatile void *)
2528 &db[1].db.immed[0], sizeof(db[1].db.immed));
2517 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2518 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2519
2520 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2521 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2522#if 1
2523 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2524 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);

--- 368 unchanged lines hidden --- 		2529 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2530 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2531
2532 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2533 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2534#if 1
2535 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2536 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);

--- 368 unchanged lines hidden ---