Deleted Added
sdiff udiff text old ( 116897 ) new ( 116978 )
full compact
fwohci.c (116897) fwohci.c (116978)
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 116897 2003-06-27 00:27:33Z simokawa $
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 116978 2003-06-28 11:11:36Z simokawa $
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

--- 501 unchanged lines hidden (view full) ---

544 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
545 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
546 fwohci_rx_enable(sc, &sc->arrq);
547 fwohci_rx_enable(sc, &sc->arrs);
548
549 /* Initialize async TX */
550 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
551 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4

--- 501 unchanged lines hidden (view full) ---

544 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
545 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
546 fwohci_rx_enable(sc, &sc->arrq);
547 fwohci_rx_enable(sc, &sc->arrs);
548
549 /* Initialize async TX */
550 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
551 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
552
552 /* AT Retries */
553 OWRITE(sc, FWOHCI_RETRY,
554 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
555 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
553 /* AT Retries */
554 OWRITE(sc, FWOHCI_RETRY,
555 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
556 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
557
558 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
559 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
560 sc->atrq.bottom = sc->atrq.top;
561 sc->atrs.bottom = sc->atrs.top;
562
556 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
557 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
558 db_tr->xfer = NULL;
559 }
560 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
561 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
562 db_tr->xfer = NULL;
563 }

--- 1112 unchanged lines hidden (view full) ---

1676/* Stop interrupt */
1677 OWRITE(sc, FWOHCI_INTMASKCLR,
1678 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1679 | OHCI_INT_PHY_INT
1680 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1681 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1682 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1683 | OHCI_INT_PHY_BUS_R);
563 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
564 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
565 db_tr->xfer = NULL;
566 }
567 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
568 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
569 db_tr->xfer = NULL;
570 }

--- 1112 unchanged lines hidden (view full) ---

1683/* Stop interrupt */
1684 OWRITE(sc, FWOHCI_INTMASKCLR,
1685 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1686 | OHCI_INT_PHY_INT
1687 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1688 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1689 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1690 | OHCI_INT_PHY_BUS_R);
1691
1692 fw_drain_txq(&sc->fc);
1693
1684/* XXX Link down? Bus reset? */
1685 return 0;
1686}
1687
1688int
1689fwohci_resume(struct fwohci_softc *sc, device_t dev)
1690{
1691 int i;
1694/* XXX Link down? Bus reset? */
1695 return 0;
1696}
1697
1698int
1699fwohci_resume(struct fwohci_softc *sc, device_t dev)
1700{
1701 int i;
1702 struct fw_xferq *ir;
1703 struct fw_bulkxfer *chunk;
1692
1693 fwohci_reset(sc, dev);
1694 /* XXX resume isochronus receive automatically. (how about TX?) */
1695 for(i = 0; i < sc->fc.nisodma; i ++) {
1704
1705 fwohci_reset(sc, dev);
1706 /* XXX resume isochronus receive automatically. (how about TX?) */
1707 for(i = 0; i < sc->fc.nisodma; i ++) {
1696 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) {
1708 ir = &sc->ir[i].xferq;
1709 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1697 device_printf(sc->fc.dev,
1698 "resume iso receive ch: %d\n", i);
1710 device_printf(sc->fc.dev,
1711 "resume iso receive ch: %d\n", i);
1699 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING;
1712 ir->flag &= ~FWXFERQ_RUNNING;
1713 /* requeue stdma to stfree */
1714 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1715 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1716 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1717 }
1700 sc->fc.irx_enable(&sc->fc, i);
1701 }
1702 }
1703
1704 bus_generic_resume(dev);
1705 sc->fc.ibr(&sc->fc);
1706 return 0;
1707}

--- 1145 unchanged lines hidden --- 		1718 sc->fc.irx_enable(&sc->fc, i);
1719 }
1720 }
1721
1722 bus_generic_resume(dev);
1723 sc->fc.ibr(&sc->fc);
1724 return 0;
1725}

--- 1145 unchanged lines hidden ---