| fwohci.c (109424) | fwohci.c (109644) |
|---|---|
| 1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * | 1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * |
| 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109424 2003-01-17 15:15:21Z simokawa $ | 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109644 2003-01-21 16:24:35Z simokawa $ |
| 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 --- 1705 unchanged lines hidden (view full) --- 1747 } 1748 if((stat & OHCI_INT_DMA_IR )){ 1749#ifndef ACK_ALL 1750 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1751#endif 1752 irstat = OREAD(sc, OHCI_IR_STAT); 1753 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1754 for(i = 0; i < fc->nisodma ; i++){ | 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 --- 1705 unchanged lines hidden (view full) --- 1747 } 1748 if((stat & OHCI_INT_DMA_IR )){ 1749#ifndef ACK_ALL 1750 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1751#endif 1752 irstat = OREAD(sc, OHCI_IR_STAT); 1753 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1754 for(i = 0; i < fc->nisodma ; i++){ |
| 1755 struct fwohci_dbch *dbch; 1756 |
|
| 1755 if((irstat & (1 << i)) != 0){ | 1757 if((irstat & (1 << i)) != 0){ |
| 1756 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1757 fwohci_ircv(sc, &sc->ir[i], count); 1758 }else{ | 1758 dbch = &sc->ir[i]; 1759 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1760 device_printf(sc->fc.dev, 1761 "dma(%d) not active\n", i); 1762 continue; 1763 } 1764 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1765 fwohci_ircv(sc, dbch, count); 1766 } else { |
| 1759 fwohci_rbuf_update(sc, i); 1760 } 1761 } 1762 } 1763 } 1764 if((stat & OHCI_INT_DMA_IT )){ 1765#ifndef ACK_ALL 1766 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); --- 977 unchanged lines hidden --- | 1767 fwohci_rbuf_update(sc, i); 1768 } 1769 } 1770 } 1771 } 1772 if((stat & OHCI_INT_DMA_IT )){ 1773#ifndef ACK_ALL 1774 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); --- 977 unchanged lines hidden --- |