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fwohci.c (108712) fwohci.c (108995)
1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108712 2003-01-05 14:58:45Z simokawa $
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108995 2003-01-09 10:25:07Z simokawa $
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4

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1480}
1481
1482static int
1483fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
1484{
1485 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1486 int err = 0;
1487 unsigned short tag, ich;
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4

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1480}
1481
1482static int
1483fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
1484{
1485 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1486 int err = 0;
1487 unsigned short tag, ich;
1488 tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1489 ich = sc->ir[dmach].xferq.flag & 0x3f;
1490 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1491
1492 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1488
1489 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1490 tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1491 ich = sc->ir[dmach].xferq.flag & 0x3f;
1492 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1493
1493 sc->ir[dmach].xferq.queued = 0;
1494 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket *
1495 sc->ir[dmach].xferq.bnchunk;
1496 sc->ir[dmach].dummy =
1497 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb,
1498 M_DEVBUF, M_DONTWAIT);
1499 if(sc->ir[dmach].dummy == NULL){
1500 err = ENOMEM;

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1534 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1535 }else{
1536 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1537 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1538 }
1539 OWRITE(sc, OHCI_IRCMD(dmach),
1540 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc);
1541 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1494 sc->ir[dmach].xferq.queued = 0;
1495 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket *
1496 sc->ir[dmach].xferq.bnchunk;
1497 sc->ir[dmach].dummy =
1498 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb,
1499 M_DEVBUF, M_DONTWAIT);
1500 if(sc->ir[dmach].dummy == NULL){
1501 err = ENOMEM;

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1535 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1536 }else{
1537 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1538 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1539 }
1540 OWRITE(sc, OHCI_IRCMD(dmach),
1541 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc);
1542 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1543 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1542 }
1544 }
1543 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1544 return err;
1545}
1546
1547static int
1548fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1549{
1550 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1551 int err = 0;

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1917 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f;
1918 switch(stat){
1919 case FWOHCIEV_ACKCOMPL:
1920 fw_rbuf_update(&sc->fc, dmach, 1);
1921 wakeup(sc->fc.ir[dmach]);
1922 fwohci_irx_enable(&sc->fc, dmach);
1923 break;
1924 default:
1545 return err;
1546}
1547
1548static int
1549fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1550{
1551 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1552 int err = 0;

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1918 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f;
1919 switch(stat){
1920 case FWOHCIEV_ACKCOMPL:
1921 fw_rbuf_update(&sc->fc, dmach, 1);
1922 wakeup(sc->fc.ir[dmach]);
1923 fwohci_irx_enable(&sc->fc, dmach);
1924 break;
1925 default:
1926 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat);
1925 break;
1926 }
1927}
1928
1929void
1930dump_dma(struct fwohci_softc *sc, u_int32_t ch)
1931{
1932 u_int32_t off, cntl, stat, cmd, match;

--- 714 unchanged lines hidden --- 		1927 break;
1928 }
1929}
1930
1931void
1932dump_dma(struct fwohci_softc *sc, u_int32_t ch)
1933{
1934 u_int32_t off, cntl, stat, cmd, match;

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