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fwohci.c (108530) fwohci.c (108642)
1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108530 2003-01-01 08:25:32Z simokawa $
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108642 2003-01-04 06:40:57Z simokawa $
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4

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522
523 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
524 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
525 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
526 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
527
528 fwohci_probe_phy(sc, dev);
529
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4

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522
523 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
524 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
525 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
526 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
527
528 fwohci_probe_phy(sc, dev);
529
530 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
530 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
531 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
532
533 /* enable link */
534 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
535 fw_busreset(&sc->fc);
531 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
532
533 /* enable link */
534 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
535 fw_busreset(&sc->fc);
536
537 /* force to start rx dma */
538 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
539 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
536 fwohci_rx_enable(sc, &sc->arrq);
537 fwohci_rx_enable(sc, &sc->arrs);
538
539 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
540 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
541 db_tr->xfer = NULL;
542 }
543 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;

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1101}
1102
1103static void
1104fwohci_db_init(struct fwohci_dbch *dbch)
1105{
1106 int idb;
1107 struct fwohcidb *db;
1108 struct fwohcidb_tr *db_tr;
540 fwohci_rx_enable(sc, &sc->arrq);
541 fwohci_rx_enable(sc, &sc->arrs);
542
543 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
544 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
545 db_tr->xfer = NULL;
546 }
547 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;

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1105}
1106
1107static void
1108fwohci_db_init(struct fwohci_dbch *dbch)
1109{
1110 int idb;
1111 struct fwohcidb *db;
1112 struct fwohcidb_tr *db_tr;
1113
1114
1115 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1116 goto out;
1117
1109 /* allocate DB entries and attach one to each DMA channels */
1110 /* DB entry must start at 16 bytes bounary. */
1118 /* allocate DB entries and attach one to each DMA channels */
1119 /* DB entry must start at 16 bytes bounary. */
1111 dbch->frag.buf = NULL;
1112 dbch->frag.len = 0;
1113 dbch->frag.plen = 0;
1114 dbch->xferq.queued = 0;
1115 dbch->pdb_tr = NULL;
1116
1117 STAILQ_INIT(&dbch->db_trq);
1118 db_tr = (struct fwohcidb_tr *)
1119 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1120 M_DEVBUF, M_DONTWAIT | M_ZERO);
1121 if(db_tr == NULL){
1120 STAILQ_INIT(&dbch->db_trq);
1121 db_tr = (struct fwohcidb_tr *)
1122 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1123 M_DEVBUF, M_DONTWAIT | M_ZERO);
1124 if(db_tr == NULL){
1122 printf("fwochi_db_init: malloc failed\n");
1125 printf("fwohci_db_init: malloc failed\n");
1123 return;
1124 }
1125 db = (struct fwohcidb *)
1126 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb,
1127 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul);
1128 if(db == NULL){
1126 return;
1127 }
1128 db = (struct fwohcidb *)
1129 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb,
1130 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul);
1131 if(db == NULL){
1129 printf("fwochi_db_init: contigmalloc failed\n");
1132 printf("fwohci_db_init: contigmalloc failed\n");
1130 free(db_tr, M_DEVBUF);
1131 return;
1132 }
1133 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb);
1134 /* Attach DB to DMA ch. */
1135 for(idb = 0 ; idb < dbch->ndb ; idb++){
1136 db_tr->dbcnt = 0;
1137 db_tr->db = &db[idb * dbch->ndesc];

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1145 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1146 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1147 ].end = (caddr_t)db_tr;
1148 }
1149 db_tr++;
1150 }
1151 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1152 = STAILQ_FIRST(&dbch->db_trq);
1133 free(db_tr, M_DEVBUF);
1134 return;
1135 }
1136 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb);
1137 /* Attach DB to DMA ch. */
1138 for(idb = 0 ; idb < dbch->ndb ; idb++){
1139 db_tr->dbcnt = 0;
1140 db_tr->db = &db[idb * dbch->ndesc];

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1148 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1149 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1150 ].end = (caddr_t)db_tr;
1151 }
1152 db_tr++;
1153 }
1154 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1155 = STAILQ_FIRST(&dbch->db_trq);
1156out:
1157 dbch->frag.buf = NULL;
1158 dbch->frag.len = 0;
1159 dbch->frag.plen = 0;
1160 dbch->xferq.queued = 0;
1161 dbch->pdb_tr = NULL;
1153 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1154 dbch->bottom = dbch->top;
1155 dbch->flags = FWOHCI_DBCH_INIT;
1156}
1157
1158static int
1159fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1160{

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1322 return err;
1323 }else{
1324 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1325 err = EBUSY;
1326 return err;
1327 }
1328 }
1329 dbch->xferq.flag |= FWXFERQ_RUNNING;
1162 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1163 dbch->bottom = dbch->top;
1164 dbch->flags = FWOHCI_DBCH_INIT;
1165}
1166
1167static int
1168fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1169{

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1331 return err;
1332 }else{
1333 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1334 err = EBUSY;
1335 return err;
1336 }
1337 }
1338 dbch->xferq.flag |= FWXFERQ_RUNNING;
1339 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1330 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1331 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1332 }
1333 db_tr = dbch->top;
1334 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1335 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1336 fwohci_add_rx_buf(db_tr,
1337 dbch->xferq.psize, dbch->xferq.flag, 0, NULL);

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1521 return err;
1522 }else{
1523 err = fwohci_irxbuf_enable(fc, dmach);
1524 return err;
1525 }
1526}
1527
1528int
1340 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1341 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1342 }
1343 db_tr = dbch->top;
1344 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1345 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1346 fwohci_add_rx_buf(db_tr,
1347 dbch->xferq.psize, dbch->xferq.flag, 0, NULL);

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1531 return err;
1532 }else{
1533 err = fwohci_irxbuf_enable(fc, dmach);
1534 return err;
1535 }
1536}
1537
1538int
1529fwohci_shutdown(device_t dev)
1539fwohci_shutdown(struct fwohci_softc *sc, device_t dev)
1530{
1531 u_int i;
1540{
1541 u_int i;
1532 struct fwohci_softc *sc = device_get_softc(dev);
1533
1534/* Now stopping all DMA channel */
1535 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1536 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1537 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1538 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1539
1540 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){

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1548/* Stop interrupt */
1549 OWRITE(sc, FWOHCI_INTMASKCLR,
1550 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1551 | OHCI_INT_PHY_INT
1552 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1553 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1554 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1555 | OHCI_INT_PHY_BUS_R);
1542
1543/* Now stopping all DMA channel */
1544 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1545 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1546 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1547 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1548
1549 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){

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1557/* Stop interrupt */
1558 OWRITE(sc, FWOHCI_INTMASKCLR,
1559 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1560 | OHCI_INT_PHY_INT
1561 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1562 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1563 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1564 | OHCI_INT_PHY_BUS_R);
1565/* XXX Link down? Bus reset? */
1556 return 0;
1557}
1558
1566 return 0;
1567}
1568
1569int
1570fwohci_resume(struct fwohci_softc *sc, device_t dev)
1571{
1572 int i;
1573
1574 fwohci_reset(sc, dev);
1575 /* XXX resume isochronus receive automatically. (how about TX?) */
1576 for(i = 0; i < sc->fc.nisodma; i ++) {
1577 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) {
1578 device_printf(sc->fc.dev,
1579 "resume iso receive ch: %d\n", i);
1580 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING;
1581 sc->fc.irx_enable(&sc->fc, i);
1582 }
1583 }
1584
1585 bus_generic_resume(dev);
1586 sc->fc.ibr(&sc->fc);
1587 return 0;
1588}
1589
1559#define ACK_ALL
1560static void
1561fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1562{
1563 u_int32_t irstat, itstat;
1564 u_int i;
1565 struct firewire_comm *fc = (struct firewire_comm *)sc;
1566

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1809
1810static void
1811fwohci_set_intr(struct firewire_comm *fc, int enable)
1812{
1813 struct fwohci_softc *sc;
1814
1815 sc = (struct fwohci_softc *)fc;
1816 if (bootverbose)
1590#define ACK_ALL
1591static void
1592fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1593{
1594 u_int32_t irstat, itstat;
1595 u_int i;
1596 struct firewire_comm *fc = (struct firewire_comm *)sc;
1597

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1840
1841static void
1842fwohci_set_intr(struct firewire_comm *fc, int enable)
1843{
1844 struct fwohci_softc *sc;
1845
1846 sc = (struct fwohci_softc *)fc;
1847 if (bootverbose)
1817 device_printf(sc->fc.dev, "fwochi_set_intr: %d\n", enable);
1848 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
1818 if (enable) {
1819 sc->intmask |= OHCI_INT_EN;
1820 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1821 } else {
1822 sc->intmask &= ~OHCI_INT_EN;
1823 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1824 }
1825}

--- 762 unchanged lines hidden --- 		1849 if (enable) {
1850 sc->intmask |= OHCI_INT_EN;
1851 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1852 } else {
1853 sc->intmask &= ~OHCI_INT_EN;
1854 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1855 }
1856}

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