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fwohci.c (106802) fwohci.c (107653)
1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 106802 2002-11-12 10:02:50Z simokawa $
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 107653 2002-12-06 02:17:30Z simokawa $
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4

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287#define OHCI_BUS_MANAGER_ID 0
288
289 OWRITE(sc, OHCI_CSR_DATA, node);
290 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
293 DELAY(100);
294 bm = OREAD(sc, OHCI_CSR_DATA);
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4

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287#define OHCI_BUS_MANAGER_ID 0
288
289 OWRITE(sc, OHCI_CSR_DATA, node);
290 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
293 DELAY(100);
294 bm = OREAD(sc, OHCI_CSR_DATA);
295 if((bm & 0x3f) == 0x3f){
296 printf("fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
295 if((bm & 0x3f) == 0x3f)
297 bm = node;
296 bm = node;
298 }else{
299 printf("fw_set_bus_manager: %d-X%d (loop=%d)\n", bm, node, i);
300 }
297 if (bootverbose)
298 device_printf(sc->fc.dev,
299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
301
302 return(bm);
303}
304
305static u_int32_t
306fwphy_rddata(struct fwohci_softc *sc, u_int addr)
307{
308 u_int32_t fun;

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466 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
467 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
468 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
469 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
470 }
471
472/* FLUSH FIFO and reset Transmitter/Reciever */
473 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
300
301 return(bm);
302}
303
304static u_int32_t
305fwphy_rddata(struct fwohci_softc *sc, u_int addr)
306{
307 u_int32_t fun;

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465 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
466 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
467 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
468 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
469 }
470
471/* FLUSH FIFO and reset Transmitter/Reciever */
472 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
474 device_printf(dev, "resetting OHCI...");
473 if (bootverbose)
474 device_printf(dev, "resetting OHCI...");
475 i = 0;
476 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
477 if (i++ > 100) break;
478 DELAY(1000);
479 }
475 i = 0;
476 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
477 if (i++ > 100) break;
478 DELAY(1000);
479 }
480 printf("done (%d)\n", i);
480 if (bootverbose)
481 printf("done (%d)\n", i);
481 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
482 /* XXX wait for SCLK. */
483 DELAY(100000);
484
485 reg = OREAD(sc, OHCI_BUS_OPT);
486 reg2 = reg | OHCI_BUSFNC;
487 /* XXX */
488 if (((reg & 0x0000f000) >> 12) < 10)
489 reg2 = (reg2 & 0xffff0fff) | (10 << 12);
482 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
483 /* XXX wait for SCLK. */
484 DELAY(100000);
485
486 reg = OREAD(sc, OHCI_BUS_OPT);
487 reg2 = reg | OHCI_BUSFNC;
488 /* XXX */
489 if (((reg & 0x0000f000) >> 12) < 10)
490 reg2 = (reg2 & 0xffff0fff) | (10 << 12);
490 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
491 if (bootverbose)
492 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
491 OWRITE(sc, OHCI_BUS_OPT, reg2);
492
493 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
494 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
495 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
496 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
497
498/*

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539
540 /* check programPhyEnable */
541 reg2 = fwphy_rddata(sc, 5);
542#if 0
543 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
544#else /* XXX force to enable 1394a */
545 if (e1394a) {
546#endif
493 OWRITE(sc, OHCI_BUS_OPT, reg2);
494
495 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
496 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
497 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
498 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
499
500/*

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541
542 /* check programPhyEnable */
543 reg2 = fwphy_rddata(sc, 5);
544#if 0
545 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
546#else /* XXX force to enable 1394a */
547 if (e1394a) {
548#endif
547 device_printf(dev, "Enable 1394a Enhancements\n");
549 if (bootverbose)
550 device_printf(dev,
551 "Enable 1394a Enhancements\n");
548 /* enable EAA EMC */
549 reg2 |= 0x03;
550 /* set aPhyEnhanceEnable */
551 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
552 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
553 } else {
554 /* for safe */
555 reg2 &= ~0x83;

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776 LAST_DB(dbch->pdb_tr, db);
777 db->db.desc.depend |= db_tr->dbcnt;
778 }
779 dbch->pdb_tr = db_tr;
780 db_tr = STAILQ_NEXT(db_tr, link);
781 if(db_tr != dbch->bottom){
782 goto txloop;
783 } else {
552 /* enable EAA EMC */
553 reg2 |= 0x03;
554 /* set aPhyEnhanceEnable */
555 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
556 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
557 } else {
558 /* for safe */
559 reg2 &= ~0x83;

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780 LAST_DB(dbch->pdb_tr, db);
781 db->db.desc.depend |= db_tr->dbcnt;
782 }
783 dbch->pdb_tr = db_tr;
784 db_tr = STAILQ_NEXT(db_tr, link);
785 if(db_tr != dbch->bottom){
786 goto txloop;
787 } else {
784 printf("fwohci_start: lack of db_trq\n");
788 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
785 dbch->flags |= FWOHCI_DBCH_FULL;
786 }
787kick:
788 if (firewire_debug) printf("kick\n");
789 /* kick asy q */
790
791 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
792 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
793 } else {
789 dbch->flags |= FWOHCI_DBCH_FULL;
790 }
791kick:
792 if (firewire_debug) printf("kick\n");
793 /* kick asy q */
794
795 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
796 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
797 } else {
794 printf("start AT DMA status=%x\n",
798 if (bootverbose)
799 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
795 OREAD(sc, OHCI_DMACTL(off)));
796 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment);
797 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
798 dbch->xferq.flag |= FWXFERQ_RUNNING;
799 }
800
801 dbch->top = db_tr;
802 splx(s);

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1715}
1716
1717static void
1718fwohci_set_intr(struct firewire_comm *fc, int enable)
1719{
1720 struct fwohci_softc *sc;
1721
1722 sc = (struct fwohci_softc *)fc;
800 OREAD(sc, OHCI_DMACTL(off)));
801 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment);
802 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
803 dbch->xferq.flag |= FWXFERQ_RUNNING;
804 }
805
806 dbch->top = db_tr;
807 splx(s);

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1720}
1721
1722static void
1723fwohci_set_intr(struct firewire_comm *fc, int enable)
1724{
1725 struct fwohci_softc *sc;
1726
1727 sc = (struct fwohci_softc *)fc;
1723 printf("fwochi_set_intr: %d\n", enable);
1728 if (bootverbose)
1729 device_printf(sc->fc.dev, "fwochi_set_intr: %d\n", enable);
1724 if (enable) {
1725 sc->intmask |= OHCI_INT_EN;
1726 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1727 } else {
1728 sc->intmask &= ~OHCI_INT_EN;
1729 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1730 }
1731}

--- 754 unchanged lines hidden --- 		1730 if (enable) {
1731 sc->intmask |= OHCI_INT_EN;
1732 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1733 } else {
1734 sc->intmask &= ~OHCI_INT_EN;
1735 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1736 }
1737}

--- 754 unchanged lines hidden ---