Cross Reference: /freebsd-11-stable/sys/dev/firewire/fwohci.c

Deleted Added

sdiff udiff text old ( 108527 ) new ( 108530 )

full compact

1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the acknowledgement as bellow:
15 *
16 * This product includes software developed by K. Kobayashi and H. Shimokawa
17 *
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *

33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108527 2003-01-01 04:23:54Z simokawa $

33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108530 2003-01-01 08:25:32Z simokawa $

34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4
42#define IRX_CH 0x24
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/types.h>
47#include <sys/mbuf.h>
48#include <sys/mman.h>
49#include <sys/socket.h>
50#include <sys/socketvar.h>
51#include <sys/signalvar.h>
52#include <sys/malloc.h>
53#include <sys/uio.h>
54#include <sys/sockio.h>
55#include <sys/bus.h>
56#include <sys/kernel.h>
57#include <sys/conf.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
61#include <sys/rman.h>
62
63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */
64#include <machine/clock.h>
65#include <pci/pcivar.h>
66#include <pci/pcireg.h>
67#include <vm/vm.h>
68#include <vm/vm_extern.h>
69#include <vm/pmap.h> /* for vtophys proto */
70
71#include <dev/firewire/firewire.h>
72#include <dev/firewire/firewirebusreg.h>
73#include <dev/firewire/firewirereg.h>
74#include <dev/firewire/fwohcireg.h>
75#include <dev/firewire/fwohcivar.h>
76#include <dev/firewire/firewire_phy.h>
77
78#undef OHCI_DEBUG
79
80static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
81 "STOR","LOAD","NOP ","STOP",};
82static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
83 "UNDEF","REG","SYS","DEV"};
84char fwohcicode[32][0x20]={
85 "No stat","Undef","long","miss Ack err",
86 "underrun","overrun","desc err", "data read err",
87 "data write err","bus reset","timeout","tcode err",
88 "Undef","Undef","unknown event","flushed",
89 "Undef","ack complete","ack pend","Undef",
90 "ack busy_X","ack busy_A","ack busy_B","Undef",
91 "Undef","Undef","Undef","ack tardy",
92 "Undef","ack data_err","ack type_err",""};
93#define MAX_SPEED 2
94extern char linkspeed[MAX_SPEED+1][0x10];
95extern int maxrec[MAX_SPEED+1];
96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
98
99static struct tcode_info tinfo[] = {
100/* hdr_len block flag*/
101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
103/* 2 WRES */ {12, FWTI_RES},
104/* 3 XXX */ { 0, 0},
105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
107/* 6 RRESQ */ {16, FWTI_RES},
108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
109/* 8 CYCS */ { 0, 0},
110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
113/* c XXX */ { 0, 0},
114/* d XXX */ { 0, 0},
115/* e PHY */ {12, FWTI_REQ},
116/* f XXX */ { 0, 0}
117};
118
119#define OHCI_WRITE_SIGMASK 0xffff0000
120#define OHCI_READ_SIGMASK 0xffff0000
121
122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
124
125static void fwohci_ibr __P((struct firewire_comm *));
126static void fwohci_db_init __P((struct fwohci_dbch *));
127static void fwohci_db_free __P((struct fwohci_dbch *));
128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *));
131static void fwohci_start_atq __P((struct firewire_comm *));
132static void fwohci_start_ats __P((struct firewire_comm *));
133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *));
134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *));
135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *));
136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *));
137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t));
138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t));
139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
141static int fwohci_irx_enable __P((struct firewire_comm *, int));
142static int fwohci_irxpp_enable __P((struct firewire_comm *, int));
143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int));
144static int fwohci_irx_disable __P((struct firewire_comm *, int));
145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *));
146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int));
147static int fwohci_itx_disable __P((struct firewire_comm *, int));
148static void fwohci_timeout __P((void *));
149static void fwohci_poll __P((struct firewire_comm *, int, int));
150static void fwohci_set_intr __P((struct firewire_comm *, int));
151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *));
152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *));
153static void dump_db __P((struct fwohci_softc *, u_int32_t));
154static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t));
155static void dump_dma __P((struct fwohci_softc *, u_int32_t));
156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *));
157static void fwohci_rbuf_update __P((struct fwohci_softc *, int));
158static void fwohci_tbuf_update __P((struct fwohci_softc *, int));
159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *));
160
161/*
162 * memory allocated for DMA programs
163 */
164#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
165
166/* #define NDB 1024 */
167#define NDB FWMAXQUEUE
168#define NDVDB (DVBUF * NDB)
169
170#define OHCI_VERSION 0x00
171#define OHCI_CROMHDR 0x18
172#define OHCI_BUS_OPT 0x20
173#define OHCI_BUSIRMC (1 << 31)
174#define OHCI_BUSCMC (1 << 30)
175#define OHCI_BUSISC (1 << 29)
176#define OHCI_BUSBMC (1 << 28)
177#define OHCI_BUSPMC (1 << 27)
178#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
179 OHCI_BUSBMC | OHCI_BUSPMC
180
181#define OHCI_EUID_HI 0x24
182#define OHCI_EUID_LO 0x28
183
184#define OHCI_CROMPTR 0x34
185#define OHCI_HCCCTL 0x50
186#define OHCI_HCCCTLCLR 0x54
187#define OHCI_AREQHI 0x100
188#define OHCI_AREQHICLR 0x104
189#define OHCI_AREQLO 0x108
190#define OHCI_AREQLOCLR 0x10c
191#define OHCI_PREQHI 0x110
192#define OHCI_PREQHICLR 0x114
193#define OHCI_PREQLO 0x118
194#define OHCI_PREQLOCLR 0x11c
195#define OHCI_PREQUPPER 0x120
196
197#define OHCI_SID_BUF 0x64
198#define OHCI_SID_CNT 0x68
199#define OHCI_SID_CNT_MASK 0xffc
200
201#define OHCI_IT_STAT 0x90
202#define OHCI_IT_STATCLR 0x94
203#define OHCI_IT_MASK 0x98
204#define OHCI_IT_MASKCLR 0x9c
205
206#define OHCI_IR_STAT 0xa0
207#define OHCI_IR_STATCLR 0xa4
208#define OHCI_IR_MASK 0xa8
209#define OHCI_IR_MASKCLR 0xac
210
211#define OHCI_LNKCTL 0xe0
212#define OHCI_LNKCTLCLR 0xe4
213
214#define OHCI_PHYACCESS 0xec
215#define OHCI_CYCLETIMER 0xf0
216
217#define OHCI_DMACTL(off) (off)
218#define OHCI_DMACTLCLR(off) (off + 4)
219#define OHCI_DMACMD(off) (off + 0xc)
220#define OHCI_DMAMATCH(off) (off + 0x10)
221
222#define OHCI_ATQOFF 0x180
223#define OHCI_ATQCTL OHCI_ATQOFF
224#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
225#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
226#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
227
228#define OHCI_ATSOFF 0x1a0
229#define OHCI_ATSCTL OHCI_ATSOFF
230#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
231#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
232#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
233
234#define OHCI_ARQOFF 0x1c0
235#define OHCI_ARQCTL OHCI_ARQOFF
236#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
237#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
238#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
239
240#define OHCI_ARSOFF 0x1e0
241#define OHCI_ARSCTL OHCI_ARSOFF
242#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
243#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
244#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
245
246#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
247#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
248#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
249#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
250
251#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
252#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
253#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
254#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
255#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
256
257d_ioctl_t fwohci_ioctl;
258
259/*
260 * Communication with PHY device
261 */
262static u_int32_t
263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
264{
265 u_int32_t fun;
266
267 addr &= 0xf;
268 data &= 0xff;
269
270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
271 OWRITE(sc, OHCI_PHYACCESS, fun);
272 DELAY(100);
273
274 return(fwphy_rddata( sc, addr));
275}
276
277static u_int32_t
278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
279{
280 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
281 int i;
282 u_int32_t bm;
283
284#define OHCI_CSR_DATA 0x0c
285#define OHCI_CSR_COMP 0x10
286#define OHCI_CSR_CONT 0x14
287#define OHCI_BUS_MANAGER_ID 0
288
289 OWRITE(sc, OHCI_CSR_DATA, node);
290 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
293 DELAY(100);
294 bm = OREAD(sc, OHCI_CSR_DATA);
295 if((bm & 0x3f) == 0x3f)
296 bm = node;
297 if (bootverbose)
298 device_printf(sc->fc.dev,
299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
300
301 return(bm);
302}
303
304static u_int32_t
305fwphy_rddata(struct fwohci_softc *sc, u_int addr)
306{
307 u_int32_t fun, stat;
308 u_int i, retry = 0;
309
310 addr &= 0xf;
311#define MAX_RETRY 100
312again:
313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
315 OWRITE(sc, OHCI_PHYACCESS, fun);
316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
317 fun = OREAD(sc, OHCI_PHYACCESS);
318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
319 break;
320 DELAY(1000);
321 }
322 if(i >= MAX_RETRY) {
323 device_printf(sc->fc.dev, "cannot read phy\n");
324#if 0
325 return 0; /* XXX */
326#else
327 if (++retry < MAX_RETRY) {
328 DELAY(1000);
329 goto again;
330 }
331#endif
332 }
333 /* Make sure that SCLK is started */
334 stat = OREAD(sc, FWOHCI_INTSTAT);
335 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
336 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
337 if (++retry < MAX_RETRY) {
338 DELAY(1000);
339 goto again;
340 }
341 }
342 if (bootverbose || retry >= MAX_RETRY)
343 device_printf(sc->fc.dev,
344 "fwphy_rddata: loop=%d, retry=%d\n", i, retry);
345#undef MAX_RETRY
346 return((fun >> PHYDEV_RDDATA )& 0xff);
347}
348/* Device specific ioctl. */
349int
350fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
351{
352 struct firewire_softc *sc;
353 struct fwohci_softc *fc;
354 int unit = DEV2UNIT(dev);
355 int err = 0;
356 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
357 u_int32_t *dmach = (u_int32_t *) data;
358
359 sc = devclass_get_softc(firewire_devclass, unit);
360 if(sc == NULL){
361 return(EINVAL);
362 }
363 fc = (struct fwohci_softc *)sc->fc;
364
365 if (!data)
366 return(EINVAL);
367
368 switch (cmd) {
369 case FWOHCI_WRREG:
370#define OHCI_MAX_REG 0x800
371 if(reg->addr <= OHCI_MAX_REG){
372 OWRITE(fc, reg->addr, reg->data);
373 reg->data = OREAD(fc, reg->addr);
374 }else{
375 err = EINVAL;
376 }
377 break;
378 case FWOHCI_RDREG:
379 if(reg->addr <= OHCI_MAX_REG){
380 reg->data = OREAD(fc, reg->addr);
381 }else{
382 err = EINVAL;
383 }
384 break;
385/* Read DMA descriptors for debug */
386 case DUMPDMA:
387 if(*dmach <= OHCI_MAX_DMA_CH ){
388 dump_dma(fc, *dmach);
389 dump_db(fc, *dmach);
390 }else{
391 err = EINVAL;
392 }
393 break;
394 default:
395 break;
396 }
397 return err;
398}
399

~~400~~int
~~401~~fwohci_init(struct fwohci_softc *sc, device_t dev)

400static int
401fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)

402{

~~403~~ int err = 0;

403 u_int32_t reg, reg2;
404 int e1394a = 1;
405/*
406 * probe PHY parameters
407 * 0. to prove PHY version, whether compliance of 1394a.
408 * 1. to probe maximum speed supported by the PHY and
409 * number of port supported by core-logic.
410 * It is not actually available port on your PC .
411 */
412 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
413#if 0
414 /* XXX wait for SCLK. */
415 DELAY(100000);
416#endif
417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
418
419 if((reg >> 5) != 7 ){
420 sc->fc.mode &= ~FWPHYASYST;
421 sc->fc.nport = reg & FW_PHY_NP;
422 sc->fc.speed = reg & FW_PHY_SPD >> 6;
423 if (sc->fc.speed > MAX_SPEED) {
424 device_printf(dev, "invalid speed %d (fixed to %d).\n",
425 sc->fc.speed, MAX_SPEED);
426 sc->fc.speed = MAX_SPEED;
427 }
428 sc->fc.maxrec = maxrec[sc->fc.speed];
429 device_printf(dev,
430 "Link 1394 only %s, %d ports, maxrec %d bytes.\n",
431 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec);
432 }else{
433 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
434 sc->fc.mode |= FWPHYASYST;
435 sc->fc.nport = reg & FW_PHY_NP;
436 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
437 if (sc->fc.speed > MAX_SPEED) {
438 device_printf(dev, "invalid speed %d (fixed to %d).\n",
439 sc->fc.speed, MAX_SPEED);
440 sc->fc.speed = MAX_SPEED;
441 }
442 sc->fc.maxrec = maxrec[sc->fc.speed];
443 device_printf(dev,
444 "Link 1394a available %s, %d ports, maxrec %d bytes.\n",
445 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec);
446
447 /* check programPhyEnable */
448 reg2 = fwphy_rddata(sc, 5);
449#if 0
450 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
451#else /* XXX force to enable 1394a */
452 if (e1394a) {
453#endif
454 if (bootverbose)
455 device_printf(dev,
456 "Enable 1394a Enhancements\n");
457 /* enable EAA EMC */
458 reg2 |= 0x03;
459 /* set aPhyEnhanceEnable */
460 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
461 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
462 } else {
463 /* for safe */
464 reg2 &= ~0x83;
465 }
466 reg2 = fwphy_wrdata(sc, 5, reg2);
467 }
468
469 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
470 if((reg >> 5) == 7 ){
471 reg = fwphy_rddata(sc, 4);
472 reg |= 1 << 6;
473 fwphy_wrdata(sc, 4, reg);
474 reg = fwphy_rddata(sc, 4);
475 }
476 return 0;
477}
478
479
480void
481fwohci_reset(struct fwohci_softc *sc, device_t dev)
482{

483 int i;
484 u_int32_t reg, reg2;
485 struct fwohcidb_tr *db_tr;

~~407~~ int e1394a = 1;

486

487/* Disable interrupt */
488 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
489
490/* Now stopping all DMA channel */
491 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
492 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
493 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
494 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
495
496 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
497 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
498 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
499 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
500 }
501
502/* FLUSH FIFO and reset Transmitter/Reciever */
503 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
504 if (bootverbose)
505 device_printf(dev, "resetting OHCI...");
506 i = 0;
507 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
508 if (i++ > 100) break;
509 DELAY(1000);
510 }
511 if (bootverbose)
512 printf("done (loop=%d)\n", i);
513
514 reg = OREAD(sc, OHCI_BUS_OPT);
515 reg2 = reg | OHCI_BUSFNC;
516 /* XXX */
517 if (((reg & 0x0000f000) >> 12) < 10)
518 reg2 = (reg2 & 0xffff0fff) | (10 << 12);
519 if (bootverbose)
520 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
521 OWRITE(sc, OHCI_BUS_OPT, reg2);
522
523 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
524 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
525 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
526 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
527
528 fwohci_probe_phy(sc, dev);
529
530 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
531 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
532
533 /* enable link */
534 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
535 fw_busreset(&sc->fc);
536 fwohci_rx_enable(sc, &sc->arrq);
537 fwohci_rx_enable(sc, &sc->arrs);
538
539 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
540 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
541 db_tr->xfer = NULL;
542 }
543 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
544 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
545 db_tr->xfer = NULL;
546 }
547
548 OWRITE(sc, FWOHCI_RETRY,
549 (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ;
550 OWRITE(sc, FWOHCI_INTMASK,
551 OHCI_INT_ERR | OHCI_INT_PHY_SID
552 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
553 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
554 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
555 fwohci_set_intr(&sc->fc, 1);
556
557 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
558 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
559}
560
561int
562fwohci_init(struct fwohci_softc *sc, device_t dev)
563{
564 int i;
565 u_int32_t reg;
566

567 reg = OREAD(sc, OHCI_VERSION);
568 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
569 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1);
570
571/* XXX: Available Isochrounous DMA channel probe */
572 for( i = 0 ; i < 0x20 ; i ++ ){
573 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN);
574 reg = OREAD(sc, OHCI_IRCTL(i));
575 if(!(reg & OHCI_CNTL_DMA_RUN)) break;
576 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN);
577 reg = OREAD(sc, OHCI_ITCTL(i));
578 if(!(reg & OHCI_CNTL_DMA_RUN)) break;
579 }
580 sc->fc.nisodma = i;
581 device_printf(dev, "No. of Isochronous channel is %d.\n", i);
582
583 sc->fc.arq = &sc->arrq.xferq;
584 sc->fc.ars = &sc->arrs.xferq;
585 sc->fc.atq = &sc->atrq.xferq;
586 sc->fc.ats = &sc->atrs.xferq;
587
588 sc->arrq.xferq.start = NULL;
589 sc->arrs.xferq.start = NULL;
590 sc->atrq.xferq.start = fwohci_start_atq;
591 sc->atrs.xferq.start = fwohci_start_ats;
592
593 sc->arrq.xferq.drain = NULL;
594 sc->arrs.xferq.drain = NULL;
595 sc->atrq.xferq.drain = fwohci_drain_atq;
596 sc->atrs.xferq.drain = fwohci_drain_ats;
597
598 sc->arrq.ndesc = 1;
599 sc->arrs.ndesc = 1;
600 sc->atrq.ndesc = 10;
601 sc->atrs.ndesc = 10 / 2;
602
603 sc->arrq.ndb = NDB;
604 sc->arrs.ndb = NDB / 2;
605 sc->atrq.ndb = NDB;
606 sc->atrs.ndb = NDB / 2;
607
608 sc->arrq.dummy = NULL;
609 sc->arrs.dummy = NULL;
610 sc->atrq.dummy = NULL;
611 sc->atrs.dummy = NULL;
612 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
613 sc->fc.it[i] = &sc->it[i].xferq;
614 sc->fc.ir[i] = &sc->ir[i].xferq;
615 sc->it[i].ndb = 0;
616 sc->ir[i].ndb = 0;
617 }
618
619 sc->fc.tcode = tinfo;
620
621 sc->cromptr = (u_int32_t *)
622 contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0);
623
624 if(sc->cromptr == NULL){
625 device_printf(dev, "cromptr alloc failed.");
626 return ENOMEM;
627 }
628 sc->fc.dev = dev;
629 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]);
630
631 sc->fc.config_rom[1] = 0x31333934;
632 sc->fc.config_rom[2] = 0xf000a002;
633 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
634 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
635 sc->fc.config_rom[5] = 0;
636 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
637
638 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
639

~~482~~
~~483~~ fw_init(&sc->fc);

640

~~485~~/* Disable interrupt */
~~486~~ OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
~~487~~
~~488~~/* Now stopping all DMA channel */
~~489~~ OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
~~490~~ OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
~~491~~ OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
~~492~~ OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
~~493~~
~~494~~ OWRITE(sc, OHCI_IR_MASKCLR, ~0);
~~495~~ for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
~~496~~ OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
~~497~~ OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
~~498~~ }
~~499~~
~~500~~/* FLUSH FIFO and reset Transmitter/Reciever */
~~501~~ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
~~502~~ if (bootverbose)
~~503~~ device_printf(dev, "resetting OHCI...");
~~504~~ i = 0;
~~505~~ while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
~~506~~ if (i++ > 100) break;
~~507~~ DELAY(1000);
~~508~~ }
~~509~~ if (bootverbose)
~~510~~ printf("done (loop=%d)\n", i);
~~511~~
~~512~~ reg = OREAD(sc, OHCI_BUS_OPT);
~~513~~ reg2 = reg | OHCI_BUSFNC;
~~514~~ /* XXX */
~~515~~ if (((reg & 0x0000f000) >> 12) < 10)
~~516~~ reg2 = (reg2 & 0xffff0fff) | (10 << 12);
~~517~~ if (bootverbose)
~~518~~ device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
~~519~~ OWRITE(sc, OHCI_BUS_OPT, reg2);
~~520~~
~~521~~ OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
~~522~~ OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
~~523~~ OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
~~524~~ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
~~525~~
~~526~~/*
~~527~~ * probe PHY parameters
~~528~~ * 0. to prove PHY version, whether compliance of 1394a.
~~529~~ * 1. to probe maximum speed supported by the PHY and
~~530~~ * number of port supported by core-logic.
~~531~~ * It is not actually available port on your PC .
~~532~~ */
~~533~~ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
~~534~~#if 0
~~535~~ /* XXX wait for SCLK. */
~~536~~ DELAY(100000);
~~537~~#endif
~~538~~ reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
~~539~~
~~540~~ if((reg >> 5) != 7 ){
~~541~~ sc->fc.mode &= ~FWPHYASYST;
~~542~~ sc->fc.nport = reg & FW_PHY_NP;
~~543~~ sc->fc.speed = reg & FW_PHY_SPD >> 6;
~~544~~ if (sc->fc.speed > MAX_SPEED) {
~~545~~ device_printf(dev, "invalid speed %d (fixed to %d).\n",
~~546~~ sc->fc.speed, MAX_SPEED);
~~547~~ sc->fc.speed = MAX_SPEED;
~~548~~ }
~~549~~ sc->fc.maxrec = maxrec[sc->fc.speed];
~~550~~ device_printf(dev,
~~551~~ "Link 1394 only %s, %d ports, maxrec %d bytes.\n",
~~552~~ linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec);
~~553~~ }else{
~~554~~ reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
~~555~~ sc->fc.mode |= FWPHYASYST;
~~556~~ sc->fc.nport = reg & FW_PHY_NP;
~~557~~ sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
~~558~~ if (sc->fc.speed > MAX_SPEED) {
~~559~~ device_printf(dev, "invalid speed %d (fixed to %d).\n",
~~560~~ sc->fc.speed, MAX_SPEED);
~~561~~ sc->fc.speed = MAX_SPEED;
~~562~~ }
~~563~~ sc->fc.maxrec = maxrec[sc->fc.speed];
~~564~~ device_printf(dev,
~~565~~ "Link 1394a available %s, %d ports, maxrec %d bytes.\n",
~~566~~ linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec);
~~567~~
~~568~~ /* check programPhyEnable */
~~569~~ reg2 = fwphy_rddata(sc, 5);
~~570~~#if 0
~~571~~ if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
~~572~~#else /* XXX force to enable 1394a */
~~573~~ if (e1394a) {
~~574~~#endif
~~575~~ if (bootverbose)
~~576~~ device_printf(dev,
~~577~~ "Enable 1394a Enhancements\n");
~~578~~ /* enable EAA EMC */
~~579~~ reg2 |= 0x03;
~~580~~ /* set aPhyEnhanceEnable */
~~581~~ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
~~582~~ OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
~~583~~ } else {
~~584~~ /* for safe */
~~585~~ reg2 &= ~0x83;
~~586~~ }
~~587~~ reg2 = fwphy_wrdata(sc, 5, reg2);
~~588~~ }
~~589~~
~~590~~ reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
~~591~~ if((reg >> 5) == 7 ){
~~592~~ reg = fwphy_rddata(sc, 4);
~~593~~ reg |= 1 << 6;
~~594~~ fwphy_wrdata(sc, 4, reg);
~~595~~ reg = fwphy_rddata(sc, 4);
~~596~~ }
~~597~~

641/* SID recieve buffer must allign 2^11 */
642#define OHCI_SIDSIZE (1 << 11)
643 sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE,
644 0x10000, 0xffffffff, OHCI_SIDSIZE);
645 if (sc->fc.sid_buf == NULL) {
646 device_printf(dev, "sid_buf alloc failed.\n");
647 return ENOMEM;
648 }
649

~~607~~ OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
~~608~~ sc->fc.sid_buf++;
~~609~~ OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
~~610~~

650

651 fwohci_db_init(&sc->arrq);
652 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
653 return ENOMEM;
654
655 fwohci_db_init(&sc->arrs);
656 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
657 return ENOMEM;
658
659 fwohci_db_init(&sc->atrq);
660 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
661 return ENOMEM;
662
663 fwohci_db_init(&sc->atrs);
664 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
665 return ENOMEM;
666
667 reg = OREAD(sc, FWOHCIGUID_H);
668 for( i = 0 ; i < 4 ; i ++){
669 sc->fc.eui[3 - i] = reg & 0xff;
670 reg = reg >> 8;
671 }
672 reg = OREAD(sc, FWOHCIGUID_L);
673 for( i = 0 ; i < 4 ; i ++){
674 sc->fc.eui[7 - i] = reg & 0xff;
675 reg = reg >> 8;
676 }
677 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
678 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3],
679 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]);
680 sc->fc.ioctl = fwohci_ioctl;
681 sc->fc.cyctimer = fwohci_cyctimer;
682 sc->fc.set_bmr = fwohci_set_bus_manager;
683 sc->fc.ibr = fwohci_ibr;
684 sc->fc.irx_enable = fwohci_irx_enable;
685 sc->fc.irx_disable = fwohci_irx_disable;
686
687 sc->fc.itx_enable = fwohci_itxbuf_enable;
688 sc->fc.itx_disable = fwohci_itx_disable;
689 sc->fc.irx_post = fwohci_irx_post;
690 sc->fc.itx_post = NULL;
691 sc->fc.timeout = fwohci_timeout;
692 sc->fc.poll = fwohci_poll;
693 sc->fc.set_intr = fwohci_set_intr;
694

~~655~~ /* enable link */
~~656~~ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
~~657~~ fw_busreset(&sc->fc);
~~658~~ fwohci_rx_enable(sc, &sc->arrq);
~~659~~ fwohci_rx_enable(sc, &sc->arrs);

695 fw_init(&sc->fc);
696 fwohci_reset(sc, dev);

697

~~661~~ for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
~~662~~ i ++, db_tr = STAILQ_NEXT(db_tr, link)){
~~663~~ db_tr->xfer = NULL;
~~664~~ }
~~665~~ for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
~~666~~ i ++, db_tr = STAILQ_NEXT(db_tr, link)){
~~667~~ db_tr->xfer = NULL;
~~668~~ }
~~669~~
~~670~~ OWRITE(sc, FWOHCI_RETRY,
~~671~~ (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ;
~~672~~ OWRITE(sc, FWOHCI_INTMASK,
~~673~~ OHCI_INT_ERR | OHCI_INT_PHY_SID
~~674~~ | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
~~675~~ | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
~~676~~ | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
~~677~~ fwohci_set_intr(&sc->fc, 1);
~~678~~
~~679~~ OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
~~680~~ OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
~~681~~
~~682~~ return err;

698 return 0;

699}
700
701void
702fwohci_timeout(void *arg)
703{
704 struct fwohci_softc *sc;
705
706 sc = (struct fwohci_softc *)arg;
707 sc->fc.timeouthandle = timeout(fwohci_timeout,
708 (void *)sc, FW_XFERTIMEOUT * hz * 10);
709}
710
711u_int32_t
712fwohci_cyctimer(struct firewire_comm *fc)
713{
714 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
715 return(OREAD(sc, OHCI_CYCLETIMER));
716}
717
718#define LAST_DB(dbtr, db) do { \
719 struct fwohcidb_tr *_dbtr = (dbtr); \
720 int _cnt = _dbtr->dbcnt; \
721 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
722} while (0)
723
724int
725fwohci_detach(struct fwohci_softc *sc, device_t dev)
726{
727 int i;
728
729 if (sc->fc.sid_buf != NULL)
730 contigfree((void *)(uintptr_t)sc->fc.sid_buf,
731 OHCI_SIDSIZE, M_DEVBUF);
732 if (sc->cromptr != NULL)
733 contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF);
734
735 fwohci_db_free(&sc->arrq);
736 fwohci_db_free(&sc->arrs);
737
738 fwohci_db_free(&sc->atrq);
739 fwohci_db_free(&sc->atrs);
740
741 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
742 fwohci_db_free(&sc->it[i]);
743 fwohci_db_free(&sc->ir[i]);
744 }
745
746 return 0;
747}
748
749static void
750fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
751{
752 int i, s;
753 int tcode, hdr_len, hdr_off, len;
754 int fsegment = -1;
755 u_int32_t off;
756 struct fw_xfer *xfer;
757 struct fw_pkt *fp;
758 volatile struct fwohci_txpkthdr *ohcifp;
759 struct fwohcidb_tr *db_tr;
760 volatile struct fwohcidb *db;
761 struct mbuf *m;
762 struct tcode_info *info;
763
764 if(&sc->atrq == dbch){
765 off = OHCI_ATQOFF;
766 }else if(&sc->atrs == dbch){
767 off = OHCI_ATSOFF;
768 }else{
769 return;
770 }
771
772 if (dbch->flags & FWOHCI_DBCH_FULL)
773 return;
774
775 s = splfw();
776 db_tr = dbch->top;
777txloop:
778 xfer = STAILQ_FIRST(&dbch->xferq.q);
779 if(xfer == NULL){
780 goto kick;
781 }
782 if(dbch->xferq.queued == 0 ){
783 device_printf(sc->fc.dev, "TX queue empty\n");
784 }
785 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
786 db_tr->xfer = xfer;
787 xfer->state = FWXF_START;
788 dbch->xferq.packets++;
789
790 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off);
791 tcode = fp->mode.common.tcode;
792
793 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
794 info = &tinfo[tcode];
795 hdr_len = hdr_off = info->hdr_len;
796 /* fw_asyreq must pass valid send.len */
797 len = xfer->send.len;
798 for( i = 0 ; i < hdr_off ; i+= 4){
799 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]);
800 }
801 ohcifp->mode.common.spd = xfer->spd;
802 if (tcode == FWTCODE_STREAM ){
803 hdr_len = 8;
804 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
805 } else if (tcode == FWTCODE_PHY) {
806 hdr_len = 12;
807 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]);
808 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]);
809 ohcifp->mode.common.spd = 0;
810 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
811 } else {
812 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst);
813 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
814 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
815 }
816 db = &db_tr->db[0];
817 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len;
818 db->db.desc.status = 0;
819/* Specify bound timer of asy. responce */
820 if(&sc->atrs == dbch){
821 db->db.desc.count
822 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13);
823 }
824
825 db_tr->dbcnt = 2;
826 db = &db_tr->db[db_tr->dbcnt];
827 if(len > hdr_off){
828 if (xfer->mbuf == NULL) {
829 db->db.desc.addr
830 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off;
831 db->db.desc.cmd
832 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff);
833 db->db.desc.status = 0;
834
835 db_tr->dbcnt++;
836 } else {
837 /* XXX we assume mbuf chain is shorter than ndesc */
838 m = xfer->mbuf;
839 do {
840 db->db.desc.addr
841 = vtophys(mtod(m, caddr_t));
842 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len;
843 db->db.desc.status = 0;
844 db++;
845 db_tr->dbcnt++;
846 m = m->m_next;
847 } while (m != NULL);
848 }
849 }
850 /* last db */
851 LAST_DB(db_tr, db);
852 db->db.desc.cmd |= OHCI_OUTPUT_LAST
853 | OHCI_INTERRUPT_ALWAYS
854 | OHCI_BRANCH_ALWAYS;
855 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db);
856
857 if(fsegment == -1 )
858 fsegment = db_tr->dbcnt;
859 if (dbch->pdb_tr != NULL) {
860 LAST_DB(dbch->pdb_tr, db);
861 db->db.desc.depend |= db_tr->dbcnt;
862 }
863 dbch->pdb_tr = db_tr;
864 db_tr = STAILQ_NEXT(db_tr, link);
865 if(db_tr != dbch->bottom){
866 goto txloop;
867 } else {
868 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
869 dbch->flags |= FWOHCI_DBCH_FULL;
870 }
871kick:
872 if (firewire_debug) printf("kick\n");
873 /* kick asy q */
874
875 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
876 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
877 } else {
878 if (bootverbose)
879 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
880 OREAD(sc, OHCI_DMACTL(off)));
881 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment);
882 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
883 dbch->xferq.flag |= FWXFERQ_RUNNING;
884 }
885
886 dbch->top = db_tr;
887 splx(s);
888 return;
889}
890
891static void
892fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer)
893{
894 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
895 fwohci_drain(&sc->fc, xfer, &(sc->atrq));
896 return;
897}
898
899static void
900fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer)
901{
902 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
903 fwohci_drain(&sc->fc, xfer, &(sc->atrs));
904 return;
905}
906
907static void
908fwohci_start_atq(struct firewire_comm *fc)
909{
910 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
911 fwohci_start( sc, &(sc->atrq));
912 return;
913}
914
915static void
916fwohci_start_ats(struct firewire_comm *fc)
917{
918 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
919 fwohci_start( sc, &(sc->atrs));
920 return;
921}
922
923void
924fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
925{
926 int s, err = 0;
927 struct fwohcidb_tr *tr;
928 volatile struct fwohcidb *db;
929 struct fw_xfer *xfer;
930 u_int32_t off;
931 u_int stat;
932 int packets;
933 struct firewire_comm *fc = (struct firewire_comm *)sc;
934 if(&sc->atrq == dbch){
935 off = OHCI_ATQOFF;
936 }else if(&sc->atrs == dbch){
937 off = OHCI_ATSOFF;
938 }else{
939 return;
940 }
941 s = splfw();
942 tr = dbch->bottom;
943 packets = 0;
944 while(dbch->xferq.queued > 0){
945 LAST_DB(tr, db);
946 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){
947 if (fc->status != FWBUSRESET)
948 /* maybe out of order?? */
949 goto out;
950 }
951 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) {
952#ifdef OHCI_DEBUG
953 dump_dma(sc, ch);
954 dump_db(sc, ch);
955#endif
956/* Stop DMA */
957 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
958 device_printf(sc->fc.dev, "force reset AT FIFO\n");
959 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
960 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
961 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
962 }
963 stat = db->db.desc.status & FWOHCIEV_MASK;
964 switch(stat){
965 case FWOHCIEV_ACKCOMPL:
966 case FWOHCIEV_ACKPEND:
967 err = 0;
968 break;
969 case FWOHCIEV_ACKBSA:
970 case FWOHCIEV_ACKBSB:
971 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
972 case FWOHCIEV_ACKBSX:
973 err = EBUSY;
974 break;
975 case FWOHCIEV_FLUSHED:
976 case FWOHCIEV_ACKTARD:
977 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
978 err = EAGAIN;
979 break;
980 case FWOHCIEV_MISSACK:
981 case FWOHCIEV_UNDRRUN:
982 case FWOHCIEV_OVRRUN:
983 case FWOHCIEV_DESCERR:
984 case FWOHCIEV_DTRDERR:
985 case FWOHCIEV_TIMEOUT:
986 case FWOHCIEV_TCODERR:
987 case FWOHCIEV_UNKNOWN:
988 case FWOHCIEV_ACKDERR:
989 case FWOHCIEV_ACKTERR:
990 default:
991 device_printf(sc->fc.dev, "txd err=%2x %s\n",
992 stat, fwohcicode[stat]);
993 err = EINVAL;
994 break;
995 }
996 if(tr->xfer != NULL){
997 xfer = tr->xfer;
998 xfer->state = FWXF_SENT;
999 if(err == EBUSY && fc->status != FWBUSRESET){
1000 xfer->state = FWXF_BUSY;
1001 switch(xfer->act_type){
1002 case FWACT_XFER:
1003 xfer->resp = err;
1004 if(xfer->retry_req != NULL){
1005 xfer->retry_req(xfer);
1006 }
1007 break;
1008 default:
1009 break;
1010 }
1011 } else if( stat != FWOHCIEV_ACKPEND){
1012 if (stat != FWOHCIEV_ACKCOMPL)
1013 xfer->state = FWXF_SENTERR;
1014 xfer->resp = err;
1015 switch(xfer->act_type){
1016 case FWACT_XFER:
1017 fw_xfer_done(xfer);
1018 break;
1019 default:
1020 break;
1021 }
1022 }
1023 dbch->xferq.queued --;
1024 }
1025 tr->xfer = NULL;
1026
1027 packets ++;
1028 tr = STAILQ_NEXT(tr, link);
1029 dbch->bottom = tr;
1030 }
1031out:
1032 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1033 printf("make free slot\n");
1034 dbch->flags &= ~FWOHCI_DBCH_FULL;
1035 fwohci_start(sc, dbch);
1036 }
1037 splx(s);
1038}
1039
1040static void
1041fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch)
1042{
1043 int i, s;
1044 struct fwohcidb_tr *tr;
1045
1046 if(xfer->state != FWXF_START) return;
1047
1048 s = splfw();
1049 tr = dbch->bottom;
1050 for( i = 0 ; i <= dbch->xferq.queued ; i ++){
1051 if(tr->xfer == xfer){
1052 s = splfw();
1053 tr->xfer = NULL;
1054 dbch->xferq.queued --;
1055#if 1
1056 /* XXX */
1057 if (tr == dbch->bottom)
1058 dbch->bottom = STAILQ_NEXT(tr, link);
1059#endif
1060 if (dbch->flags & FWOHCI_DBCH_FULL) {
1061 printf("fwohci_drain: make slot\n");
1062 dbch->flags &= ~FWOHCI_DBCH_FULL;
1063 fwohci_start((struct fwohci_softc *)fc, dbch);
1064 }
1065
1066 splx(s);
1067 break;
1068 }
1069 tr = STAILQ_NEXT(tr, link);
1070 }
1071 splx(s);
1072 return;
1073}
1074
1075static void
1076fwohci_db_free(struct fwohci_dbch *dbch)
1077{
1078 struct fwohcidb_tr *db_tr;
1079 int idb;
1080
1081 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1082 return;
1083
1084 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1085 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0;
1086 idb < dbch->ndb;
1087 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1088 if (db_tr->buf != NULL) {
1089 free(db_tr->buf, M_DEVBUF);
1090 db_tr->buf = NULL;
1091 }
1092 }
1093 }
1094 dbch->ndb = 0;
1095 db_tr = STAILQ_FIRST(&dbch->db_trq);
1096 contigfree((void *)(uintptr_t)(volatile void *)db_tr->db,
1097 sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF);
1098 free(db_tr, M_DEVBUF);
1099 STAILQ_INIT(&dbch->db_trq);
1100 dbch->flags &= ~FWOHCI_DBCH_INIT;
1101}
1102
1103static void
1104fwohci_db_init(struct fwohci_dbch *dbch)
1105{
1106 int idb;
1107 struct fwohcidb *db;
1108 struct fwohcidb_tr *db_tr;
1109 /* allocate DB entries and attach one to each DMA channels */
1110 /* DB entry must start at 16 bytes bounary. */
1111 dbch->frag.buf = NULL;
1112 dbch->frag.len = 0;
1113 dbch->frag.plen = 0;
1114 dbch->xferq.queued = 0;
1115 dbch->pdb_tr = NULL;
1116
1117 STAILQ_INIT(&dbch->db_trq);
1118 db_tr = (struct fwohcidb_tr *)
1119 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1120 M_DEVBUF, M_DONTWAIT | M_ZERO);
1121 if(db_tr == NULL){
1122 printf("fwochi_db_init: malloc failed\n");
1123 return;
1124 }
1125 db = (struct fwohcidb *)
1126 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb,
1127 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul);
1128 if(db == NULL){
1129 printf("fwochi_db_init: contigmalloc failed\n");
1130 free(db_tr, M_DEVBUF);
1131 return;
1132 }
1133 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb);
1134 /* Attach DB to DMA ch. */
1135 for(idb = 0 ; idb < dbch->ndb ; idb++){
1136 db_tr->dbcnt = 0;
1137 db_tr->db = &db[idb * dbch->ndesc];
1138 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);

~~1123~~ if(!(dbch->xferq.flag & FWXFERQ_PACKET) &&
~~1124~~ (idb % dbch->xferq.bnpacket == 0)){
~~1125~~ dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].start
~~1126~~ = (caddr_t)db_tr;

1139 if (!(dbch->xferq.flag & FWXFERQ_PACKET) &&
1140 dbch->xferq.bnpacket != 0) {
1141 /* XXX what thoes for? */
1142 if (idb % dbch->xferq.bnpacket == 0)
1143 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1144 ].start = (caddr_t)db_tr;
1145 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1146 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1147 ].end = (caddr_t)db_tr;

1148 }

~~1128~~ if((!(dbch->xferq.flag & FWXFERQ_PACKET)) &&
~~1129~~ ((idb + 1)% dbch->xferq.bnpacket == 0)){
~~1130~~ dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].end
~~1131~~ = (caddr_t)db_tr;
~~1132~~ }

1149 db_tr++;
1150 }
1151 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1152 = STAILQ_FIRST(&dbch->db_trq);
1153 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1154 dbch->bottom = dbch->top;
1155 dbch->flags = FWOHCI_DBCH_INIT;
1156}
1157
1158static int
1159fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1160{
1161 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1162 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1163 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1164 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1165 fwohci_db_free(&sc->it[dmach]);
1166 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1167 return 0;
1168}
1169
1170static int
1171fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1172{
1173 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1174
1175 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1176 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1177 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1178 if(sc->ir[dmach].dummy != NULL){
1179 free(sc->ir[dmach].dummy, M_DEVBUF);
1180 }
1181 sc->ir[dmach].dummy = NULL;
1182 fwohci_db_free(&sc->ir[dmach]);
1183 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1184 return 0;
1185}
1186
1187static void
1188fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1189{
1190 qld[0] = ntohl(qld[0]);
1191 return;
1192}
1193
1194static int
1195fwohci_irxpp_enable(struct firewire_comm *fc, int dmach)
1196{
1197 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1198 int err = 0;
1199 unsigned short tag, ich;
1200
1201 tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1202 ich = sc->ir[dmach].xferq.flag & 0x3f;
1203
1204#if 0
1205 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){
1206 wakeup(fc->ir[dmach]);
1207 return err;
1208 }
1209#endif
1210
1211 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1212 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1213 sc->ir[dmach].xferq.queued = 0;
1214 sc->ir[dmach].ndb = NDB;
1215 sc->ir[dmach].xferq.psize = FWPMAX_S400;
1216 sc->ir[dmach].ndesc = 1;
1217 fwohci_db_init(&sc->ir[dmach]);
1218 err = fwohci_rx_enable(sc, &sc->ir[dmach]);
1219 }
1220 if(err){
1221 device_printf(sc->fc.dev, "err in IRX setting\n");
1222 return err;
1223 }
1224 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1225 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1226 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1227 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1228 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1229 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000);
1230 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1231 OWRITE(sc, OHCI_IRCMD(dmach),
1232 vtophys(sc->ir[dmach].top->db) | 1);
1233 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1234 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1235 }
1236 return err;
1237}
1238
1239static int
1240fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1241{
1242 int err = 0;
1243 int idb, z, i, dmach = 0;
1244 u_int32_t off = NULL;
1245 struct fwohcidb_tr *db_tr;
1246
1247 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1248 err = EINVAL;
1249 return err;
1250 }
1251 z = dbch->ndesc;
1252 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1253 if( &sc->it[dmach] == dbch){
1254 off = OHCI_ITOFF(dmach);
1255 break;
1256 }
1257 }
1258 if(off == NULL){
1259 err = EINVAL;
1260 return err;
1261 }
1262 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1263 return err;
1264 dbch->xferq.flag |= FWXFERQ_RUNNING;
1265 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1266 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1267 }
1268 db_tr = dbch->top;
1269 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1270 fwohci_add_tx_buf(db_tr,
1271 dbch->xferq.psize, dbch->xferq.flag,
1272 dbch->xferq.buf + dbch->xferq.psize * idb);
1273 if(STAILQ_NEXT(db_tr, link) == NULL){
1274 break;
1275 }
1276 db_tr->db[0].db.desc.depend
1277 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1278 db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1279 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1280 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1281 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1282 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1283 |= OHCI_INTERRUPT_ALWAYS;
1284 db_tr->db[0].db.desc.depend &= ~0xf;
1285 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1286 ~0xf;
1287 }
1288 }
1289 db_tr = STAILQ_NEXT(db_tr, link);
1290 }
1291 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1292 return err;
1293}
1294
1295static int
1296fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1297{
1298 int err = 0;
1299 int idb, z, i, dmach = 0;
1300 u_int32_t off = NULL;
1301 struct fwohcidb_tr *db_tr;
1302
1303 z = dbch->ndesc;
1304 if(&sc->arrq == dbch){
1305 off = OHCI_ARQOFF;
1306 }else if(&sc->arrs == dbch){
1307 off = OHCI_ARSOFF;
1308 }else{
1309 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1310 if( &sc->ir[dmach] == dbch){
1311 off = OHCI_IROFF(dmach);
1312 break;
1313 }
1314 }
1315 }
1316 if(off == NULL){
1317 err = EINVAL;
1318 return err;
1319 }
1320 if(dbch->xferq.flag & FWXFERQ_STREAM){
1321 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1322 return err;
1323 }else{
1324 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1325 err = EBUSY;
1326 return err;
1327 }
1328 }
1329 dbch->xferq.flag |= FWXFERQ_RUNNING;
1330 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1331 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1332 }
1333 db_tr = dbch->top;
1334 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1335 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1336 fwohci_add_rx_buf(db_tr,
1337 dbch->xferq.psize, dbch->xferq.flag, 0, NULL);
1338 }else{
1339 fwohci_add_rx_buf(db_tr,
1340 dbch->xferq.psize, dbch->xferq.flag,
1341 dbch->xferq.buf + dbch->xferq.psize * idb,
1342 dbch->dummy + sizeof(u_int32_t) * idb);
1343 }
1344 if(STAILQ_NEXT(db_tr, link) == NULL){
1345 break;
1346 }
1347 db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1348 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1349 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1350 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1351 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1352 |= OHCI_INTERRUPT_ALWAYS;
1353 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1354 ~0xf;
1355 }
1356 }
1357 db_tr = STAILQ_NEXT(db_tr, link);
1358 }
1359 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1360 dbch->buf_offset = 0;
1361 if(dbch->xferq.flag & FWXFERQ_STREAM){
1362 return err;
1363 }else{
1364 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z);
1365 }
1366 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1367 return err;
1368}
1369
1370static int
1371fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1372{
1373 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1374 int err = 0;
1375 unsigned short tag, ich;
1376 struct fwohci_dbch *dbch;
1377 struct fw_pkt *fp;
1378 struct fwohcidb_tr *db_tr;
1379
1380 tag = (sc->it[dmach].xferq.flag >> 6) & 3;
1381 ich = sc->it[dmach].xferq.flag & 0x3f;
1382 dbch = &sc->it[dmach];
1383 if(dbch->ndb == 0){
1384 dbch->xferq.queued = 0;
1385 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk;
1386 dbch->ndesc = 3;
1387 fwohci_db_init(dbch);
1388 err = fwohci_tx_enable(sc, dbch);
1389 }
1390 if(err)
1391 return err;
1392 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){
1393 if(dbch->xferq.stdma2 != NULL){
1394 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1395 ((struct fwohcidb_tr *)
1396 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1397 |= OHCI_BRANCH_ALWAYS;
1398 ((struct fwohcidb_tr *)
1399 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1400 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1401 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1402 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1403 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1404 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1405 }
1406 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1407 fw_tbuf_update(&sc->fc, dmach, 0);
1408 if(dbch->xferq.stdma == NULL){
1409 return err;
1410 }
1411 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1412 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1413 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1414 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1415 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000);
1416 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma);
1417 if(dbch->xferq.stdma2 != NULL){
1418 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1419 ((struct fwohcidb_tr *)
1420 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1421 |= OHCI_BRANCH_ALWAYS;
1422 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1423 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1424 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1425 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1426 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1427 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1428 }else{
1429 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1430 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1431 }
1432 OWRITE(sc, OHCI_ITCMD(dmach),
1433 vtophys(((struct fwohcidb_tr *)
1434 (dbch->xferq.stdma->start))->db) | dbch->ndesc);
1435 if(dbch->xferq.flag & FWXFERQ_DV){
1436 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start;
1437 fp = (struct fw_pkt *)db_tr->buf;
1438 fp->mode.ld[2] = htonl(0x80000000 +
1439 ((fc->cyctimer(fc) + 0x3000) & 0xf000));
1440 }
1441
1442 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1443 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1444 }
1445 return err;
1446}
1447
1448static int
1449fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
1450{
1451 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1452 int err = 0;
1453 unsigned short tag, ich;
1454 tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1455 ich = sc->ir[dmach].xferq.flag & 0x3f;
1456 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1457
1458 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1459 sc->ir[dmach].xferq.queued = 0;
1460 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket *
1461 sc->ir[dmach].xferq.bnchunk;
1462 sc->ir[dmach].dummy =
1463 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb,
1464 M_DEVBUF, M_DONTWAIT);
1465 if(sc->ir[dmach].dummy == NULL){
1466 err = ENOMEM;
1467 return err;
1468 }
1469 sc->ir[dmach].ndesc = 2;
1470 fwohci_db_init(&sc->ir[dmach]);
1471 err = fwohci_rx_enable(sc, &sc->ir[dmach]);
1472 }
1473 if(err)
1474 return err;
1475
1476 if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){
1477 if(sc->ir[dmach].xferq.stdma2 != NULL){
1478 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend =
1479 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc;
1480 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend =
1481 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db);
1482 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1483 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1484 }
1485 }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)
1486 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){
1487 fw_rbuf_update(&sc->fc, dmach, 0);
1488
1489 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1490 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1491 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1492 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1493 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1494 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1495 if(sc->ir[dmach].xferq.stdma2 != NULL){
1496 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend =
1497 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc;
1498 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend =
1499 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db);
1500 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1501 }else{
1502 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf;
1503 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1504 }
1505 OWRITE(sc, OHCI_IRCMD(dmach),
1506 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc);
1507 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1508 }
1509 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1510 return err;
1511}
1512
1513static int
1514fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1515{
1516 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1517 int err = 0;
1518
1519 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){
1520 err = fwohci_irxpp_enable(fc, dmach);
1521 return err;
1522 }else{
1523 err = fwohci_irxbuf_enable(fc, dmach);
1524 return err;
1525 }
1526}
1527
1528int
1529fwohci_shutdown(device_t dev)
1530{
1531 u_int i;
1532 struct fwohci_softc *sc = device_get_softc(dev);
1533
1534/* Now stopping all DMA channel */
1535 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1536 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1537 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1538 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1539
1540 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1541 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1542 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1543 }
1544
1545/* FLUSH FIFO and reset Transmitter/Reciever */
1546 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1547
1548/* Stop interrupt */
1549 OWRITE(sc, FWOHCI_INTMASKCLR,
1550 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1551 | OHCI_INT_PHY_INT
1552 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1553 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1554 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1555 | OHCI_INT_PHY_BUS_R);
1556 return 0;
1557}
1558
1559#define ACK_ALL
1560static void
1561fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1562{
1563 u_int32_t irstat, itstat;
1564 u_int i;
1565 struct firewire_comm *fc = (struct firewire_comm *)sc;
1566
1567#ifdef OHCI_DEBUG
1568 if(stat & OREAD(sc, FWOHCI_INTMASK))
1569 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1570 stat & OHCI_INT_EN ? "DMA_EN ":"",
1571 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1572 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1573 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1574 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1575 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1576 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1577 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1578 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1579 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1580 stat & OHCI_INT_PHY_SID ? "SID ":"",
1581 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1582 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1583 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1584 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1585 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1586 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1587 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1588 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1589 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1590 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1591 stat, OREAD(sc, FWOHCI_INTMASK)
1592 );
1593#endif
1594/* Bus reset */
1595 if(stat & OHCI_INT_PHY_BUS_R ){
1596 device_printf(fc->dev, "BUS reset\n");
1597 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1598 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1599
1600 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1601 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1602 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1603 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1604
1605#if 0
1606 for( i = 0 ; i < fc->nisodma ; i ++ ){
1607 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1608 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1609 }
1610
1611#endif
1612 fw_busreset(fc);
1613
1614 /* XXX need to wait DMA to stop */
1615#ifndef ACK_ALL
1616 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1617#endif
1618#if 1
1619 /* pending all pre-bus_reset packets */
1620 fwohci_txd(sc, &sc->atrq);
1621 fwohci_txd(sc, &sc->atrs);
1622 fwohci_arcv(sc, &sc->arrs, -1);
1623 fwohci_arcv(sc, &sc->arrq, -1);
1624#endif
1625
1626
1627 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1628 /* XXX insecure ?? */
1629 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1630 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1631 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1632
1633 }
1634 if((stat & OHCI_INT_DMA_IR )){
1635#ifndef ACK_ALL
1636 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1637#endif
1638 irstat = OREAD(sc, OHCI_IR_STAT);
1639 OWRITE(sc, OHCI_IR_STATCLR, ~0);
1640 for(i = 0; i < fc->nisodma ; i++){
1641 if((irstat & (1 << i)) != 0){
1642 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){
1643 fwohci_ircv(sc, &sc->ir[i], count);
1644 }else{
1645 fwohci_rbuf_update(sc, i);
1646 }
1647 }
1648 }
1649 }
1650 if((stat & OHCI_INT_DMA_IT )){
1651#ifndef ACK_ALL
1652 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1653#endif
1654 itstat = OREAD(sc, OHCI_IT_STAT);
1655 OWRITE(sc, OHCI_IT_STATCLR, ~0);
1656 for(i = 0; i < fc->nisodma ; i++){
1657 if((itstat & (1 << i)) != 0){
1658 fwohci_tbuf_update(sc, i);
1659 }
1660 }
1661 }
1662 if((stat & OHCI_INT_DMA_PRRS )){
1663#ifndef ACK_ALL
1664 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1665#endif
1666#if 0
1667 dump_dma(sc, ARRS_CH);
1668 dump_db(sc, ARRS_CH);
1669#endif
1670 fwohci_arcv(sc, &sc->arrs, count);
1671 }
1672 if((stat & OHCI_INT_DMA_PRRQ )){
1673#ifndef ACK_ALL
1674 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1675#endif
1676#if 0
1677 dump_dma(sc, ARRQ_CH);
1678 dump_db(sc, ARRQ_CH);
1679#endif
1680 fwohci_arcv(sc, &sc->arrq, count);
1681 }
1682 if(stat & OHCI_INT_PHY_SID){
1683 caddr_t buf;
1684 int plen;
1685
1686#ifndef ACK_ALL
1687 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1688#endif
1689/*
1690** Checking whether the node is root or not. If root, turn on
1691** cycle master.
1692*/
1693 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID));
1694 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){
1695 printf("Bus reset failure\n");
1696 goto sidout;
1697 }
1698 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){
1699 printf("CYCLEMASTER mode\n");
1700 OWRITE(sc, OHCI_LNKCTL,
1701 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1702 }else{
1703 printf("non CYCLEMASTER mode\n");
1704 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1705 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1706 }
1707 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f;
1708
1709 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK;
1710 plen -= 4; /* chop control info */
1711 buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT);
1712 if(buf == NULL) goto sidout;

~~1697~~ bcopy((void *)(uintptr_t)(volatile void *)fc->sid_buf,

1713 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1),

1714 buf, plen);
1715 fw_sidrcv(fc, buf, plen, 0);
1716 }
1717sidout:
1718 if((stat & OHCI_INT_DMA_ATRQ )){
1719#ifndef ACK_ALL
1720 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1721#endif
1722 fwohci_txd(sc, &(sc->atrq));
1723 }
1724 if((stat & OHCI_INT_DMA_ATRS )){
1725#ifndef ACK_ALL
1726 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1727#endif
1728 fwohci_txd(sc, &(sc->atrs));
1729 }
1730 if((stat & OHCI_INT_PW_ERR )){
1731#ifndef ACK_ALL
1732 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1733#endif
1734 device_printf(fc->dev, "posted write error\n");
1735 }
1736 if((stat & OHCI_INT_ERR )){
1737#ifndef ACK_ALL
1738 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1739#endif
1740 device_printf(fc->dev, "unrecoverable error\n");
1741 }
1742 if((stat & OHCI_INT_PHY_INT)) {
1743#ifndef ACK_ALL
1744 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1745#endif
1746 device_printf(fc->dev, "phy int\n");
1747 }
1748
1749 return;
1750}
1751
1752void
1753fwohci_intr(void *arg)
1754{
1755 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1756 u_int32_t stat;
1757
1758 if (!(sc->intmask & OHCI_INT_EN)) {
1759 /* polling mode */
1760 return;
1761 }
1762
1763 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) {
1764 if (stat == 0xffffffff) {
1765 device_printf(sc->fc.dev,
1766 "device physically ejected?\n");
1767 return;
1768 }
1769#ifdef ACK_ALL
1770 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1771#endif
1772 fwohci_intr_body(sc, stat, -1);
1773 }
1774}
1775
1776static void
1777fwohci_poll(struct firewire_comm *fc, int quick, int count)
1778{
1779 int s;
1780 u_int32_t stat;
1781 struct fwohci_softc *sc;
1782
1783
1784 sc = (struct fwohci_softc *)fc;
1785 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
1786 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
1787 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
1788#if 0
1789 if (!quick) {
1790#else
1791 if (1) {
1792#endif
1793 stat = OREAD(sc, FWOHCI_INTSTAT);
1794 if (stat == 0)
1795 return;
1796 if (stat == 0xffffffff) {
1797 device_printf(sc->fc.dev,
1798 "device physically ejected?\n");
1799 return;
1800 }
1801#ifdef ACK_ALL
1802 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1803#endif
1804 }
1805 s = splfw();
1806 fwohci_intr_body(sc, stat, count);
1807 splx(s);
1808}
1809
1810static void
1811fwohci_set_intr(struct firewire_comm *fc, int enable)
1812{
1813 struct fwohci_softc *sc;
1814
1815 sc = (struct fwohci_softc *)fc;
1816 if (bootverbose)
1817 device_printf(sc->fc.dev, "fwochi_set_intr: %d\n", enable);
1818 if (enable) {
1819 sc->intmask |= OHCI_INT_EN;
1820 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1821 } else {
1822 sc->intmask &= ~OHCI_INT_EN;
1823 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1824 }
1825}
1826
1827static void
1828fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
1829{
1830 int stat;
1831 struct firewire_comm *fc = &sc->fc;
1832 struct fw_pkt *fp;
1833 struct fwohci_dbch *dbch;
1834 struct fwohcidb_tr *db_tr;
1835
1836 dbch = &sc->it[dmach];
1837 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){
1838 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start;
1839/*
1840 * Overwrite highest significant 4 bits timestamp information
1841 */
1842 fp = (struct fw_pkt *)db_tr->buf;
1843 fp->mode.ld[2] |= htonl(0x80000000 |
1844 ((fc->cyctimer(fc) + 0x4000) & 0xf000));
1845 }
1846 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f;
1847 switch(stat){
1848 case FWOHCIEV_ACKCOMPL:
1849 fw_tbuf_update(fc, dmach, 1);
1850 break;
1851 default:
1852 fw_tbuf_update(fc, dmach, 0);
1853 break;
1854 }
1855 fwohci_itxbuf_enable(&sc->fc, dmach);
1856}
1857
1858static void
1859fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
1860{
1861 int stat;
1862 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f;
1863 switch(stat){
1864 case FWOHCIEV_ACKCOMPL:
1865 fw_rbuf_update(&sc->fc, dmach, 1);
1866 wakeup(sc->fc.ir[dmach]);
1867 fwohci_irx_enable(&sc->fc, dmach);
1868 break;
1869 default:
1870 break;
1871 }
1872}
1873
1874void
1875dump_dma(struct fwohci_softc *sc, u_int32_t ch)
1876{
1877 u_int32_t off, cntl, stat, cmd, match;
1878
1879 if(ch == 0){
1880 off = OHCI_ATQOFF;
1881 }else if(ch == 1){
1882 off = OHCI_ATSOFF;
1883 }else if(ch == 2){
1884 off = OHCI_ARQOFF;
1885 }else if(ch == 3){
1886 off = OHCI_ARSOFF;
1887 }else if(ch < IRX_CH){
1888 off = OHCI_ITCTL(ch - ITX_CH);
1889 }else{
1890 off = OHCI_IRCTL(ch - IRX_CH);
1891 }
1892 cntl = stat = OREAD(sc, off);
1893 cmd = OREAD(sc, off + 0xc);
1894 match = OREAD(sc, off + 0x10);
1895
1896 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n",
1897 ch,
1898 cntl,
1899 stat,
1900 cmd,
1901 match);
1902 stat &= 0xffff ;
1903 if(stat & 0xff00){
1904 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
1905 ch,
1906 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
1907 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
1908 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
1909 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
1910 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
1911 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
1912 fwohcicode[stat & 0x1f],
1913 stat & 0x1f
1914 );
1915 }else{
1916 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
1917 }
1918}
1919
1920void
1921dump_db(struct fwohci_softc *sc, u_int32_t ch)
1922{
1923 struct fwohci_dbch *dbch;
1924 struct fwohcidb_tr *cp = NULL, *pp, *np;
1925 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL;
1926 int idb, jdb;
1927 u_int32_t cmd, off;
1928 if(ch == 0){
1929 off = OHCI_ATQOFF;
1930 dbch = &sc->atrq;
1931 }else if(ch == 1){
1932 off = OHCI_ATSOFF;
1933 dbch = &sc->atrs;
1934 }else if(ch == 2){
1935 off = OHCI_ARQOFF;
1936 dbch = &sc->arrq;
1937 }else if(ch == 3){
1938 off = OHCI_ARSOFF;
1939 dbch = &sc->arrs;
1940 }else if(ch < IRX_CH){
1941 off = OHCI_ITCTL(ch - ITX_CH);
1942 dbch = &sc->it[ch - ITX_CH];
1943 }else {
1944 off = OHCI_IRCTL(ch - IRX_CH);
1945 dbch = &sc->ir[ch - IRX_CH];
1946 }
1947 cmd = OREAD(sc, off + 0xc);
1948
1949 if( dbch->ndb == 0 ){
1950 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
1951 return;
1952 }
1953 pp = dbch->top;
1954 prev = pp->db;
1955 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
1956 if(pp == NULL){
1957 curr = NULL;
1958 goto outdb;
1959 }
1960 cp = STAILQ_NEXT(pp, link);
1961 if(cp == NULL){
1962 curr = NULL;
1963 goto outdb;
1964 }
1965 np = STAILQ_NEXT(cp, link);
1966 if(cp == NULL) break;
1967 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
1968 if((cmd & 0xfffffff0)
1969 == vtophys(&(cp->db[jdb]))){
1970 curr = cp->db;
1971 if(np != NULL){
1972 next = np->db;
1973 }else{
1974 next = NULL;
1975 }
1976 goto outdb;
1977 }
1978 }
1979 pp = STAILQ_NEXT(pp, link);
1980 prev = pp->db;
1981 }
1982outdb:
1983 if( curr != NULL){
1984 printf("Prev DB %d\n", ch);
1985 print_db(prev, ch, dbch->ndesc);
1986 printf("Current DB %d\n", ch);
1987 print_db(curr, ch, dbch->ndesc);
1988 printf("Next DB %d\n", ch);
1989 print_db(next, ch, dbch->ndesc);
1990 }else{
1991 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
1992 }
1993 return;
1994}
1995
1996void
1997print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max)
1998{
1999 fwohcireg_t stat;
2000 int i, key;
2001
2002 if(db == NULL){
2003 printf("No Descriptor is found\n");
2004 return;
2005 }
2006
2007 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2008 ch,
2009 "Current",
2010 "OP ",
2011 "KEY",
2012 "INT",
2013 "BR ",
2014 "len",
2015 "Addr",
2016 "Depend",
2017 "Stat",
2018 "Cnt");
2019 for( i = 0 ; i <= max ; i ++){
2020 key = db[i].db.desc.cmd & OHCI_KEY_MASK;
2021 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x",
2022 vtophys(&db[i]),
2023 dbcode[(db[i].db.desc.cmd >> 28) & 0xf],
2024 dbkey[(db[i].db.desc.cmd >> 24) & 0x7],
2025 dbcond[(db[i].db.desc.cmd >> 20) & 0x3],
2026 dbcond[(db[i].db.desc.cmd >> 18) & 0x3],
2027 db[i].db.desc.cmd & 0xffff,
2028 db[i].db.desc.addr,
2029 db[i].db.desc.depend,
2030 db[i].db.desc.status,
2031 db[i].db.desc.count);
2032 stat = db[i].db.desc.status;
2033 if(stat & 0xff00){
2034 printf(" %s%s%s%s%s%s %s(%x)\n",
2035 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2036 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2037 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2038 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2039 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2040 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2041 fwohcicode[stat & 0x1f],
2042 stat & 0x1f
2043 );
2044 }else{
2045 printf(" Nostat\n");
2046 }
2047 if(key == OHCI_KEY_ST2 ){
2048 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2049 db[i+1].db.immed[0],
2050 db[i+1].db.immed[1],
2051 db[i+1].db.immed[2],
2052 db[i+1].db.immed[3]);
2053 }
2054 if(key == OHCI_KEY_DEVICE){
2055 return;
2056 }
2057 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK)
2058 == OHCI_BRANCH_ALWAYS){
2059 return;
2060 }
2061 if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2062 == OHCI_OUTPUT_LAST){
2063 return;
2064 }
2065 if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2066 == OHCI_INPUT_LAST){
2067 return;
2068 }
2069 if(key == OHCI_KEY_ST2 ){
2070 i++;
2071 }
2072 }
2073 return;
2074}
2075
2076void
2077fwohci_ibr(struct firewire_comm *fc)
2078{
2079 struct fwohci_softc *sc;
2080 u_int32_t fun;
2081
2082 sc = (struct fwohci_softc *)fc;
2083
2084 /*
2085 * Set root hold-off bit so that non cyclemaster capable node
2086 * shouldn't became the root node.
2087 */
2088 fun = fwphy_rddata(sc, FW_PHY_RHB_REG);
2089 fun |= FW_PHY_RHB;
2090 fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun);
2091#if 1
2092 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2093 fun |= FW_PHY_IBR;
2094 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2095#else
2096 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2097 fun |= FW_PHY_ISBR;
2098 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2099#endif
2100}
2101
2102void
2103fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2104{
2105 struct fwohcidb_tr *db_tr, *fdb_tr;
2106 struct fwohci_dbch *dbch;
2107 struct fw_pkt *fp;
2108 volatile struct fwohci_txpkthdr *ohcifp;
2109 unsigned short chtag;
2110 int idb;
2111
2112 dbch = &sc->it[dmach];
2113 chtag = sc->it[dmach].xferq.flag & 0xff;
2114
2115 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2116 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2117/*
2118device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db));
2119*/
2120 if(bulkxfer->flag != 0){
2121 return;
2122 }
2123 bulkxfer->flag = 1;
2124 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){
2125 db_tr->db[0].db.desc.cmd
2126 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2127 fp = (struct fw_pkt *)db_tr->buf;
2128 ohcifp = (volatile struct fwohci_txpkthdr *)
2129 db_tr->db[1].db.immed;
2130 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]);
2131 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
2132 ohcifp->mode.stream.chtag = chtag;
2133 ohcifp->mode.stream.tcode = 0xa;
2134 ohcifp->mode.stream.spd = 4;
2135 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]);
2136 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]);
2137
2138 db_tr->db[2].db.desc.cmd
2139 = OHCI_OUTPUT_LAST
2140 | OHCI_UPDATE
2141 | OHCI_BRANCH_ALWAYS
2142 | ((ntohs(fp->mode.stream.len) ) & 0xffff);
2143 db_tr->db[2].db.desc.status = 0;
2144 db_tr->db[2].db.desc.count = 0;
2145 if(dbch->xferq.flag & FWXFERQ_DV){
2146 db_tr->db[0].db.desc.depend
2147 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2148 db_tr->db[dbch->ndesc - 1].db.desc.depend
2149 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2150 }else{
2151 db_tr->db[0].db.desc.depend
2152 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2153 db_tr->db[dbch->ndesc - 1].db.desc.depend
2154 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2155 }
2156 bulkxfer->end = (caddr_t)db_tr;
2157 db_tr = STAILQ_NEXT(db_tr, link);
2158 }
2159 db_tr = (struct fwohcidb_tr *)bulkxfer->end;
2160 db_tr->db[0].db.desc.depend &= ~0xf;
2161 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
2162/**/
2163 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS;
2164 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER;
2165/**/
2166 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS;
2167
2168 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2169 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2170/*
2171device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db));
2172*/
2173 return;
2174}
2175
2176static int
2177fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size,
2178 int mode, void *buf)
2179{
2180 volatile struct fwohcidb *db = db_tr->db;
2181 int err = 0;
2182 if(buf == 0){
2183 err = EINVAL;
2184 return err;
2185 }
2186 db_tr->buf = buf;
2187 db_tr->dbcnt = 3;
2188 db_tr->dummy = NULL;
2189
2190 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2191
2192 db[2].db.desc.depend = 0;
2193 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t);
2194 db[2].db.desc.cmd = OHCI_OUTPUT_MORE;
2195
2196 db[0].db.desc.status = 0;
2197 db[0].db.desc.count = 0;
2198
2199 db[2].db.desc.status = 0;
2200 db[2].db.desc.count = 0;
2201 if( mode & FWXFERQ_STREAM ){
2202 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST;
2203 if(mode & FWXFERQ_PACKET ){
2204 db[2].db.desc.cmd
2205 |= OHCI_INTERRUPT_ALWAYS;
2206 }
2207 }
2208 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2209 return 1;
2210}
2211
2212int
2213fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode,
2214 void *buf, void *dummy)
2215{
2216 volatile struct fwohcidb *db = db_tr->db;
2217 int i;
2218 void *dbuf[2];
2219 int dsiz[2];
2220
2221 if(buf == 0){
2222 buf = malloc(size, M_DEVBUF, M_NOWAIT);
2223 if(buf == NULL) return 0;
2224 db_tr->buf = buf;
2225 db_tr->dbcnt = 1;
2226 db_tr->dummy = NULL;
2227 dsiz[0] = size;
2228 dbuf[0] = buf;
2229 }else if(dummy == NULL){
2230 db_tr->buf = buf;
2231 db_tr->dbcnt = 1;
2232 db_tr->dummy = NULL;
2233 dsiz[0] = size;
2234 dbuf[0] = buf;
2235 }else{
2236 db_tr->buf = buf;
2237 db_tr->dbcnt = 2;
2238 db_tr->dummy = dummy;
2239 dsiz[0] = sizeof(u_int32_t);
2240 dsiz[1] = size;
2241 dbuf[0] = dummy;
2242 dbuf[1] = buf;
2243 }
2244 for(i = 0 ; i < db_tr->dbcnt ; i++){
2245 db[i].db.desc.addr = vtophys(dbuf[i]) ;
2246 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i];
2247 if( mode & FWXFERQ_STREAM ){
2248 db[i].db.desc.cmd |= OHCI_UPDATE;
2249 }
2250 db[i].db.desc.status = 0;
2251 db[i].db.desc.count = dsiz[i];
2252 }
2253 if( mode & FWXFERQ_STREAM ){
2254 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST;
2255 if(mode & FWXFERQ_PACKET ){
2256 db[db_tr->dbcnt - 1].db.desc.cmd
2257 |= OHCI_INTERRUPT_ALWAYS;
2258 }
2259 }
2260 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2261 return 1;
2262}
2263
2264static void
2265fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2266{
2267 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr;
2268 struct firewire_comm *fc = (struct firewire_comm *)sc;
2269 int z = 1;
2270 struct fw_pkt *fp;
2271 u_int8_t *ld;
2272 u_int32_t off = NULL;
2273 u_int32_t stat;
2274 u_int32_t *qld;
2275 u_int32_t reg;
2276 u_int spd;
2277 u_int dmach;
2278 int len, i, plen;
2279 caddr_t buf;
2280
2281 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
2282 if( &sc->ir[dmach] == dbch){
2283 off = OHCI_IROFF(dmach);
2284 break;
2285 }
2286 }
2287 if(off == NULL){
2288 return;
2289 }
2290 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){
2291 fwohci_irx_disable(&sc->fc, dmach);
2292 return;
2293 }
2294
2295 odb_tr = NULL;
2296 db_tr = dbch->top;
2297 i = 0;
2298 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) {
2299 if (count >= 0 && count-- == 0)
2300 break;
2301 ld = (u_int8_t *)db_tr->buf;
2302 if (dbch->xferq.flag & FWXFERQ_PACKET) {
2303 /* skip timeStamp */
2304 ld += sizeof(struct fwohci_trailer);
2305 }
2306 qld = (u_int32_t *)ld;
2307 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count);
2308/*
2309{
2310device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len,
2311 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]);
2312}
2313*/
2314 fp=(struct fw_pkt *)ld;
2315 qld[0] = htonl(qld[0]);
2316 plen = sizeof(struct fw_isohdr)
2317 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t);
2318 ld += plen;
2319 len -= plen;
2320 buf = db_tr->buf;
2321 db_tr->buf = NULL;
2322 stat = reg & 0x1f;
2323 spd = reg & 0x3;
2324 switch(stat){
2325 case FWOHCIEV_ACKCOMPL:
2326 case FWOHCIEV_ACKPEND:
2327 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd);
2328 break;
2329 default:
2330 free(buf, M_DEVBUF);
2331 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat);
2332 break;
2333 }
2334 i++;
2335 fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2336 dbch->xferq.flag, 0, NULL);
2337 db_tr->db[0].db.desc.depend &= ~0xf;
2338 if(dbch->pdb_tr != NULL){
2339 dbch->pdb_tr->db[0].db.desc.depend |= z;
2340 } else {
2341 /* XXX should be rewritten in better way */
2342 dbch->bottom->db[0].db.desc.depend |= z;
2343 }
2344 dbch->pdb_tr = db_tr;
2345 db_tr = STAILQ_NEXT(db_tr, link);
2346 }
2347 dbch->top = db_tr;
2348 reg = OREAD(sc, OHCI_DMACTL(off));
2349 if (reg & OHCI_CNTL_DMA_ACTIVE)
2350 return;
2351 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n",
2352 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i);
2353 dbch->top = db_tr;
2354 fwohci_irx_enable(fc, dmach);
2355}
2356
2357#define PLEN(x) (((ntohs(x))+0x3) & ~0x3)
2358static int
2359fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen)
2360{
2361 int i;
2362
2363 for( i = 4; i < hlen ; i+=4){
2364 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]);
2365 }
2366
2367 switch(fp->mode.common.tcode){
2368 case FWTCODE_RREQQ:
2369 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t);
2370 case FWTCODE_WRES:
2371 return sizeof(fp->mode.wres) + sizeof(u_int32_t);
2372 case FWTCODE_WREQQ:
2373 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t);
2374 case FWTCODE_RREQB:
2375 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t);
2376 case FWTCODE_RRESQ:
2377 return sizeof(fp->mode.rresq) + sizeof(u_int32_t);
2378 case FWTCODE_WREQB:
2379 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len)
2380 + sizeof(u_int32_t);
2381 case FWTCODE_LREQ:
2382 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len)
2383 + sizeof(u_int32_t);
2384 case FWTCODE_RRESB:
2385 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len)
2386 + sizeof(u_int32_t);
2387 case FWTCODE_LRES:
2388 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len)
2389 + sizeof(u_int32_t);
2390 case FWOHCITCODE_PHY:
2391 return 16;
2392 }
2393 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2394 return 0;
2395}
2396
2397static void
2398fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2399{
2400 struct fwohcidb_tr *db_tr;
2401 int z = 1;
2402 struct fw_pkt *fp;
2403 u_int8_t *ld;
2404 u_int32_t stat, off;
2405 u_int spd;
2406 int len, plen, hlen, pcnt, poff = 0, rlen;
2407 int s;
2408 caddr_t buf;
2409 int resCount;
2410
2411 if(&sc->arrq == dbch){
2412 off = OHCI_ARQOFF;
2413 }else if(&sc->arrs == dbch){
2414 off = OHCI_ARSOFF;
2415 }else{
2416 return;
2417 }
2418
2419 s = splfw();
2420 db_tr = dbch->top;
2421 pcnt = 0;
2422 /* XXX we cannot handle a packet which lies in more than two buf */
2423 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) {
2424 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset;
2425 resCount = db_tr->db[0].db.desc.count;
2426 len = dbch->xferq.psize - resCount
2427 - dbch->buf_offset;
2428 while (len > 0 ) {
2429 if (count >= 0 && count-- == 0)
2430 goto out;
2431 if(dbch->frag.buf != NULL){
2432 buf = dbch->frag.buf;
2433 if (dbch->frag.plen < 0) {
2434 /* incomplete header */
2435 int hlen;
2436
2437 hlen = - dbch->frag.plen;
2438 rlen = hlen - dbch->frag.len;
2439 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen);
2440 ld += rlen;
2441 len -= rlen;
2442 dbch->frag.len += rlen;
2443#if 0
2444 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2445#endif
2446 fp=(struct fw_pkt *)dbch->frag.buf;
2447 dbch->frag.plen
2448 = fwohci_get_plen(sc, fp, hlen);
2449 if (dbch->frag.plen == 0)
2450 goto out;
2451 }
2452 rlen = dbch->frag.plen - dbch->frag.len;
2453#if 0
2454 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2455#endif
2456 bcopy(ld, dbch->frag.buf + dbch->frag.len,
2457 rlen);
2458 ld += rlen;
2459 len -= rlen;
2460 plen = dbch->frag.plen;
2461 dbch->frag.buf = NULL;
2462 dbch->frag.plen = 0;
2463 dbch->frag.len = 0;
2464 poff = 0;
2465 }else{
2466 fp=(struct fw_pkt *)ld;
2467 fp->mode.ld[0] = htonl(fp->mode.ld[0]);
2468 switch(fp->mode.common.tcode){
2469 case FWTCODE_RREQQ:
2470 case FWTCODE_WRES:
2471 case FWTCODE_WREQQ:
2472 case FWTCODE_RRESQ:
2473 case FWOHCITCODE_PHY:
2474 hlen = 12;
2475 break;
2476 case FWTCODE_RREQB:
2477 case FWTCODE_WREQB:
2478 case FWTCODE_LREQ:
2479 case FWTCODE_RRESB:
2480 case FWTCODE_LRES:
2481 hlen = 16;
2482 break;
2483 default:
2484 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2485 goto out;
2486 }
2487 if (len >= hlen) {
2488 plen = fwohci_get_plen(sc, fp, hlen);
2489 if (plen == 0)
2490 goto out;
2491 plen = (plen + 3) & ~3;
2492 len -= plen;
2493 } else {
2494 plen = -hlen;
2495 len -= hlen;
2496 }
2497 if(resCount > 0 || len > 0){
2498 buf = malloc( dbch->xferq.psize,
2499 M_DEVBUF, M_NOWAIT);
2500 if(buf == NULL){
2501 printf("cannot malloc!\n");
2502 free(db_tr->buf, M_DEVBUF);
2503 goto out;
2504 }
2505 bcopy(ld, buf, plen);
2506 poff = 0;
2507 dbch->frag.buf = NULL;
2508 dbch->frag.plen = 0;
2509 dbch->frag.len = 0;
2510 }else if(len < 0){
2511 dbch->frag.buf = db_tr->buf;
2512 if (plen < 0) {
2513#if 0
2514 printf("plen < 0:"
2515 "hlen: %d len: %d\n",
2516 hlen, len);
2517#endif
2518 dbch->frag.len = hlen + len;
2519 dbch->frag.plen = -hlen;
2520 } else {
2521 dbch->frag.len = plen + len;
2522 dbch->frag.plen = plen;
2523 }
2524 bcopy(ld, db_tr->buf, dbch->frag.len);
2525 buf = NULL;
2526 }else{
2527 buf = db_tr->buf;
2528 poff = ld - (u_int8_t *)buf;
2529 dbch->frag.buf = NULL;
2530 dbch->frag.plen = 0;
2531 dbch->frag.len = 0;
2532 }
2533 ld += plen;
2534 }
2535 if( buf != NULL){
2536/* DMA result-code will be written at the tail of packet */
2537 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2538 spd = (stat >> 5) & 0x3;
2539 stat &= 0x1f;
2540 switch(stat){
2541 case FWOHCIEV_ACKPEND:
2542#if 0
2543 printf("fwohci_arcv: ack pending..\n");
2544#endif
2545 /* fall through */
2546 case FWOHCIEV_ACKCOMPL:
2547 if( poff != 0 )
2548 bcopy(buf+poff, buf, plen - 4);
2549 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd);
2550 break;
2551 case FWOHCIEV_BUSRST:
2552 free(buf, M_DEVBUF);
2553 if (sc->fc.status != FWBUSRESET)
2554 printf("got BUSRST packet!?\n");
2555 break;
2556 default:
2557 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2558#if 0 /* XXX */
2559 goto out;
2560#endif
2561 break;
2562 }
2563 }
2564 pcnt ++;
2565 };
2566out:
2567 if (resCount == 0) {
2568 /* done on this buffer */
2569 fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2570 dbch->xferq.flag, 0, NULL);
2571 dbch->bottom->db[0].db.desc.depend |= z;
2572 dbch->bottom = db_tr;
2573 db_tr = STAILQ_NEXT(db_tr, link);
2574 dbch->top = db_tr;
2575 dbch->buf_offset = 0;
2576 } else {
2577 dbch->buf_offset = dbch->xferq.psize - resCount;
2578 break;
2579 }
2580 /* XXX make sure DMA is not dead */
2581 }
2582#if 0
2583 if (pcnt < 1)
2584 printf("fwohci_arcv: no packets\n");
2585#endif
2586 splx(s);
2587}