1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
16 *
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
| 1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
16 *
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
|
34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 119289 2003-08-22 07:30:41Z simokawa $
| 34 * $FreeBSD: head/sys/dev/firewire/fwohci.c 120660 2003-10-02 04:06:56Z simokawa $
|
35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4
43#define IRX_CH 0x24
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/mbuf.h>
48#include <sys/malloc.h>
49#include <sys/sockio.h>
50#include <sys/bus.h>
51#include <sys/kernel.h>
52#include <sys/conf.h>
53#include <sys/endian.h>
54
55#include <machine/bus.h>
56
57#if __FreeBSD_version < 500000
58#include <machine/clock.h> /* for DELAY() */
59#endif
60
61#include <dev/firewire/firewire.h>
62#include <dev/firewire/firewirereg.h>
63#include <dev/firewire/fwdma.h>
64#include <dev/firewire/fwohcireg.h>
65#include <dev/firewire/fwohcivar.h>
66#include <dev/firewire/firewire_phy.h>
67
68#undef OHCI_DEBUG
69
70static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
71 "STOR","LOAD","NOP ","STOP",};
72
73static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
74 "UNDEF","REG","SYS","DEV"};
75static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
76char fwohcicode[32][0x20]={
77 "No stat","Undef","long","miss Ack err",
78 "underrun","overrun","desc err", "data read err",
79 "data write err","bus reset","timeout","tcode err",
80 "Undef","Undef","unknown event","flushed",
81 "Undef","ack complete","ack pend","Undef",
82 "ack busy_X","ack busy_A","ack busy_B","Undef",
83 "Undef","Undef","Undef","ack tardy",
84 "Undef","ack data_err","ack type_err",""};
85
86#define MAX_SPEED 3
87extern char linkspeed[][0x10];
88u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
89
90static struct tcode_info tinfo[] = {
91/* hdr_len block flag*/
92/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
93/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
94/* 2 WRES */ {12, FWTI_RES},
95/* 3 XXX */ { 0, 0},
96/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
97/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
98/* 6 RRESQ */ {16, FWTI_RES},
99/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
100/* 8 CYCS */ { 0, 0},
101/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
102/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
103/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
104/* c XXX */ { 0, 0},
105/* d XXX */ { 0, 0},
106/* e PHY */ {12, FWTI_REQ},
107/* f XXX */ { 0, 0}
108};
109
110#define OHCI_WRITE_SIGMASK 0xffff0000
111#define OHCI_READ_SIGMASK 0xffff0000
112
113#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
114#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
115
116static void fwohci_ibr __P((struct firewire_comm *));
117static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *));
118static void fwohci_db_free __P((struct fwohci_dbch *));
119static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
120static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *));
121static void fwohci_start_atq __P((struct firewire_comm *));
122static void fwohci_start_ats __P((struct firewire_comm *));
123static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *));
124static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t));
125static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t));
126static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
127static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
128static int fwohci_irx_enable __P((struct firewire_comm *, int));
129static int fwohci_irx_disable __P((struct firewire_comm *, int));
130#if BYTE_ORDER == BIG_ENDIAN
131static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *));
132#endif
133static int fwohci_itxbuf_enable __P((struct firewire_comm *, int));
134static int fwohci_itx_disable __P((struct firewire_comm *, int));
135static void fwohci_timeout __P((void *));
136static void fwohci_set_intr __P((struct firewire_comm *, int));
137
138static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *));
139static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int));
140static void dump_db __P((struct fwohci_softc *, u_int32_t));
| 35 *
36 */
37
38#define ATRQ_CH 0
39#define ATRS_CH 1
40#define ARRQ_CH 2
41#define ARRS_CH 3
42#define ITX_CH 4
43#define IRX_CH 0x24
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/mbuf.h>
48#include <sys/malloc.h>
49#include <sys/sockio.h>
50#include <sys/bus.h>
51#include <sys/kernel.h>
52#include <sys/conf.h>
53#include <sys/endian.h>
54
55#include <machine/bus.h>
56
57#if __FreeBSD_version < 500000
58#include <machine/clock.h> /* for DELAY() */
59#endif
60
61#include <dev/firewire/firewire.h>
62#include <dev/firewire/firewirereg.h>
63#include <dev/firewire/fwdma.h>
64#include <dev/firewire/fwohcireg.h>
65#include <dev/firewire/fwohcivar.h>
66#include <dev/firewire/firewire_phy.h>
67
68#undef OHCI_DEBUG
69
70static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
71 "STOR","LOAD","NOP ","STOP",};
72
73static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
74 "UNDEF","REG","SYS","DEV"};
75static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
76char fwohcicode[32][0x20]={
77 "No stat","Undef","long","miss Ack err",
78 "underrun","overrun","desc err", "data read err",
79 "data write err","bus reset","timeout","tcode err",
80 "Undef","Undef","unknown event","flushed",
81 "Undef","ack complete","ack pend","Undef",
82 "ack busy_X","ack busy_A","ack busy_B","Undef",
83 "Undef","Undef","Undef","ack tardy",
84 "Undef","ack data_err","ack type_err",""};
85
86#define MAX_SPEED 3
87extern char linkspeed[][0x10];
88u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
89
90static struct tcode_info tinfo[] = {
91/* hdr_len block flag*/
92/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
93/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
94/* 2 WRES */ {12, FWTI_RES},
95/* 3 XXX */ { 0, 0},
96/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
97/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
98/* 6 RRESQ */ {16, FWTI_RES},
99/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
100/* 8 CYCS */ { 0, 0},
101/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
102/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
103/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
104/* c XXX */ { 0, 0},
105/* d XXX */ { 0, 0},
106/* e PHY */ {12, FWTI_REQ},
107/* f XXX */ { 0, 0}
108};
109
110#define OHCI_WRITE_SIGMASK 0xffff0000
111#define OHCI_READ_SIGMASK 0xffff0000
112
113#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
114#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
115
116static void fwohci_ibr __P((struct firewire_comm *));
117static void fwohci_db_init __P((struct fwohci_softc *, struct fwohci_dbch *));
118static void fwohci_db_free __P((struct fwohci_dbch *));
119static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
120static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *));
121static void fwohci_start_atq __P((struct firewire_comm *));
122static void fwohci_start_ats __P((struct firewire_comm *));
123static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *));
124static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t));
125static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t));
126static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
127static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
128static int fwohci_irx_enable __P((struct firewire_comm *, int));
129static int fwohci_irx_disable __P((struct firewire_comm *, int));
130#if BYTE_ORDER == BIG_ENDIAN
131static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *));
132#endif
133static int fwohci_itxbuf_enable __P((struct firewire_comm *, int));
134static int fwohci_itx_disable __P((struct firewire_comm *, int));
135static void fwohci_timeout __P((void *));
136static void fwohci_set_intr __P((struct firewire_comm *, int));
137
138static int fwohci_add_rx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *));
139static int fwohci_add_tx_buf __P((struct fwohci_dbch *, struct fwohcidb_tr *, int));
140static void dump_db __P((struct fwohci_softc *, u_int32_t));
|
141static void print_db __P((struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t));
| 141static void print_db __P((struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t));
|
142static void dump_dma __P((struct fwohci_softc *, u_int32_t));
143static u_int32_t fwohci_cyctimer __P((struct firewire_comm *));
144static void fwohci_rbuf_update __P((struct fwohci_softc *, int));
145static void fwohci_tbuf_update __P((struct fwohci_softc *, int));
146void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *));
147#if FWOHCI_TASKQUEUE
148static void fwohci_complete(void *, int);
149#endif
150
151/*
152 * memory allocated for DMA programs
153 */
154#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
155
156#define NDB FWMAXQUEUE
157
158#define OHCI_VERSION 0x00
159#define OHCI_ATRETRY 0x08
160#define OHCI_CROMHDR 0x18
161#define OHCI_BUS_OPT 0x20
162#define OHCI_BUSIRMC (1 << 31)
163#define OHCI_BUSCMC (1 << 30)
164#define OHCI_BUSISC (1 << 29)
165#define OHCI_BUSBMC (1 << 28)
166#define OHCI_BUSPMC (1 << 27)
167#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
168 OHCI_BUSBMC | OHCI_BUSPMC
169
170#define OHCI_EUID_HI 0x24
171#define OHCI_EUID_LO 0x28
172
173#define OHCI_CROMPTR 0x34
174#define OHCI_HCCCTL 0x50
175#define OHCI_HCCCTLCLR 0x54
176#define OHCI_AREQHI 0x100
177#define OHCI_AREQHICLR 0x104
178#define OHCI_AREQLO 0x108
179#define OHCI_AREQLOCLR 0x10c
180#define OHCI_PREQHI 0x110
181#define OHCI_PREQHICLR 0x114
182#define OHCI_PREQLO 0x118
183#define OHCI_PREQLOCLR 0x11c
184#define OHCI_PREQUPPER 0x120
185
186#define OHCI_SID_BUF 0x64
187#define OHCI_SID_CNT 0x68
188#define OHCI_SID_ERR (1 << 31)
189#define OHCI_SID_CNT_MASK 0xffc
190
191#define OHCI_IT_STAT 0x90
192#define OHCI_IT_STATCLR 0x94
193#define OHCI_IT_MASK 0x98
194#define OHCI_IT_MASKCLR 0x9c
195
196#define OHCI_IR_STAT 0xa0
197#define OHCI_IR_STATCLR 0xa4
198#define OHCI_IR_MASK 0xa8
199#define OHCI_IR_MASKCLR 0xac
200
201#define OHCI_LNKCTL 0xe0
202#define OHCI_LNKCTLCLR 0xe4
203
204#define OHCI_PHYACCESS 0xec
205#define OHCI_CYCLETIMER 0xf0
206
207#define OHCI_DMACTL(off) (off)
208#define OHCI_DMACTLCLR(off) (off + 4)
209#define OHCI_DMACMD(off) (off + 0xc)
210#define OHCI_DMAMATCH(off) (off + 0x10)
211
212#define OHCI_ATQOFF 0x180
213#define OHCI_ATQCTL OHCI_ATQOFF
214#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
215#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
216#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
217
218#define OHCI_ATSOFF 0x1a0
219#define OHCI_ATSCTL OHCI_ATSOFF
220#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
221#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
222#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
223
224#define OHCI_ARQOFF 0x1c0
225#define OHCI_ARQCTL OHCI_ARQOFF
226#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
227#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
228#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
229
230#define OHCI_ARSOFF 0x1e0
231#define OHCI_ARSCTL OHCI_ARSOFF
232#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
233#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
234#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
235
236#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
237#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
238#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
239#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
240
241#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
242#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
243#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
244#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
245#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
246
247d_ioctl_t fwohci_ioctl;
248
249/*
250 * Communication with PHY device
251 */
252static u_int32_t
253fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
254{
255 u_int32_t fun;
256
257 addr &= 0xf;
258 data &= 0xff;
259
260 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
261 OWRITE(sc, OHCI_PHYACCESS, fun);
262 DELAY(100);
263
264 return(fwphy_rddata( sc, addr));
265}
266
267static u_int32_t
268fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
269{
270 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
271 int i;
272 u_int32_t bm;
273
274#define OHCI_CSR_DATA 0x0c
275#define OHCI_CSR_COMP 0x10
276#define OHCI_CSR_CONT 0x14
277#define OHCI_BUS_MANAGER_ID 0
278
279 OWRITE(sc, OHCI_CSR_DATA, node);
280 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
281 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
282 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
283 DELAY(10);
284 bm = OREAD(sc, OHCI_CSR_DATA);
285 if((bm & 0x3f) == 0x3f)
286 bm = node;
287 if (bootverbose)
288 device_printf(sc->fc.dev,
289 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
290
291 return(bm);
292}
293
294static u_int32_t
295fwphy_rddata(struct fwohci_softc *sc, u_int addr)
296{
297 u_int32_t fun, stat;
298 u_int i, retry = 0;
299
300 addr &= 0xf;
301#define MAX_RETRY 100
302again:
303 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
304 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
305 OWRITE(sc, OHCI_PHYACCESS, fun);
306 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
307 fun = OREAD(sc, OHCI_PHYACCESS);
308 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
309 break;
310 DELAY(100);
311 }
312 if(i >= MAX_RETRY) {
313 if (bootverbose)
314 device_printf(sc->fc.dev, "phy read failed(1).\n");
315 if (++retry < MAX_RETRY) {
316 DELAY(100);
317 goto again;
318 }
319 }
320 /* Make sure that SCLK is started */
321 stat = OREAD(sc, FWOHCI_INTSTAT);
322 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
323 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
324 if (bootverbose)
325 device_printf(sc->fc.dev, "phy read failed(2).\n");
326 if (++retry < MAX_RETRY) {
327 DELAY(100);
328 goto again;
329 }
330 }
331 if (bootverbose || retry >= MAX_RETRY)
332 device_printf(sc->fc.dev,
333 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
334#undef MAX_RETRY
335 return((fun >> PHYDEV_RDDATA )& 0xff);
336}
337/* Device specific ioctl. */
338int
339fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
340{
341 struct firewire_softc *sc;
342 struct fwohci_softc *fc;
343 int unit = DEV2UNIT(dev);
344 int err = 0;
345 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
346 u_int32_t *dmach = (u_int32_t *) data;
347
348 sc = devclass_get_softc(firewire_devclass, unit);
349 if(sc == NULL){
350 return(EINVAL);
351 }
352 fc = (struct fwohci_softc *)sc->fc;
353
354 if (!data)
355 return(EINVAL);
356
357 switch (cmd) {
358 case FWOHCI_WRREG:
359#define OHCI_MAX_REG 0x800
360 if(reg->addr <= OHCI_MAX_REG){
361 OWRITE(fc, reg->addr, reg->data);
362 reg->data = OREAD(fc, reg->addr);
363 }else{
364 err = EINVAL;
365 }
366 break;
367 case FWOHCI_RDREG:
368 if(reg->addr <= OHCI_MAX_REG){
369 reg->data = OREAD(fc, reg->addr);
370 }else{
371 err = EINVAL;
372 }
373 break;
374/* Read DMA descriptors for debug */
375 case DUMPDMA:
376 if(*dmach <= OHCI_MAX_DMA_CH ){
377 dump_dma(fc, *dmach);
378 dump_db(fc, *dmach);
379 }else{
380 err = EINVAL;
381 }
382 break;
383/* Read/Write Phy registers */
384#define OHCI_MAX_PHY_REG 0xf
385 case FWOHCI_RDPHYREG:
386 if (reg->addr <= OHCI_MAX_PHY_REG)
387 reg->data = fwphy_rddata(fc, reg->addr);
388 else
389 err = EINVAL;
390 break;
391 case FWOHCI_WRPHYREG:
392 if (reg->addr <= OHCI_MAX_PHY_REG)
393 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
394 else
395 err = EINVAL;
396 break;
397 default:
398 err = EINVAL;
399 break;
400 }
401 return err;
402}
403
404static int
405fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
406{
407 u_int32_t reg, reg2;
408 int e1394a = 1;
409/*
410 * probe PHY parameters
411 * 0. to prove PHY version, whether compliance of 1394a.
412 * 1. to probe maximum speed supported by the PHY and
413 * number of port supported by core-logic.
414 * It is not actually available port on your PC .
415 */
416 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
418
419 if((reg >> 5) != 7 ){
420 sc->fc.mode &= ~FWPHYASYST;
421 sc->fc.nport = reg & FW_PHY_NP;
422 sc->fc.speed = reg & FW_PHY_SPD >> 6;
423 if (sc->fc.speed > MAX_SPEED) {
424 device_printf(dev, "invalid speed %d (fixed to %d).\n",
425 sc->fc.speed, MAX_SPEED);
426 sc->fc.speed = MAX_SPEED;
427 }
428 device_printf(dev,
429 "Phy 1394 only %s, %d ports.\n",
430 linkspeed[sc->fc.speed], sc->fc.nport);
431 }else{
432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
433 sc->fc.mode |= FWPHYASYST;
434 sc->fc.nport = reg & FW_PHY_NP;
435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
436 if (sc->fc.speed > MAX_SPEED) {
437 device_printf(dev, "invalid speed %d (fixed to %d).\n",
438 sc->fc.speed, MAX_SPEED);
439 sc->fc.speed = MAX_SPEED;
440 }
441 device_printf(dev,
442 "Phy 1394a available %s, %d ports.\n",
443 linkspeed[sc->fc.speed], sc->fc.nport);
444
445 /* check programPhyEnable */
446 reg2 = fwphy_rddata(sc, 5);
447#if 0
448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
449#else /* XXX force to enable 1394a */
450 if (e1394a) {
451#endif
452 if (bootverbose)
453 device_printf(dev,
454 "Enable 1394a Enhancements\n");
455 /* enable EAA EMC */
456 reg2 |= 0x03;
457 /* set aPhyEnhanceEnable */
458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
460 } else {
461 /* for safe */
462 reg2 &= ~0x83;
463 }
464 reg2 = fwphy_wrdata(sc, 5, reg2);
465 }
466
467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
468 if((reg >> 5) == 7 ){
469 reg = fwphy_rddata(sc, 4);
470 reg |= 1 << 6;
471 fwphy_wrdata(sc, 4, reg);
472 reg = fwphy_rddata(sc, 4);
473 }
474 return 0;
475}
476
477
478void
479fwohci_reset(struct fwohci_softc *sc, device_t dev)
480{
481 int i, max_rec, speed;
482 u_int32_t reg, reg2;
483 struct fwohcidb_tr *db_tr;
484
485 /* Disable interrupt */
486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
487
488 /* Now stopping all DMA channel */
489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
493
494 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
498 }
499
500 /* FLUSH FIFO and reset Transmitter/Reciever */
501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
502 if (bootverbose)
503 device_printf(dev, "resetting OHCI...");
504 i = 0;
505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
506 if (i++ > 100) break;
507 DELAY(1000);
508 }
509 if (bootverbose)
510 printf("done (loop=%d)\n", i);
511
512 /* Probe phy */
513 fwohci_probe_phy(sc, dev);
514
515 /* Probe link */
516 reg = OREAD(sc, OHCI_BUS_OPT);
517 reg2 = reg | OHCI_BUSFNC;
518 max_rec = (reg & 0x0000f000) >> 12;
519 speed = (reg & 0x00000007);
520 device_printf(dev, "Link %s, max_rec %d bytes.\n",
521 linkspeed[speed], MAXREC(max_rec));
522 /* XXX fix max_rec */
523 sc->fc.maxrec = sc->fc.speed + 8;
524 if (max_rec != sc->fc.maxrec) {
525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
526 device_printf(dev, "max_rec %d -> %d\n",
527 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
528 }
529 if (bootverbose)
530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
531 OWRITE(sc, OHCI_BUS_OPT, reg2);
532
533 /* Initialize registers */
534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
535 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
538 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
540 fw_busreset(&sc->fc);
541
542 /* Enable link */
543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
544
545 /* Force to start async RX DMA */
546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
548 fwohci_rx_enable(sc, &sc->arrq);
549 fwohci_rx_enable(sc, &sc->arrs);
550
551 /* Initialize async TX */
552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
554
555 /* AT Retries */
556 OWRITE(sc, FWOHCI_RETRY,
557 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
558 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
559
560 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
561 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
562 sc->atrq.bottom = sc->atrq.top;
563 sc->atrs.bottom = sc->atrs.top;
564
565 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
566 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
567 db_tr->xfer = NULL;
568 }
569 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
570 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
571 db_tr->xfer = NULL;
572 }
573
574
575 /* Enable interrupt */
576 OWRITE(sc, FWOHCI_INTMASK,
577 OHCI_INT_ERR | OHCI_INT_PHY_SID
578 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
579 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
580 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
581 fwohci_set_intr(&sc->fc, 1);
582
583}
584
585int
586fwohci_init(struct fwohci_softc *sc, device_t dev)
587{
588 int i;
589 u_int32_t reg;
590 u_int8_t ui[8];
591
592#if FWOHCI_TASKQUEUE
593 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
594#endif
595
596 reg = OREAD(sc, OHCI_VERSION);
597 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
598 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1);
599
600 if (((reg>>16) & 0xff) < 1) {
601 device_printf(dev, "invalid OHCI version\n");
602 return (ENXIO);
603 }
604
605/* Available Isochrounous DMA channel probe */
606 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
607 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
608 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
609 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
610 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
611 for (i = 0; i < 0x20; i++)
612 if ((reg & (1 << i)) == 0)
613 break;
614 sc->fc.nisodma = i;
615 device_printf(dev, "No. of Isochronous channel is %d.\n", i);
616 if (i == 0)
617 return (ENXIO);
618
619 sc->fc.arq = &sc->arrq.xferq;
620 sc->fc.ars = &sc->arrs.xferq;
621 sc->fc.atq = &sc->atrq.xferq;
622 sc->fc.ats = &sc->atrs.xferq;
623
624 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
625 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
626 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
627 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
628
629 sc->arrq.xferq.start = NULL;
630 sc->arrs.xferq.start = NULL;
631 sc->atrq.xferq.start = fwohci_start_atq;
632 sc->atrs.xferq.start = fwohci_start_ats;
633
634 sc->arrq.xferq.buf = NULL;
635 sc->arrs.xferq.buf = NULL;
636 sc->atrq.xferq.buf = NULL;
637 sc->atrs.xferq.buf = NULL;
638
639 sc->arrq.xferq.dmach = -1;
640 sc->arrs.xferq.dmach = -1;
641 sc->atrq.xferq.dmach = -1;
642 sc->atrs.xferq.dmach = -1;
643
644 sc->arrq.ndesc = 1;
645 sc->arrs.ndesc = 1;
646 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */
647 sc->atrs.ndesc = 2;
648
649 sc->arrq.ndb = NDB;
650 sc->arrs.ndb = NDB / 2;
651 sc->atrq.ndb = NDB;
652 sc->atrs.ndb = NDB / 2;
653
654 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
655 sc->fc.it[i] = &sc->it[i].xferq;
656 sc->fc.ir[i] = &sc->ir[i].xferq;
657 sc->it[i].xferq.dmach = i;
658 sc->ir[i].xferq.dmach = i;
659 sc->it[i].ndb = 0;
660 sc->ir[i].ndb = 0;
661 }
662
663 sc->fc.tcode = tinfo;
664 sc->fc.dev = dev;
665
666 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
667 &sc->crom_dma, BUS_DMA_WAITOK);
668 if(sc->fc.config_rom == NULL){
669 device_printf(dev, "config_rom alloc failed.");
670 return ENOMEM;
671 }
672
673#if 0
674 bzero(&sc->fc.config_rom[0], CROMSIZE);
675 sc->fc.config_rom[1] = 0x31333934;
676 sc->fc.config_rom[2] = 0xf000a002;
677 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
678 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
679 sc->fc.config_rom[5] = 0;
680 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
681
682 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
683#endif
684
685
686/* SID recieve buffer must allign 2^11 */
687#define OHCI_SIDSIZE (1 << 11)
688 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
689 &sc->sid_dma, BUS_DMA_WAITOK);
690 if (sc->sid_buf == NULL) {
691 device_printf(dev, "sid_buf alloc failed.");
692 return ENOMEM;
693 }
694
695 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t),
696 &sc->dummy_dma, BUS_DMA_WAITOK);
697
698 if (sc->dummy_dma.v_addr == NULL) {
699 device_printf(dev, "dummy_dma alloc failed.");
700 return ENOMEM;
701 }
702
703 fwohci_db_init(sc, &sc->arrq);
704 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
705 return ENOMEM;
706
707 fwohci_db_init(sc, &sc->arrs);
708 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
709 return ENOMEM;
710
711 fwohci_db_init(sc, &sc->atrq);
712 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
713 return ENOMEM;
714
715 fwohci_db_init(sc, &sc->atrs);
716 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
717 return ENOMEM;
718
719 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
720 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
721 for( i = 0 ; i < 8 ; i ++)
722 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
723 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
724 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
725
726 sc->fc.ioctl = fwohci_ioctl;
727 sc->fc.cyctimer = fwohci_cyctimer;
728 sc->fc.set_bmr = fwohci_set_bus_manager;
729 sc->fc.ibr = fwohci_ibr;
730 sc->fc.irx_enable = fwohci_irx_enable;
731 sc->fc.irx_disable = fwohci_irx_disable;
732
733 sc->fc.itx_enable = fwohci_itxbuf_enable;
734 sc->fc.itx_disable = fwohci_itx_disable;
735#if BYTE_ORDER == BIG_ENDIAN
736 sc->fc.irx_post = fwohci_irx_post;
737#else
738 sc->fc.irx_post = NULL;
739#endif
740 sc->fc.itx_post = NULL;
741 sc->fc.timeout = fwohci_timeout;
742 sc->fc.poll = fwohci_poll;
743 sc->fc.set_intr = fwohci_set_intr;
744
745 sc->intmask = sc->irstat = sc->itstat = 0;
746
747 fw_init(&sc->fc);
748 fwohci_reset(sc, dev);
749
750 return 0;
751}
752
753void
754fwohci_timeout(void *arg)
755{
756 struct fwohci_softc *sc;
757
758 sc = (struct fwohci_softc *)arg;
759}
760
761u_int32_t
762fwohci_cyctimer(struct firewire_comm *fc)
763{
764 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
765 return(OREAD(sc, OHCI_CYCLETIMER));
766}
767
768int
769fwohci_detach(struct fwohci_softc *sc, device_t dev)
770{
771 int i;
772
773 if (sc->sid_buf != NULL)
774 fwdma_free(&sc->fc, &sc->sid_dma);
775 if (sc->fc.config_rom != NULL)
776 fwdma_free(&sc->fc, &sc->crom_dma);
777
778 fwohci_db_free(&sc->arrq);
779 fwohci_db_free(&sc->arrs);
780
781 fwohci_db_free(&sc->atrq);
782 fwohci_db_free(&sc->atrs);
783
784 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
785 fwohci_db_free(&sc->it[i]);
786 fwohci_db_free(&sc->ir[i]);
787 }
788
789 return 0;
790}
791
792#define LAST_DB(dbtr, db) do { \
793 struct fwohcidb_tr *_dbtr = (dbtr); \
794 int _cnt = _dbtr->dbcnt; \
795 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
796} while (0)
797
798static void
799fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
800{
801 struct fwohcidb_tr *db_tr;
| 142static void dump_dma __P((struct fwohci_softc *, u_int32_t));
143static u_int32_t fwohci_cyctimer __P((struct firewire_comm *));
144static void fwohci_rbuf_update __P((struct fwohci_softc *, int));
145static void fwohci_tbuf_update __P((struct fwohci_softc *, int));
146void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *));
147#if FWOHCI_TASKQUEUE
148static void fwohci_complete(void *, int);
149#endif
150
151/*
152 * memory allocated for DMA programs
153 */
154#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
155
156#define NDB FWMAXQUEUE
157
158#define OHCI_VERSION 0x00
159#define OHCI_ATRETRY 0x08
160#define OHCI_CROMHDR 0x18
161#define OHCI_BUS_OPT 0x20
162#define OHCI_BUSIRMC (1 << 31)
163#define OHCI_BUSCMC (1 << 30)
164#define OHCI_BUSISC (1 << 29)
165#define OHCI_BUSBMC (1 << 28)
166#define OHCI_BUSPMC (1 << 27)
167#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
168 OHCI_BUSBMC | OHCI_BUSPMC
169
170#define OHCI_EUID_HI 0x24
171#define OHCI_EUID_LO 0x28
172
173#define OHCI_CROMPTR 0x34
174#define OHCI_HCCCTL 0x50
175#define OHCI_HCCCTLCLR 0x54
176#define OHCI_AREQHI 0x100
177#define OHCI_AREQHICLR 0x104
178#define OHCI_AREQLO 0x108
179#define OHCI_AREQLOCLR 0x10c
180#define OHCI_PREQHI 0x110
181#define OHCI_PREQHICLR 0x114
182#define OHCI_PREQLO 0x118
183#define OHCI_PREQLOCLR 0x11c
184#define OHCI_PREQUPPER 0x120
185
186#define OHCI_SID_BUF 0x64
187#define OHCI_SID_CNT 0x68
188#define OHCI_SID_ERR (1 << 31)
189#define OHCI_SID_CNT_MASK 0xffc
190
191#define OHCI_IT_STAT 0x90
192#define OHCI_IT_STATCLR 0x94
193#define OHCI_IT_MASK 0x98
194#define OHCI_IT_MASKCLR 0x9c
195
196#define OHCI_IR_STAT 0xa0
197#define OHCI_IR_STATCLR 0xa4
198#define OHCI_IR_MASK 0xa8
199#define OHCI_IR_MASKCLR 0xac
200
201#define OHCI_LNKCTL 0xe0
202#define OHCI_LNKCTLCLR 0xe4
203
204#define OHCI_PHYACCESS 0xec
205#define OHCI_CYCLETIMER 0xf0
206
207#define OHCI_DMACTL(off) (off)
208#define OHCI_DMACTLCLR(off) (off + 4)
209#define OHCI_DMACMD(off) (off + 0xc)
210#define OHCI_DMAMATCH(off) (off + 0x10)
211
212#define OHCI_ATQOFF 0x180
213#define OHCI_ATQCTL OHCI_ATQOFF
214#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
215#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
216#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
217
218#define OHCI_ATSOFF 0x1a0
219#define OHCI_ATSCTL OHCI_ATSOFF
220#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
221#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
222#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
223
224#define OHCI_ARQOFF 0x1c0
225#define OHCI_ARQCTL OHCI_ARQOFF
226#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
227#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
228#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
229
230#define OHCI_ARSOFF 0x1e0
231#define OHCI_ARSCTL OHCI_ARSOFF
232#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
233#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
234#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
235
236#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
237#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
238#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
239#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
240
241#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
242#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
243#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
244#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
245#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
246
247d_ioctl_t fwohci_ioctl;
248
249/*
250 * Communication with PHY device
251 */
252static u_int32_t
253fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
254{
255 u_int32_t fun;
256
257 addr &= 0xf;
258 data &= 0xff;
259
260 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
261 OWRITE(sc, OHCI_PHYACCESS, fun);
262 DELAY(100);
263
264 return(fwphy_rddata( sc, addr));
265}
266
267static u_int32_t
268fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
269{
270 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
271 int i;
272 u_int32_t bm;
273
274#define OHCI_CSR_DATA 0x0c
275#define OHCI_CSR_COMP 0x10
276#define OHCI_CSR_CONT 0x14
277#define OHCI_BUS_MANAGER_ID 0
278
279 OWRITE(sc, OHCI_CSR_DATA, node);
280 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
281 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
282 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
283 DELAY(10);
284 bm = OREAD(sc, OHCI_CSR_DATA);
285 if((bm & 0x3f) == 0x3f)
286 bm = node;
287 if (bootverbose)
288 device_printf(sc->fc.dev,
289 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
290
291 return(bm);
292}
293
294static u_int32_t
295fwphy_rddata(struct fwohci_softc *sc, u_int addr)
296{
297 u_int32_t fun, stat;
298 u_int i, retry = 0;
299
300 addr &= 0xf;
301#define MAX_RETRY 100
302again:
303 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
304 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
305 OWRITE(sc, OHCI_PHYACCESS, fun);
306 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
307 fun = OREAD(sc, OHCI_PHYACCESS);
308 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
309 break;
310 DELAY(100);
311 }
312 if(i >= MAX_RETRY) {
313 if (bootverbose)
314 device_printf(sc->fc.dev, "phy read failed(1).\n");
315 if (++retry < MAX_RETRY) {
316 DELAY(100);
317 goto again;
318 }
319 }
320 /* Make sure that SCLK is started */
321 stat = OREAD(sc, FWOHCI_INTSTAT);
322 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
323 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
324 if (bootverbose)
325 device_printf(sc->fc.dev, "phy read failed(2).\n");
326 if (++retry < MAX_RETRY) {
327 DELAY(100);
328 goto again;
329 }
330 }
331 if (bootverbose || retry >= MAX_RETRY)
332 device_printf(sc->fc.dev,
333 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
334#undef MAX_RETRY
335 return((fun >> PHYDEV_RDDATA )& 0xff);
336}
337/* Device specific ioctl. */
338int
339fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
340{
341 struct firewire_softc *sc;
342 struct fwohci_softc *fc;
343 int unit = DEV2UNIT(dev);
344 int err = 0;
345 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
346 u_int32_t *dmach = (u_int32_t *) data;
347
348 sc = devclass_get_softc(firewire_devclass, unit);
349 if(sc == NULL){
350 return(EINVAL);
351 }
352 fc = (struct fwohci_softc *)sc->fc;
353
354 if (!data)
355 return(EINVAL);
356
357 switch (cmd) {
358 case FWOHCI_WRREG:
359#define OHCI_MAX_REG 0x800
360 if(reg->addr <= OHCI_MAX_REG){
361 OWRITE(fc, reg->addr, reg->data);
362 reg->data = OREAD(fc, reg->addr);
363 }else{
364 err = EINVAL;
365 }
366 break;
367 case FWOHCI_RDREG:
368 if(reg->addr <= OHCI_MAX_REG){
369 reg->data = OREAD(fc, reg->addr);
370 }else{
371 err = EINVAL;
372 }
373 break;
374/* Read DMA descriptors for debug */
375 case DUMPDMA:
376 if(*dmach <= OHCI_MAX_DMA_CH ){
377 dump_dma(fc, *dmach);
378 dump_db(fc, *dmach);
379 }else{
380 err = EINVAL;
381 }
382 break;
383/* Read/Write Phy registers */
384#define OHCI_MAX_PHY_REG 0xf
385 case FWOHCI_RDPHYREG:
386 if (reg->addr <= OHCI_MAX_PHY_REG)
387 reg->data = fwphy_rddata(fc, reg->addr);
388 else
389 err = EINVAL;
390 break;
391 case FWOHCI_WRPHYREG:
392 if (reg->addr <= OHCI_MAX_PHY_REG)
393 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
394 else
395 err = EINVAL;
396 break;
397 default:
398 err = EINVAL;
399 break;
400 }
401 return err;
402}
403
404static int
405fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
406{
407 u_int32_t reg, reg2;
408 int e1394a = 1;
409/*
410 * probe PHY parameters
411 * 0. to prove PHY version, whether compliance of 1394a.
412 * 1. to probe maximum speed supported by the PHY and
413 * number of port supported by core-logic.
414 * It is not actually available port on your PC .
415 */
416 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
418
419 if((reg >> 5) != 7 ){
420 sc->fc.mode &= ~FWPHYASYST;
421 sc->fc.nport = reg & FW_PHY_NP;
422 sc->fc.speed = reg & FW_PHY_SPD >> 6;
423 if (sc->fc.speed > MAX_SPEED) {
424 device_printf(dev, "invalid speed %d (fixed to %d).\n",
425 sc->fc.speed, MAX_SPEED);
426 sc->fc.speed = MAX_SPEED;
427 }
428 device_printf(dev,
429 "Phy 1394 only %s, %d ports.\n",
430 linkspeed[sc->fc.speed], sc->fc.nport);
431 }else{
432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
433 sc->fc.mode |= FWPHYASYST;
434 sc->fc.nport = reg & FW_PHY_NP;
435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
436 if (sc->fc.speed > MAX_SPEED) {
437 device_printf(dev, "invalid speed %d (fixed to %d).\n",
438 sc->fc.speed, MAX_SPEED);
439 sc->fc.speed = MAX_SPEED;
440 }
441 device_printf(dev,
442 "Phy 1394a available %s, %d ports.\n",
443 linkspeed[sc->fc.speed], sc->fc.nport);
444
445 /* check programPhyEnable */
446 reg2 = fwphy_rddata(sc, 5);
447#if 0
448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
449#else /* XXX force to enable 1394a */
450 if (e1394a) {
451#endif
452 if (bootverbose)
453 device_printf(dev,
454 "Enable 1394a Enhancements\n");
455 /* enable EAA EMC */
456 reg2 |= 0x03;
457 /* set aPhyEnhanceEnable */
458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
460 } else {
461 /* for safe */
462 reg2 &= ~0x83;
463 }
464 reg2 = fwphy_wrdata(sc, 5, reg2);
465 }
466
467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
468 if((reg >> 5) == 7 ){
469 reg = fwphy_rddata(sc, 4);
470 reg |= 1 << 6;
471 fwphy_wrdata(sc, 4, reg);
472 reg = fwphy_rddata(sc, 4);
473 }
474 return 0;
475}
476
477
478void
479fwohci_reset(struct fwohci_softc *sc, device_t dev)
480{
481 int i, max_rec, speed;
482 u_int32_t reg, reg2;
483 struct fwohcidb_tr *db_tr;
484
485 /* Disable interrupt */
486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
487
488 /* Now stopping all DMA channel */
489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
493
494 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
498 }
499
500 /* FLUSH FIFO and reset Transmitter/Reciever */
501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
502 if (bootverbose)
503 device_printf(dev, "resetting OHCI...");
504 i = 0;
505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
506 if (i++ > 100) break;
507 DELAY(1000);
508 }
509 if (bootverbose)
510 printf("done (loop=%d)\n", i);
511
512 /* Probe phy */
513 fwohci_probe_phy(sc, dev);
514
515 /* Probe link */
516 reg = OREAD(sc, OHCI_BUS_OPT);
517 reg2 = reg | OHCI_BUSFNC;
518 max_rec = (reg & 0x0000f000) >> 12;
519 speed = (reg & 0x00000007);
520 device_printf(dev, "Link %s, max_rec %d bytes.\n",
521 linkspeed[speed], MAXREC(max_rec));
522 /* XXX fix max_rec */
523 sc->fc.maxrec = sc->fc.speed + 8;
524 if (max_rec != sc->fc.maxrec) {
525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
526 device_printf(dev, "max_rec %d -> %d\n",
527 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
528 }
529 if (bootverbose)
530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
531 OWRITE(sc, OHCI_BUS_OPT, reg2);
532
533 /* Initialize registers */
534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
535 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
538 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
540 fw_busreset(&sc->fc);
541
542 /* Enable link */
543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
544
545 /* Force to start async RX DMA */
546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
548 fwohci_rx_enable(sc, &sc->arrq);
549 fwohci_rx_enable(sc, &sc->arrs);
550
551 /* Initialize async TX */
552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
554
555 /* AT Retries */
556 OWRITE(sc, FWOHCI_RETRY,
557 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
558 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
559
560 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
561 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
562 sc->atrq.bottom = sc->atrq.top;
563 sc->atrs.bottom = sc->atrs.top;
564
565 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
566 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
567 db_tr->xfer = NULL;
568 }
569 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
570 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
571 db_tr->xfer = NULL;
572 }
573
574
575 /* Enable interrupt */
576 OWRITE(sc, FWOHCI_INTMASK,
577 OHCI_INT_ERR | OHCI_INT_PHY_SID
578 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
579 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
580 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
581 fwohci_set_intr(&sc->fc, 1);
582
583}
584
585int
586fwohci_init(struct fwohci_softc *sc, device_t dev)
587{
588 int i;
589 u_int32_t reg;
590 u_int8_t ui[8];
591
592#if FWOHCI_TASKQUEUE
593 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
594#endif
595
596 reg = OREAD(sc, OHCI_VERSION);
597 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
598 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1);
599
600 if (((reg>>16) & 0xff) < 1) {
601 device_printf(dev, "invalid OHCI version\n");
602 return (ENXIO);
603 }
604
605/* Available Isochrounous DMA channel probe */
606 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
607 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
608 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
609 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
610 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
611 for (i = 0; i < 0x20; i++)
612 if ((reg & (1 << i)) == 0)
613 break;
614 sc->fc.nisodma = i;
615 device_printf(dev, "No. of Isochronous channel is %d.\n", i);
616 if (i == 0)
617 return (ENXIO);
618
619 sc->fc.arq = &sc->arrq.xferq;
620 sc->fc.ars = &sc->arrs.xferq;
621 sc->fc.atq = &sc->atrq.xferq;
622 sc->fc.ats = &sc->atrs.xferq;
623
624 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
625 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
626 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
627 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
628
629 sc->arrq.xferq.start = NULL;
630 sc->arrs.xferq.start = NULL;
631 sc->atrq.xferq.start = fwohci_start_atq;
632 sc->atrs.xferq.start = fwohci_start_ats;
633
634 sc->arrq.xferq.buf = NULL;
635 sc->arrs.xferq.buf = NULL;
636 sc->atrq.xferq.buf = NULL;
637 sc->atrs.xferq.buf = NULL;
638
639 sc->arrq.xferq.dmach = -1;
640 sc->arrs.xferq.dmach = -1;
641 sc->atrq.xferq.dmach = -1;
642 sc->atrs.xferq.dmach = -1;
643
644 sc->arrq.ndesc = 1;
645 sc->arrs.ndesc = 1;
646 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */
647 sc->atrs.ndesc = 2;
648
649 sc->arrq.ndb = NDB;
650 sc->arrs.ndb = NDB / 2;
651 sc->atrq.ndb = NDB;
652 sc->atrs.ndb = NDB / 2;
653
654 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
655 sc->fc.it[i] = &sc->it[i].xferq;
656 sc->fc.ir[i] = &sc->ir[i].xferq;
657 sc->it[i].xferq.dmach = i;
658 sc->ir[i].xferq.dmach = i;
659 sc->it[i].ndb = 0;
660 sc->ir[i].ndb = 0;
661 }
662
663 sc->fc.tcode = tinfo;
664 sc->fc.dev = dev;
665
666 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
667 &sc->crom_dma, BUS_DMA_WAITOK);
668 if(sc->fc.config_rom == NULL){
669 device_printf(dev, "config_rom alloc failed.");
670 return ENOMEM;
671 }
672
673#if 0
674 bzero(&sc->fc.config_rom[0], CROMSIZE);
675 sc->fc.config_rom[1] = 0x31333934;
676 sc->fc.config_rom[2] = 0xf000a002;
677 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
678 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
679 sc->fc.config_rom[5] = 0;
680 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
681
682 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
683#endif
684
685
686/* SID recieve buffer must allign 2^11 */
687#define OHCI_SIDSIZE (1 << 11)
688 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
689 &sc->sid_dma, BUS_DMA_WAITOK);
690 if (sc->sid_buf == NULL) {
691 device_printf(dev, "sid_buf alloc failed.");
692 return ENOMEM;
693 }
694
695 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t),
696 &sc->dummy_dma, BUS_DMA_WAITOK);
697
698 if (sc->dummy_dma.v_addr == NULL) {
699 device_printf(dev, "dummy_dma alloc failed.");
700 return ENOMEM;
701 }
702
703 fwohci_db_init(sc, &sc->arrq);
704 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
705 return ENOMEM;
706
707 fwohci_db_init(sc, &sc->arrs);
708 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
709 return ENOMEM;
710
711 fwohci_db_init(sc, &sc->atrq);
712 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
713 return ENOMEM;
714
715 fwohci_db_init(sc, &sc->atrs);
716 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
717 return ENOMEM;
718
719 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
720 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
721 for( i = 0 ; i < 8 ; i ++)
722 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
723 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
724 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
725
726 sc->fc.ioctl = fwohci_ioctl;
727 sc->fc.cyctimer = fwohci_cyctimer;
728 sc->fc.set_bmr = fwohci_set_bus_manager;
729 sc->fc.ibr = fwohci_ibr;
730 sc->fc.irx_enable = fwohci_irx_enable;
731 sc->fc.irx_disable = fwohci_irx_disable;
732
733 sc->fc.itx_enable = fwohci_itxbuf_enable;
734 sc->fc.itx_disable = fwohci_itx_disable;
735#if BYTE_ORDER == BIG_ENDIAN
736 sc->fc.irx_post = fwohci_irx_post;
737#else
738 sc->fc.irx_post = NULL;
739#endif
740 sc->fc.itx_post = NULL;
741 sc->fc.timeout = fwohci_timeout;
742 sc->fc.poll = fwohci_poll;
743 sc->fc.set_intr = fwohci_set_intr;
744
745 sc->intmask = sc->irstat = sc->itstat = 0;
746
747 fw_init(&sc->fc);
748 fwohci_reset(sc, dev);
749
750 return 0;
751}
752
753void
754fwohci_timeout(void *arg)
755{
756 struct fwohci_softc *sc;
757
758 sc = (struct fwohci_softc *)arg;
759}
760
761u_int32_t
762fwohci_cyctimer(struct firewire_comm *fc)
763{
764 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
765 return(OREAD(sc, OHCI_CYCLETIMER));
766}
767
768int
769fwohci_detach(struct fwohci_softc *sc, device_t dev)
770{
771 int i;
772
773 if (sc->sid_buf != NULL)
774 fwdma_free(&sc->fc, &sc->sid_dma);
775 if (sc->fc.config_rom != NULL)
776 fwdma_free(&sc->fc, &sc->crom_dma);
777
778 fwohci_db_free(&sc->arrq);
779 fwohci_db_free(&sc->arrs);
780
781 fwohci_db_free(&sc->atrq);
782 fwohci_db_free(&sc->atrs);
783
784 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
785 fwohci_db_free(&sc->it[i]);
786 fwohci_db_free(&sc->ir[i]);
787 }
788
789 return 0;
790}
791
792#define LAST_DB(dbtr, db) do { \
793 struct fwohcidb_tr *_dbtr = (dbtr); \
794 int _cnt = _dbtr->dbcnt; \
795 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
796} while (0)
797
798static void
799fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
800{
801 struct fwohcidb_tr *db_tr;
|
802 volatile struct fwohcidb *db;
| 802 struct fwohcidb *db;
|
803 bus_dma_segment_t *s;
804 int i;
805
806 db_tr = (struct fwohcidb_tr *)arg;
807 db = &db_tr->db[db_tr->dbcnt];
808 if (error) {
809 if (firewire_debug || error != EFBIG)
810 printf("fwohci_execute_db: error=%d\n", error);
811 return;
812 }
813 for (i = 0; i < nseg; i++) {
814 s = &segs[i];
815 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
816 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
817 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
818 db++;
819 db_tr->dbcnt++;
820 }
821}
822
823static void
824fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
825 bus_size_t size, int error)
826{
827 fwohci_execute_db(arg, segs, nseg, error);
828}
829
830static void
831fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
832{
833 int i, s;
| 803 bus_dma_segment_t *s;
804 int i;
805
806 db_tr = (struct fwohcidb_tr *)arg;
807 db = &db_tr->db[db_tr->dbcnt];
808 if (error) {
809 if (firewire_debug || error != EFBIG)
810 printf("fwohci_execute_db: error=%d\n", error);
811 return;
812 }
813 for (i = 0; i < nseg; i++) {
814 s = &segs[i];
815 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
816 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
817 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
818 db++;
819 db_tr->dbcnt++;
820 }
821}
822
823static void
824fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
825 bus_size_t size, int error)
826{
827 fwohci_execute_db(arg, segs, nseg, error);
828}
829
830static void
831fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
832{
833 int i, s;
|
834 int tcode, hdr_len, pl_off, pl_len;
| 834 int tcode, hdr_len, pl_off;
|
835 int fsegment = -1;
836 u_int32_t off;
837 struct fw_xfer *xfer;
838 struct fw_pkt *fp;
| 835 int fsegment = -1;
836 u_int32_t off;
837 struct fw_xfer *xfer;
838 struct fw_pkt *fp;
|
839 volatile struct fwohci_txpkthdr *ohcifp;
| 839 struct fwohci_txpkthdr *ohcifp;
|
840 struct fwohcidb_tr *db_tr;
| 840 struct fwohcidb_tr *db_tr;
|
841 volatile struct fwohcidb *db;
842 volatile u_int32_t *ld;
| 841 struct fwohcidb *db;
842 u_int32_t *ld;
|
843 struct tcode_info *info;
844 static int maxdesc=0;
845
846 if(&sc->atrq == dbch){
847 off = OHCI_ATQOFF;
848 }else if(&sc->atrs == dbch){
849 off = OHCI_ATSOFF;
850 }else{
851 return;
852 }
853
854 if (dbch->flags & FWOHCI_DBCH_FULL)
855 return;
856
857 s = splfw();
858 db_tr = dbch->top;
859txloop:
860 xfer = STAILQ_FIRST(&dbch->xferq.q);
861 if(xfer == NULL){
862 goto kick;
863 }
864 if(dbch->xferq.queued == 0 ){
865 device_printf(sc->fc.dev, "TX queue empty\n");
866 }
867 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
868 db_tr->xfer = xfer;
869 xfer->state = FWXF_START;
870
| 843 struct tcode_info *info;
844 static int maxdesc=0;
845
846 if(&sc->atrq == dbch){
847 off = OHCI_ATQOFF;
848 }else if(&sc->atrs == dbch){
849 off = OHCI_ATSOFF;
850 }else{
851 return;
852 }
853
854 if (dbch->flags & FWOHCI_DBCH_FULL)
855 return;
856
857 s = splfw();
858 db_tr = dbch->top;
859txloop:
860 xfer = STAILQ_FIRST(&dbch->xferq.q);
861 if(xfer == NULL){
862 goto kick;
863 }
864 if(dbch->xferq.queued == 0 ){
865 device_printf(sc->fc.dev, "TX queue empty\n");
866 }
867 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
868 db_tr->xfer = xfer;
869 xfer->state = FWXF_START;
870
|
871 fp = (struct fw_pkt *)xfer->send.buf;
| 871 fp = &xfer->send.hdr;
|
872 tcode = fp->mode.common.tcode;
873
| 872 tcode = fp->mode.common.tcode;
873
|
874 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
| 874 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
|
875 info = &tinfo[tcode];
876 hdr_len = pl_off = info->hdr_len;
877
878 ld = &ohcifp->mode.ld[0];
879 ld[0] = ld[1] = ld[2] = ld[3] = 0;
880 for( i = 0 ; i < pl_off ; i+= 4)
881 ld[i/4] = fp->mode.ld[i/4];
882
| 875 info = &tinfo[tcode];
876 hdr_len = pl_off = info->hdr_len;
877
878 ld = &ohcifp->mode.ld[0];
879 ld[0] = ld[1] = ld[2] = ld[3] = 0;
880 for( i = 0 ; i < pl_off ; i+= 4)
881 ld[i/4] = fp->mode.ld[i/4];
882
|
883 ohcifp->mode.common.spd = xfer->spd & 0x7;
| 883 ohcifp->mode.common.spd = xfer->send.spd & 0x7;
|
884 if (tcode == FWTCODE_STREAM ){
885 hdr_len = 8;
886 ohcifp->mode.stream.len = fp->mode.stream.len;
887 } else if (tcode == FWTCODE_PHY) {
888 hdr_len = 12;
889 ld[1] = fp->mode.ld[1];
890 ld[2] = fp->mode.ld[2];
891 ohcifp->mode.common.spd = 0;
892 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
893 } else {
894 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
895 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
896 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
897 }
898 db = &db_tr->db[0];
899 FWOHCI_DMA_WRITE(db->db.desc.cmd,
900 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
901 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
902 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
903/* Specify bound timer of asy. responce */
904 if(&sc->atrs == dbch){
905 FWOHCI_DMA_WRITE(db->db.desc.res,
906 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
907 }
908#if BYTE_ORDER == BIG_ENDIAN
909 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
910 hdr_len = 12;
911 for (i = 0; i < hdr_len/4; i ++)
912 FWOHCI_DMA_WRITE(ld[i], ld[i]);
913#endif
914
915again:
916 db_tr->dbcnt = 2;
917 db = &db_tr->db[db_tr->dbcnt];
| 884 if (tcode == FWTCODE_STREAM ){
885 hdr_len = 8;
886 ohcifp->mode.stream.len = fp->mode.stream.len;
887 } else if (tcode == FWTCODE_PHY) {
888 hdr_len = 12;
889 ld[1] = fp->mode.ld[1];
890 ld[2] = fp->mode.ld[2];
891 ohcifp->mode.common.spd = 0;
892 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
893 } else {
894 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
895 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
896 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
897 }
898 db = &db_tr->db[0];
899 FWOHCI_DMA_WRITE(db->db.desc.cmd,
900 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
901 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
902 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
903/* Specify bound timer of asy. responce */
904 if(&sc->atrs == dbch){
905 FWOHCI_DMA_WRITE(db->db.desc.res,
906 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
907 }
908#if BYTE_ORDER == BIG_ENDIAN
909 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
910 hdr_len = 12;
911 for (i = 0; i < hdr_len/4; i ++)
912 FWOHCI_DMA_WRITE(ld[i], ld[i]);
913#endif
914
915again:
916 db_tr->dbcnt = 2;
917 db = &db_tr->db[db_tr->dbcnt];
|
918 pl_len = xfer->send.len - pl_off;
919 if (pl_len > 0) {
| 918 if (xfer->send.pay_len > 0) {
|
920 int err;
921 /* handle payload */
922 if (xfer->mbuf == NULL) {
| 919 int err;
920 /* handle payload */
921 if (xfer->mbuf == NULL) {
|
923 caddr_t pl_addr;
924
925 pl_addr = xfer->send.buf + pl_off;
| |
926 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
| 922 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
|
927 pl_addr, pl_len,
| 923 &xfer->send.payload[0], xfer->send.pay_len,
|
928 fwohci_execute_db, db_tr,
929 /*flags*/0);
930 } else {
931 /* XXX we can handle only 6 (=8-2) mbuf chains */
932 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
933 xfer->mbuf,
934 fwohci_execute_db2, db_tr,
935 /* flags */0);
936 if (err == EFBIG) {
937 struct mbuf *m0;
938
939 if (firewire_debug)
940 device_printf(sc->fc.dev, "EFBIG.\n");
941 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
942 if (m0 != NULL) {
943 m_copydata(xfer->mbuf, 0,
944 xfer->mbuf->m_pkthdr.len,
945 mtod(m0, caddr_t));
946 m0->m_len = m0->m_pkthdr.len =
947 xfer->mbuf->m_pkthdr.len;
948 m_freem(xfer->mbuf);
949 xfer->mbuf = m0;
950 goto again;
951 }
952 device_printf(sc->fc.dev, "m_getcl failed.\n");
953 }
954 }
955 if (err)
956 printf("dmamap_load: err=%d\n", err);
957 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
958 BUS_DMASYNC_PREWRITE);
959#if 0 /* OHCI_OUTPUT_MODE == 0 */
960 for (i = 2; i < db_tr->dbcnt; i++)
961 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
962 OHCI_OUTPUT_MORE);
963#endif
964 }
965 if (maxdesc < db_tr->dbcnt) {
966 maxdesc = db_tr->dbcnt;
967 if (bootverbose)
968 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
969 }
970 /* last db */
971 LAST_DB(db_tr, db);
972 FWOHCI_DMA_SET(db->db.desc.cmd,
973 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
974 FWOHCI_DMA_WRITE(db->db.desc.depend,
975 STAILQ_NEXT(db_tr, link)->bus_addr);
976
977 if(fsegment == -1 )
978 fsegment = db_tr->dbcnt;
979 if (dbch->pdb_tr != NULL) {
980 LAST_DB(dbch->pdb_tr, db);
981 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
982 }
983 dbch->pdb_tr = db_tr;
984 db_tr = STAILQ_NEXT(db_tr, link);
985 if(db_tr != dbch->bottom){
986 goto txloop;
987 } else {
988 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
989 dbch->flags |= FWOHCI_DBCH_FULL;
990 }
991kick:
992 /* kick asy q */
993 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
994 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
995
996 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
997 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
998 } else {
999 if (bootverbose)
1000 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1001 OREAD(sc, OHCI_DMACTL(off)));
1002 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1003 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1004 dbch->xferq.flag |= FWXFERQ_RUNNING;
1005 }
1006
1007 dbch->top = db_tr;
1008 splx(s);
1009 return;
1010}
1011
1012static void
1013fwohci_start_atq(struct firewire_comm *fc)
1014{
1015 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1016 fwohci_start( sc, &(sc->atrq));
1017 return;
1018}
1019
1020static void
1021fwohci_start_ats(struct firewire_comm *fc)
1022{
1023 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1024 fwohci_start( sc, &(sc->atrs));
1025 return;
1026}
1027
1028void
1029fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1030{
1031 int s, ch, err = 0;
1032 struct fwohcidb_tr *tr;
| 924 fwohci_execute_db, db_tr,
925 /*flags*/0);
926 } else {
927 /* XXX we can handle only 6 (=8-2) mbuf chains */
928 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
929 xfer->mbuf,
930 fwohci_execute_db2, db_tr,
931 /* flags */0);
932 if (err == EFBIG) {
933 struct mbuf *m0;
934
935 if (firewire_debug)
936 device_printf(sc->fc.dev, "EFBIG.\n");
937 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
938 if (m0 != NULL) {
939 m_copydata(xfer->mbuf, 0,
940 xfer->mbuf->m_pkthdr.len,
941 mtod(m0, caddr_t));
942 m0->m_len = m0->m_pkthdr.len =
943 xfer->mbuf->m_pkthdr.len;
944 m_freem(xfer->mbuf);
945 xfer->mbuf = m0;
946 goto again;
947 }
948 device_printf(sc->fc.dev, "m_getcl failed.\n");
949 }
950 }
951 if (err)
952 printf("dmamap_load: err=%d\n", err);
953 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
954 BUS_DMASYNC_PREWRITE);
955#if 0 /* OHCI_OUTPUT_MODE == 0 */
956 for (i = 2; i < db_tr->dbcnt; i++)
957 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
958 OHCI_OUTPUT_MORE);
959#endif
960 }
961 if (maxdesc < db_tr->dbcnt) {
962 maxdesc = db_tr->dbcnt;
963 if (bootverbose)
964 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
965 }
966 /* last db */
967 LAST_DB(db_tr, db);
968 FWOHCI_DMA_SET(db->db.desc.cmd,
969 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
970 FWOHCI_DMA_WRITE(db->db.desc.depend,
971 STAILQ_NEXT(db_tr, link)->bus_addr);
972
973 if(fsegment == -1 )
974 fsegment = db_tr->dbcnt;
975 if (dbch->pdb_tr != NULL) {
976 LAST_DB(dbch->pdb_tr, db);
977 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
978 }
979 dbch->pdb_tr = db_tr;
980 db_tr = STAILQ_NEXT(db_tr, link);
981 if(db_tr != dbch->bottom){
982 goto txloop;
983 } else {
984 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
985 dbch->flags |= FWOHCI_DBCH_FULL;
986 }
987kick:
988 /* kick asy q */
989 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
990 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
991
992 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
993 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
994 } else {
995 if (bootverbose)
996 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
997 OREAD(sc, OHCI_DMACTL(off)));
998 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
999 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1000 dbch->xferq.flag |= FWXFERQ_RUNNING;
1001 }
1002
1003 dbch->top = db_tr;
1004 splx(s);
1005 return;
1006}
1007
1008static void
1009fwohci_start_atq(struct firewire_comm *fc)
1010{
1011 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1012 fwohci_start( sc, &(sc->atrq));
1013 return;
1014}
1015
1016static void
1017fwohci_start_ats(struct firewire_comm *fc)
1018{
1019 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1020 fwohci_start( sc, &(sc->atrs));
1021 return;
1022}
1023
1024void
1025fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1026{
1027 int s, ch, err = 0;
1028 struct fwohcidb_tr *tr;
|
1033 volatile struct fwohcidb *db;
| 1029 struct fwohcidb *db;
|
1034 struct fw_xfer *xfer;
1035 u_int32_t off;
1036 u_int stat, status;
1037 int packets;
1038 struct firewire_comm *fc = (struct firewire_comm *)sc;
1039
1040 if(&sc->atrq == dbch){
1041 off = OHCI_ATQOFF;
1042 ch = ATRQ_CH;
1043 }else if(&sc->atrs == dbch){
1044 off = OHCI_ATSOFF;
1045 ch = ATRS_CH;
1046 }else{
1047 return;
1048 }
1049 s = splfw();
1050 tr = dbch->bottom;
1051 packets = 0;
1052 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1053 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1054 while(dbch->xferq.queued > 0){
1055 LAST_DB(tr, db);
1056 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1057 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1058 if (fc->status != FWBUSRESET)
1059 /* maybe out of order?? */
1060 goto out;
1061 }
1062 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1063 BUS_DMASYNC_POSTWRITE);
1064 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1065#if 1
1066 if (firewire_debug)
1067 dump_db(sc, ch);
1068#endif
1069 if(status & OHCI_CNTL_DMA_DEAD) {
1070 /* Stop DMA */
1071 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1072 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1073 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1074 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1075 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1076 }
1077 stat = status & FWOHCIEV_MASK;
1078 switch(stat){
1079 case FWOHCIEV_ACKPEND:
1080 case FWOHCIEV_ACKCOMPL:
1081 err = 0;
1082 break;
1083 case FWOHCIEV_ACKBSA:
1084 case FWOHCIEV_ACKBSB:
1085 case FWOHCIEV_ACKBSX:
1086 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1087 err = EBUSY;
1088 break;
1089 case FWOHCIEV_FLUSHED:
1090 case FWOHCIEV_ACKTARD:
1091 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1092 err = EAGAIN;
1093 break;
1094 case FWOHCIEV_MISSACK:
1095 case FWOHCIEV_UNDRRUN:
1096 case FWOHCIEV_OVRRUN:
1097 case FWOHCIEV_DESCERR:
1098 case FWOHCIEV_DTRDERR:
1099 case FWOHCIEV_TIMEOUT:
1100 case FWOHCIEV_TCODERR:
1101 case FWOHCIEV_UNKNOWN:
1102 case FWOHCIEV_ACKDERR:
1103 case FWOHCIEV_ACKTERR:
1104 default:
1105 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1106 stat, fwohcicode[stat]);
1107 err = EINVAL;
1108 break;
1109 }
1110 if (tr->xfer != NULL) {
1111 xfer = tr->xfer;
1112 if (xfer->state == FWXF_RCVD) {
1113#if 0
1114 if (firewire_debug)
1115 printf("already rcvd\n");
1116#endif
1117 fw_xfer_done(xfer);
1118 } else {
1119 xfer->state = FWXF_SENT;
1120 if (err == EBUSY && fc->status != FWBUSRESET) {
1121 xfer->state = FWXF_BUSY;
1122 xfer->resp = err;
1123 if (xfer->retry_req != NULL)
1124 xfer->retry_req(xfer);
1125 else {
| 1030 struct fw_xfer *xfer;
1031 u_int32_t off;
1032 u_int stat, status;
1033 int packets;
1034 struct firewire_comm *fc = (struct firewire_comm *)sc;
1035
1036 if(&sc->atrq == dbch){
1037 off = OHCI_ATQOFF;
1038 ch = ATRQ_CH;
1039 }else if(&sc->atrs == dbch){
1040 off = OHCI_ATSOFF;
1041 ch = ATRS_CH;
1042 }else{
1043 return;
1044 }
1045 s = splfw();
1046 tr = dbch->bottom;
1047 packets = 0;
1048 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1049 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1050 while(dbch->xferq.queued > 0){
1051 LAST_DB(tr, db);
1052 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1053 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1054 if (fc->status != FWBUSRESET)
1055 /* maybe out of order?? */
1056 goto out;
1057 }
1058 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1059 BUS_DMASYNC_POSTWRITE);
1060 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1061#if 1
1062 if (firewire_debug)
1063 dump_db(sc, ch);
1064#endif
1065 if(status & OHCI_CNTL_DMA_DEAD) {
1066 /* Stop DMA */
1067 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1068 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1069 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1070 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1071 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1072 }
1073 stat = status & FWOHCIEV_MASK;
1074 switch(stat){
1075 case FWOHCIEV_ACKPEND:
1076 case FWOHCIEV_ACKCOMPL:
1077 err = 0;
1078 break;
1079 case FWOHCIEV_ACKBSA:
1080 case FWOHCIEV_ACKBSB:
1081 case FWOHCIEV_ACKBSX:
1082 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1083 err = EBUSY;
1084 break;
1085 case FWOHCIEV_FLUSHED:
1086 case FWOHCIEV_ACKTARD:
1087 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1088 err = EAGAIN;
1089 break;
1090 case FWOHCIEV_MISSACK:
1091 case FWOHCIEV_UNDRRUN:
1092 case FWOHCIEV_OVRRUN:
1093 case FWOHCIEV_DESCERR:
1094 case FWOHCIEV_DTRDERR:
1095 case FWOHCIEV_TIMEOUT:
1096 case FWOHCIEV_TCODERR:
1097 case FWOHCIEV_UNKNOWN:
1098 case FWOHCIEV_ACKDERR:
1099 case FWOHCIEV_ACKTERR:
1100 default:
1101 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1102 stat, fwohcicode[stat]);
1103 err = EINVAL;
1104 break;
1105 }
1106 if (tr->xfer != NULL) {
1107 xfer = tr->xfer;
1108 if (xfer->state == FWXF_RCVD) {
1109#if 0
1110 if (firewire_debug)
1111 printf("already rcvd\n");
1112#endif
1113 fw_xfer_done(xfer);
1114 } else {
1115 xfer->state = FWXF_SENT;
1116 if (err == EBUSY && fc->status != FWBUSRESET) {
1117 xfer->state = FWXF_BUSY;
1118 xfer->resp = err;
1119 if (xfer->retry_req != NULL)
1120 xfer->retry_req(xfer);
1121 else {
|
1126 xfer->recv.len = 0;
| 1122 xfer->recv.pay_len = 0;
|
1127 fw_xfer_done(xfer);
1128 }
1129 } else if (stat != FWOHCIEV_ACKPEND) {
1130 if (stat != FWOHCIEV_ACKCOMPL)
1131 xfer->state = FWXF_SENTERR;
1132 xfer->resp = err;
| 1123 fw_xfer_done(xfer);
1124 }
1125 } else if (stat != FWOHCIEV_ACKPEND) {
1126 if (stat != FWOHCIEV_ACKCOMPL)
1127 xfer->state = FWXF_SENTERR;
1128 xfer->resp = err;
|
1133 xfer->recv.len = 0;
| 1129 xfer->recv.pay_len = 0;
|
1134 fw_xfer_done(xfer);
1135 }
1136 }
1137 /*
1138 * The watchdog timer takes care of split
1139 * transcation timeout for ACKPEND case.
1140 */
1141 } else {
1142 printf("this shouldn't happen\n");
1143 }
1144 dbch->xferq.queued --;
1145 tr->xfer = NULL;
1146
1147 packets ++;
1148 tr = STAILQ_NEXT(tr, link);
1149 dbch->bottom = tr;
1150 if (dbch->bottom == dbch->top) {
1151 /* we reaches the end of context program */
1152 if (firewire_debug && dbch->xferq.queued > 0)
1153 printf("queued > 0\n");
1154 break;
1155 }
1156 }
1157out:
1158 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1159 printf("make free slot\n");
1160 dbch->flags &= ~FWOHCI_DBCH_FULL;
1161 fwohci_start(sc, dbch);
1162 }
1163 splx(s);
1164}
1165
1166static void
1167fwohci_db_free(struct fwohci_dbch *dbch)
1168{
1169 struct fwohcidb_tr *db_tr;
1170 int idb;
1171
1172 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1173 return;
1174
1175 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1176 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1177 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1178 db_tr->buf != NULL) {
1179 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1180 db_tr->buf, dbch->xferq.psize);
1181 db_tr->buf = NULL;
1182 } else if (db_tr->dma_map != NULL)
1183 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1184 }
1185 dbch->ndb = 0;
1186 db_tr = STAILQ_FIRST(&dbch->db_trq);
1187 fwdma_free_multiseg(dbch->am);
1188 free(db_tr, M_FW);
1189 STAILQ_INIT(&dbch->db_trq);
1190 dbch->flags &= ~FWOHCI_DBCH_INIT;
1191}
1192
1193static void
1194fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1195{
1196 int idb;
1197 struct fwohcidb_tr *db_tr;
1198
1199 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1200 goto out;
1201
1202 /* create dma_tag for buffers */
1203#define MAX_REQCOUNT 0xffff
1204 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1205 /*alignment*/ 1, /*boundary*/ 0,
1206 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1207 /*highaddr*/ BUS_SPACE_MAXADDR,
1208 /*filter*/NULL, /*filterarg*/NULL,
1209 /*maxsize*/ dbch->xferq.psize,
1210 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1211 /*maxsegsz*/ MAX_REQCOUNT,
1212 /*flags*/ 0,
1213#if __FreeBSD_version >= 501102
1214 /*lockfunc*/busdma_lock_mutex,
1215 /*lockarg*/&Giant,
1216#endif
1217 &dbch->dmat))
1218 return;
1219
1220 /* allocate DB entries and attach one to each DMA channels */
1221 /* DB entry must start at 16 bytes bounary. */
1222 STAILQ_INIT(&dbch->db_trq);
1223 db_tr = (struct fwohcidb_tr *)
1224 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1225 M_FW, M_WAITOK | M_ZERO);
1226 if(db_tr == NULL){
1227 printf("fwohci_db_init: malloc(1) failed\n");
1228 return;
1229 }
1230
1231#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1232 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1233 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1234 if (dbch->am == NULL) {
1235 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1236 return;
1237 }
1238 /* Attach DB to DMA ch. */
1239 for(idb = 0 ; idb < dbch->ndb ; idb++){
1240 db_tr->dbcnt = 0;
1241 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1242 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1243 /* create dmamap for buffers */
1244 /* XXX do we need 4bytes alignment tag? */
1245 /* XXX don't alloc dma_map for AR */
1246 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1247 printf("bus_dmamap_create failed\n");
1248 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1249 fwohci_db_free(dbch);
1250 return;
1251 }
1252 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1253 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1254 if (idb % dbch->xferq.bnpacket == 0)
1255 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1256 ].start = (caddr_t)db_tr;
1257 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1258 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1259 ].end = (caddr_t)db_tr;
1260 }
1261 db_tr++;
1262 }
1263 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1264 = STAILQ_FIRST(&dbch->db_trq);
1265out:
1266 dbch->xferq.queued = 0;
1267 dbch->pdb_tr = NULL;
1268 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1269 dbch->bottom = dbch->top;
1270 dbch->flags = FWOHCI_DBCH_INIT;
1271}
1272
1273static int
1274fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1275{
1276 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1277 int sleepch;
1278
1279 OWRITE(sc, OHCI_ITCTLCLR(dmach),
1280 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1281 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1282 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1283 /* XXX we cannot free buffers until the DMA really stops */
1284 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz);
1285 fwohci_db_free(&sc->it[dmach]);
1286 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1287 return 0;
1288}
1289
1290static int
1291fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1292{
1293 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1294 int sleepch;
1295
1296 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1297 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1298 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1299 /* XXX we cannot free buffers until the DMA really stops */
1300 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1301 fwohci_db_free(&sc->ir[dmach]);
1302 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1303 return 0;
1304}
1305
1306#if BYTE_ORDER == BIG_ENDIAN
1307static void
1308fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1309{
1310 qld[0] = FWOHCI_DMA_READ(qld[0]);
1311 return;
1312}
1313#endif
1314
1315static int
1316fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1317{
1318 int err = 0;
1319 int idb, z, i, dmach = 0, ldesc;
1320 u_int32_t off = NULL;
1321 struct fwohcidb_tr *db_tr;
| 1130 fw_xfer_done(xfer);
1131 }
1132 }
1133 /*
1134 * The watchdog timer takes care of split
1135 * transcation timeout for ACKPEND case.
1136 */
1137 } else {
1138 printf("this shouldn't happen\n");
1139 }
1140 dbch->xferq.queued --;
1141 tr->xfer = NULL;
1142
1143 packets ++;
1144 tr = STAILQ_NEXT(tr, link);
1145 dbch->bottom = tr;
1146 if (dbch->bottom == dbch->top) {
1147 /* we reaches the end of context program */
1148 if (firewire_debug && dbch->xferq.queued > 0)
1149 printf("queued > 0\n");
1150 break;
1151 }
1152 }
1153out:
1154 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1155 printf("make free slot\n");
1156 dbch->flags &= ~FWOHCI_DBCH_FULL;
1157 fwohci_start(sc, dbch);
1158 }
1159 splx(s);
1160}
1161
1162static void
1163fwohci_db_free(struct fwohci_dbch *dbch)
1164{
1165 struct fwohcidb_tr *db_tr;
1166 int idb;
1167
1168 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1169 return;
1170
1171 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1172 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1173 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1174 db_tr->buf != NULL) {
1175 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1176 db_tr->buf, dbch->xferq.psize);
1177 db_tr->buf = NULL;
1178 } else if (db_tr->dma_map != NULL)
1179 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1180 }
1181 dbch->ndb = 0;
1182 db_tr = STAILQ_FIRST(&dbch->db_trq);
1183 fwdma_free_multiseg(dbch->am);
1184 free(db_tr, M_FW);
1185 STAILQ_INIT(&dbch->db_trq);
1186 dbch->flags &= ~FWOHCI_DBCH_INIT;
1187}
1188
1189static void
1190fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1191{
1192 int idb;
1193 struct fwohcidb_tr *db_tr;
1194
1195 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1196 goto out;
1197
1198 /* create dma_tag for buffers */
1199#define MAX_REQCOUNT 0xffff
1200 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1201 /*alignment*/ 1, /*boundary*/ 0,
1202 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1203 /*highaddr*/ BUS_SPACE_MAXADDR,
1204 /*filter*/NULL, /*filterarg*/NULL,
1205 /*maxsize*/ dbch->xferq.psize,
1206 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1207 /*maxsegsz*/ MAX_REQCOUNT,
1208 /*flags*/ 0,
1209#if __FreeBSD_version >= 501102
1210 /*lockfunc*/busdma_lock_mutex,
1211 /*lockarg*/&Giant,
1212#endif
1213 &dbch->dmat))
1214 return;
1215
1216 /* allocate DB entries and attach one to each DMA channels */
1217 /* DB entry must start at 16 bytes bounary. */
1218 STAILQ_INIT(&dbch->db_trq);
1219 db_tr = (struct fwohcidb_tr *)
1220 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1221 M_FW, M_WAITOK | M_ZERO);
1222 if(db_tr == NULL){
1223 printf("fwohci_db_init: malloc(1) failed\n");
1224 return;
1225 }
1226
1227#define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1228 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1229 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1230 if (dbch->am == NULL) {
1231 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1232 return;
1233 }
1234 /* Attach DB to DMA ch. */
1235 for(idb = 0 ; idb < dbch->ndb ; idb++){
1236 db_tr->dbcnt = 0;
1237 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1238 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1239 /* create dmamap for buffers */
1240 /* XXX do we need 4bytes alignment tag? */
1241 /* XXX don't alloc dma_map for AR */
1242 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1243 printf("bus_dmamap_create failed\n");
1244 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1245 fwohci_db_free(dbch);
1246 return;
1247 }
1248 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1249 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1250 if (idb % dbch->xferq.bnpacket == 0)
1251 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1252 ].start = (caddr_t)db_tr;
1253 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1254 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1255 ].end = (caddr_t)db_tr;
1256 }
1257 db_tr++;
1258 }
1259 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1260 = STAILQ_FIRST(&dbch->db_trq);
1261out:
1262 dbch->xferq.queued = 0;
1263 dbch->pdb_tr = NULL;
1264 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1265 dbch->bottom = dbch->top;
1266 dbch->flags = FWOHCI_DBCH_INIT;
1267}
1268
1269static int
1270fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1271{
1272 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1273 int sleepch;
1274
1275 OWRITE(sc, OHCI_ITCTLCLR(dmach),
1276 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1277 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1278 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1279 /* XXX we cannot free buffers until the DMA really stops */
1280 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz);
1281 fwohci_db_free(&sc->it[dmach]);
1282 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1283 return 0;
1284}
1285
1286static int
1287fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1288{
1289 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1290 int sleepch;
1291
1292 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1293 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1294 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1295 /* XXX we cannot free buffers until the DMA really stops */
1296 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1297 fwohci_db_free(&sc->ir[dmach]);
1298 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1299 return 0;
1300}
1301
1302#if BYTE_ORDER == BIG_ENDIAN
1303static void
1304fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1305{
1306 qld[0] = FWOHCI_DMA_READ(qld[0]);
1307 return;
1308}
1309#endif
1310
1311static int
1312fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1313{
1314 int err = 0;
1315 int idb, z, i, dmach = 0, ldesc;
1316 u_int32_t off = NULL;
1317 struct fwohcidb_tr *db_tr;
|
1322 volatile struct fwohcidb *db;
| 1318 struct fwohcidb *db;
|
1323
1324 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1325 err = EINVAL;
1326 return err;
1327 }
1328 z = dbch->ndesc;
1329 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1330 if( &sc->it[dmach] == dbch){
1331 off = OHCI_ITOFF(dmach);
1332 break;
1333 }
1334 }
1335 if(off == NULL){
1336 err = EINVAL;
1337 return err;
1338 }
1339 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1340 return err;
1341 dbch->xferq.flag |= FWXFERQ_RUNNING;
1342 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1343 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1344 }
1345 db_tr = dbch->top;
1346 for (idb = 0; idb < dbch->ndb; idb ++) {
1347 fwohci_add_tx_buf(dbch, db_tr, idb);
1348 if(STAILQ_NEXT(db_tr, link) == NULL){
1349 break;
1350 }
1351 db = db_tr->db;
1352 ldesc = db_tr->dbcnt - 1;
1353 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1354 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1355 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1356 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1357 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1358 FWOHCI_DMA_SET(
1359 db[ldesc].db.desc.cmd,
1360 OHCI_INTERRUPT_ALWAYS);
1361 /* OHCI 1.1 and above */
1362 FWOHCI_DMA_SET(
1363 db[0].db.desc.cmd,
1364 OHCI_INTERRUPT_ALWAYS);
1365 }
1366 }
1367 db_tr = STAILQ_NEXT(db_tr, link);
1368 }
1369 FWOHCI_DMA_CLEAR(
1370 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1371 return err;
1372}
1373
1374static int
1375fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1376{
1377 int err = 0;
1378 int idb, z, i, dmach = 0, ldesc;
1379 u_int32_t off = NULL;
1380 struct fwohcidb_tr *db_tr;
| 1319
1320 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1321 err = EINVAL;
1322 return err;
1323 }
1324 z = dbch->ndesc;
1325 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1326 if( &sc->it[dmach] == dbch){
1327 off = OHCI_ITOFF(dmach);
1328 break;
1329 }
1330 }
1331 if(off == NULL){
1332 err = EINVAL;
1333 return err;
1334 }
1335 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1336 return err;
1337 dbch->xferq.flag |= FWXFERQ_RUNNING;
1338 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1339 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1340 }
1341 db_tr = dbch->top;
1342 for (idb = 0; idb < dbch->ndb; idb ++) {
1343 fwohci_add_tx_buf(dbch, db_tr, idb);
1344 if(STAILQ_NEXT(db_tr, link) == NULL){
1345 break;
1346 }
1347 db = db_tr->db;
1348 ldesc = db_tr->dbcnt - 1;
1349 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1350 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1351 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1352 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1353 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1354 FWOHCI_DMA_SET(
1355 db[ldesc].db.desc.cmd,
1356 OHCI_INTERRUPT_ALWAYS);
1357 /* OHCI 1.1 and above */
1358 FWOHCI_DMA_SET(
1359 db[0].db.desc.cmd,
1360 OHCI_INTERRUPT_ALWAYS);
1361 }
1362 }
1363 db_tr = STAILQ_NEXT(db_tr, link);
1364 }
1365 FWOHCI_DMA_CLEAR(
1366 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1367 return err;
1368}
1369
1370static int
1371fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1372{
1373 int err = 0;
1374 int idb, z, i, dmach = 0, ldesc;
1375 u_int32_t off = NULL;
1376 struct fwohcidb_tr *db_tr;
|
1381 volatile struct fwohcidb *db;
| 1377 struct fwohcidb *db;
|
1382
1383 z = dbch->ndesc;
1384 if(&sc->arrq == dbch){
1385 off = OHCI_ARQOFF;
1386 }else if(&sc->arrs == dbch){
1387 off = OHCI_ARSOFF;
1388 }else{
1389 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1390 if( &sc->ir[dmach] == dbch){
1391 off = OHCI_IROFF(dmach);
1392 break;
1393 }
1394 }
1395 }
1396 if(off == NULL){
1397 err = EINVAL;
1398 return err;
1399 }
1400 if(dbch->xferq.flag & FWXFERQ_STREAM){
1401 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1402 return err;
1403 }else{
1404 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1405 err = EBUSY;
1406 return err;
1407 }
1408 }
1409 dbch->xferq.flag |= FWXFERQ_RUNNING;
1410 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1411 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1412 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1413 }
1414 db_tr = dbch->top;
1415 for (idb = 0; idb < dbch->ndb; idb ++) {
1416 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1417 if (STAILQ_NEXT(db_tr, link) == NULL)
1418 break;
1419 db = db_tr->db;
1420 ldesc = db_tr->dbcnt - 1;
1421 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1422 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1423 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1424 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1425 FWOHCI_DMA_SET(
1426 db[ldesc].db.desc.cmd,
1427 OHCI_INTERRUPT_ALWAYS);
1428 FWOHCI_DMA_CLEAR(
1429 db[ldesc].db.desc.depend,
1430 0xf);
1431 }
1432 }
1433 db_tr = STAILQ_NEXT(db_tr, link);
1434 }
1435 FWOHCI_DMA_CLEAR(
1436 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1437 dbch->buf_offset = 0;
1438 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1439 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1440 if(dbch->xferq.flag & FWXFERQ_STREAM){
1441 return err;
1442 }else{
1443 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1444 }
1445 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1446 return err;
1447}
1448
1449static int
1450fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1451{
1452 int sec, cycle, cycle_match;
1453
1454 cycle = cycle_now & 0x1fff;
1455 sec = cycle_now >> 13;
1456#define CYCLE_MOD 0x10
1457#if 1
1458#define CYCLE_DELAY 8 /* min delay to start DMA */
1459#else
1460#define CYCLE_DELAY 7000 /* min delay to start DMA */
1461#endif
1462 cycle = cycle + CYCLE_DELAY;
1463 if (cycle >= 8000) {
1464 sec ++;
1465 cycle -= 8000;
1466 }
1467 cycle = roundup2(cycle, CYCLE_MOD);
1468 if (cycle >= 8000) {
1469 sec ++;
1470 if (cycle == 8000)
1471 cycle = 0;
1472 else
1473 cycle = CYCLE_MOD;
1474 }
1475 cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1476
1477 return(cycle_match);
1478}
1479
1480static int
1481fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1482{
1483 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1484 int err = 0;
1485 unsigned short tag, ich;
1486 struct fwohci_dbch *dbch;
1487 int cycle_match, cycle_now, s, ldesc;
1488 u_int32_t stat;
1489 struct fw_bulkxfer *first, *chunk, *prev;
1490 struct fw_xferq *it;
1491
1492 dbch = &sc->it[dmach];
1493 it = &dbch->xferq;
1494
1495 tag = (it->flag >> 6) & 3;
1496 ich = it->flag & 0x3f;
1497 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1498 dbch->ndb = it->bnpacket * it->bnchunk;
1499 dbch->ndesc = 3;
1500 fwohci_db_init(sc, dbch);
1501 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1502 return ENOMEM;
1503 err = fwohci_tx_enable(sc, dbch);
1504 }
1505 if(err)
1506 return err;
1507
1508 ldesc = dbch->ndesc - 1;
1509 s = splfw();
1510 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1511 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
| 1378
1379 z = dbch->ndesc;
1380 if(&sc->arrq == dbch){
1381 off = OHCI_ARQOFF;
1382 }else if(&sc->arrs == dbch){
1383 off = OHCI_ARSOFF;
1384 }else{
1385 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1386 if( &sc->ir[dmach] == dbch){
1387 off = OHCI_IROFF(dmach);
1388 break;
1389 }
1390 }
1391 }
1392 if(off == NULL){
1393 err = EINVAL;
1394 return err;
1395 }
1396 if(dbch->xferq.flag & FWXFERQ_STREAM){
1397 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1398 return err;
1399 }else{
1400 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1401 err = EBUSY;
1402 return err;
1403 }
1404 }
1405 dbch->xferq.flag |= FWXFERQ_RUNNING;
1406 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1407 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1408 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1409 }
1410 db_tr = dbch->top;
1411 for (idb = 0; idb < dbch->ndb; idb ++) {
1412 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1413 if (STAILQ_NEXT(db_tr, link) == NULL)
1414 break;
1415 db = db_tr->db;
1416 ldesc = db_tr->dbcnt - 1;
1417 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1418 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1419 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1420 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1421 FWOHCI_DMA_SET(
1422 db[ldesc].db.desc.cmd,
1423 OHCI_INTERRUPT_ALWAYS);
1424 FWOHCI_DMA_CLEAR(
1425 db[ldesc].db.desc.depend,
1426 0xf);
1427 }
1428 }
1429 db_tr = STAILQ_NEXT(db_tr, link);
1430 }
1431 FWOHCI_DMA_CLEAR(
1432 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1433 dbch->buf_offset = 0;
1434 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1435 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1436 if(dbch->xferq.flag & FWXFERQ_STREAM){
1437 return err;
1438 }else{
1439 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1440 }
1441 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1442 return err;
1443}
1444
1445static int
1446fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1447{
1448 int sec, cycle, cycle_match;
1449
1450 cycle = cycle_now & 0x1fff;
1451 sec = cycle_now >> 13;
1452#define CYCLE_MOD 0x10
1453#if 1
1454#define CYCLE_DELAY 8 /* min delay to start DMA */
1455#else
1456#define CYCLE_DELAY 7000 /* min delay to start DMA */
1457#endif
1458 cycle = cycle + CYCLE_DELAY;
1459 if (cycle >= 8000) {
1460 sec ++;
1461 cycle -= 8000;
1462 }
1463 cycle = roundup2(cycle, CYCLE_MOD);
1464 if (cycle >= 8000) {
1465 sec ++;
1466 if (cycle == 8000)
1467 cycle = 0;
1468 else
1469 cycle = CYCLE_MOD;
1470 }
1471 cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1472
1473 return(cycle_match);
1474}
1475
1476static int
1477fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1478{
1479 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1480 int err = 0;
1481 unsigned short tag, ich;
1482 struct fwohci_dbch *dbch;
1483 int cycle_match, cycle_now, s, ldesc;
1484 u_int32_t stat;
1485 struct fw_bulkxfer *first, *chunk, *prev;
1486 struct fw_xferq *it;
1487
1488 dbch = &sc->it[dmach];
1489 it = &dbch->xferq;
1490
1491 tag = (it->flag >> 6) & 3;
1492 ich = it->flag & 0x3f;
1493 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1494 dbch->ndb = it->bnpacket * it->bnchunk;
1495 dbch->ndesc = 3;
1496 fwohci_db_init(sc, dbch);
1497 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1498 return ENOMEM;
1499 err = fwohci_tx_enable(sc, dbch);
1500 }
1501 if(err)
1502 return err;
1503
1504 ldesc = dbch->ndesc - 1;
1505 s = splfw();
1506 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1507 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
|
1512 volatile struct fwohcidb *db;
| 1508 struct fwohcidb *db;
|
1513
1514 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1515 BUS_DMASYNC_PREWRITE);
1516 fwohci_txbufdb(sc, dmach, chunk);
1517 if (prev != NULL) {
1518 db = ((struct fwohcidb_tr *)(prev->end))->db;
1519#if 0 /* XXX necessary? */
1520 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1521 OHCI_BRANCH_ALWAYS);
1522#endif
1523#if 0 /* if bulkxfer->npacket changes */
1524 db[ldesc].db.desc.depend = db[0].db.desc.depend =
1525 ((struct fwohcidb_tr *)
1526 (chunk->start))->bus_addr | dbch->ndesc;
1527#else
1528 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1529 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1530#endif
1531 }
1532 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1533 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1534 prev = chunk;
1535 }
1536 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1537 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1538 splx(s);
1539 stat = OREAD(sc, OHCI_ITCTL(dmach));
1540 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1541 printf("stat 0x%x\n", stat);
1542
1543 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1544 return 0;
1545
1546#if 0
1547 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1548#endif
1549 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1550 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1551 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1552 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1553
1554 first = STAILQ_FIRST(&it->stdma);
1555 OWRITE(sc, OHCI_ITCMD(dmach),
1556 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1557 if (firewire_debug) {
1558 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1559#if 1
1560 dump_dma(sc, ITX_CH + dmach);
1561#endif
1562 }
1563 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1564#if 1
1565 /* Don't start until all chunks are buffered */
1566 if (STAILQ_FIRST(&it->stfree) != NULL)
1567 goto out;
1568#endif
1569#if 1
1570 /* Clear cycle match counter bits */
1571 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1572
1573 /* 2bit second + 13bit cycle */
1574 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1575 cycle_match = fwohci_next_cycle(fc, cycle_now);
1576
1577 OWRITE(sc, OHCI_ITCTL(dmach),
1578 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1579 | OHCI_CNTL_DMA_RUN);
1580#else
1581 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1582#endif
1583 if (firewire_debug) {
1584 printf("cycle_match: 0x%04x->0x%04x\n",
1585 cycle_now, cycle_match);
1586 dump_dma(sc, ITX_CH + dmach);
1587 dump_db(sc, ITX_CH + dmach);
1588 }
1589 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1590 device_printf(sc->fc.dev,
1591 "IT DMA underrun (0x%08x)\n", stat);
1592 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1593 }
1594out:
1595 return err;
1596}
1597
1598static int
1599fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1600{
1601 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1602 int err = 0, s, ldesc;
1603 unsigned short tag, ich;
1604 u_int32_t stat;
1605 struct fwohci_dbch *dbch;
1606 struct fwohcidb_tr *db_tr;
1607 struct fw_bulkxfer *first, *prev, *chunk;
1608 struct fw_xferq *ir;
1609
1610 dbch = &sc->ir[dmach];
1611 ir = &dbch->xferq;
1612
1613 if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1614 tag = (ir->flag >> 6) & 3;
1615 ich = ir->flag & 0x3f;
1616 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1617
1618 ir->queued = 0;
1619 dbch->ndb = ir->bnpacket * ir->bnchunk;
1620 dbch->ndesc = 2;
1621 fwohci_db_init(sc, dbch);
1622 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1623 return ENOMEM;
1624 err = fwohci_rx_enable(sc, dbch);
1625 }
1626 if(err)
1627 return err;
1628
1629 first = STAILQ_FIRST(&ir->stfree);
1630 if (first == NULL) {
1631 device_printf(fc->dev, "IR DMA no free chunk\n");
1632 return 0;
1633 }
1634
1635 ldesc = dbch->ndesc - 1;
1636 s = splfw();
1637 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1638 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
| 1509
1510 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1511 BUS_DMASYNC_PREWRITE);
1512 fwohci_txbufdb(sc, dmach, chunk);
1513 if (prev != NULL) {
1514 db = ((struct fwohcidb_tr *)(prev->end))->db;
1515#if 0 /* XXX necessary? */
1516 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1517 OHCI_BRANCH_ALWAYS);
1518#endif
1519#if 0 /* if bulkxfer->npacket changes */
1520 db[ldesc].db.desc.depend = db[0].db.desc.depend =
1521 ((struct fwohcidb_tr *)
1522 (chunk->start))->bus_addr | dbch->ndesc;
1523#else
1524 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1525 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1526#endif
1527 }
1528 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1529 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1530 prev = chunk;
1531 }
1532 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1533 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1534 splx(s);
1535 stat = OREAD(sc, OHCI_ITCTL(dmach));
1536 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1537 printf("stat 0x%x\n", stat);
1538
1539 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1540 return 0;
1541
1542#if 0
1543 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1544#endif
1545 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1546 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1547 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1548 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1549
1550 first = STAILQ_FIRST(&it->stdma);
1551 OWRITE(sc, OHCI_ITCMD(dmach),
1552 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1553 if (firewire_debug) {
1554 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1555#if 1
1556 dump_dma(sc, ITX_CH + dmach);
1557#endif
1558 }
1559 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1560#if 1
1561 /* Don't start until all chunks are buffered */
1562 if (STAILQ_FIRST(&it->stfree) != NULL)
1563 goto out;
1564#endif
1565#if 1
1566 /* Clear cycle match counter bits */
1567 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1568
1569 /* 2bit second + 13bit cycle */
1570 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1571 cycle_match = fwohci_next_cycle(fc, cycle_now);
1572
1573 OWRITE(sc, OHCI_ITCTL(dmach),
1574 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1575 | OHCI_CNTL_DMA_RUN);
1576#else
1577 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1578#endif
1579 if (firewire_debug) {
1580 printf("cycle_match: 0x%04x->0x%04x\n",
1581 cycle_now, cycle_match);
1582 dump_dma(sc, ITX_CH + dmach);
1583 dump_db(sc, ITX_CH + dmach);
1584 }
1585 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1586 device_printf(sc->fc.dev,
1587 "IT DMA underrun (0x%08x)\n", stat);
1588 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1589 }
1590out:
1591 return err;
1592}
1593
1594static int
1595fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1596{
1597 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1598 int err = 0, s, ldesc;
1599 unsigned short tag, ich;
1600 u_int32_t stat;
1601 struct fwohci_dbch *dbch;
1602 struct fwohcidb_tr *db_tr;
1603 struct fw_bulkxfer *first, *prev, *chunk;
1604 struct fw_xferq *ir;
1605
1606 dbch = &sc->ir[dmach];
1607 ir = &dbch->xferq;
1608
1609 if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1610 tag = (ir->flag >> 6) & 3;
1611 ich = ir->flag & 0x3f;
1612 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1613
1614 ir->queued = 0;
1615 dbch->ndb = ir->bnpacket * ir->bnchunk;
1616 dbch->ndesc = 2;
1617 fwohci_db_init(sc, dbch);
1618 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1619 return ENOMEM;
1620 err = fwohci_rx_enable(sc, dbch);
1621 }
1622 if(err)
1623 return err;
1624
1625 first = STAILQ_FIRST(&ir->stfree);
1626 if (first == NULL) {
1627 device_printf(fc->dev, "IR DMA no free chunk\n");
1628 return 0;
1629 }
1630
1631 ldesc = dbch->ndesc - 1;
1632 s = splfw();
1633 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1634 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
|
1639 volatile struct fwohcidb *db;
| 1635 struct fwohcidb *db;
|
1640
1641#if 1 /* XXX for if_fwe */
1642 if (chunk->mbuf != NULL) {
1643 db_tr = (struct fwohcidb_tr *)(chunk->start);
1644 db_tr->dbcnt = 1;
1645 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1646 chunk->mbuf, fwohci_execute_db2, db_tr,
1647 /* flags */0);
1648 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1649 OHCI_UPDATE | OHCI_INPUT_LAST |
1650 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1651 }
1652#endif
1653 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1654 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1655 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1656 if (prev != NULL) {
1657 db = ((struct fwohcidb_tr *)(prev->end))->db;
1658 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1659 }
1660 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1661 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1662 prev = chunk;
1663 }
1664 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1665 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1666 splx(s);
1667 stat = OREAD(sc, OHCI_IRCTL(dmach));
1668 if (stat & OHCI_CNTL_DMA_ACTIVE)
1669 return 0;
1670 if (stat & OHCI_CNTL_DMA_RUN) {
1671 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1672 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1673 }
1674
1675 if (firewire_debug)
1676 printf("start IR DMA 0x%x\n", stat);
1677 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1678 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1679 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1680 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1681 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1682 OWRITE(sc, OHCI_IRCMD(dmach),
1683 ((struct fwohcidb_tr *)(first->start))->bus_addr
1684 | dbch->ndesc);
1685 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1686 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1687#if 0
1688 dump_db(sc, IRX_CH + dmach);
1689#endif
1690 return err;
1691}
1692
1693int
1694fwohci_stop(struct fwohci_softc *sc, device_t dev)
1695{
1696 u_int i;
1697
1698/* Now stopping all DMA channel */
1699 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1700 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1701 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1702 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1703
1704 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1705 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1706 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1707 }
1708
1709/* FLUSH FIFO and reset Transmitter/Reciever */
1710 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1711
1712/* Stop interrupt */
1713 OWRITE(sc, FWOHCI_INTMASKCLR,
1714 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1715 | OHCI_INT_PHY_INT
1716 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1717 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1718 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1719 | OHCI_INT_PHY_BUS_R);
1720
1721 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1722 fw_drain_txq(&sc->fc);
1723
1724/* XXX Link down? Bus reset? */
1725 return 0;
1726}
1727
1728int
1729fwohci_resume(struct fwohci_softc *sc, device_t dev)
1730{
1731 int i;
1732 struct fw_xferq *ir;
1733 struct fw_bulkxfer *chunk;
1734
1735 fwohci_reset(sc, dev);
1736 /* XXX resume isochronus receive automatically. (how about TX?) */
1737 for(i = 0; i < sc->fc.nisodma; i ++) {
1738 ir = &sc->ir[i].xferq;
1739 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1740 device_printf(sc->fc.dev,
1741 "resume iso receive ch: %d\n", i);
1742 ir->flag &= ~FWXFERQ_RUNNING;
1743 /* requeue stdma to stfree */
1744 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1745 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1746 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1747 }
1748 sc->fc.irx_enable(&sc->fc, i);
1749 }
1750 }
1751
1752 bus_generic_resume(dev);
1753 sc->fc.ibr(&sc->fc);
1754 return 0;
1755}
1756
1757#define ACK_ALL
1758static void
1759fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1760{
1761 u_int32_t irstat, itstat;
1762 u_int i;
1763 struct firewire_comm *fc = (struct firewire_comm *)sc;
1764
1765#ifdef OHCI_DEBUG
1766 if(stat & OREAD(sc, FWOHCI_INTMASK))
1767 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1768 stat & OHCI_INT_EN ? "DMA_EN ":"",
1769 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1770 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1771 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1772 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1773 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1774 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1775 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1776 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1777 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1778 stat & OHCI_INT_PHY_SID ? "SID ":"",
1779 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1780 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1781 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1782 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1783 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1784 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1785 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1786 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1787 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1788 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1789 stat, OREAD(sc, FWOHCI_INTMASK)
1790 );
1791#endif
1792/* Bus reset */
1793 if(stat & OHCI_INT_PHY_BUS_R ){
1794 if (fc->status == FWBUSRESET)
1795 goto busresetout;
1796 /* Disable bus reset interrupt until sid recv. */
1797 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1798
1799 device_printf(fc->dev, "BUS reset\n");
1800 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1801 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1802
1803 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1804 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1805 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1806 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1807
1808#ifndef ACK_ALL
1809 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1810#endif
1811 fw_busreset(fc);
1812 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1813 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
1814 }
1815busresetout:
1816 if((stat & OHCI_INT_DMA_IR )){
1817#ifndef ACK_ALL
1818 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1819#endif
1820#if __FreeBSD_version >= 500000
1821 irstat = atomic_readandclear_int(&sc->irstat);
1822#else
1823 irstat = sc->irstat;
1824 sc->irstat = 0;
1825#endif
1826 for(i = 0; i < fc->nisodma ; i++){
1827 struct fwohci_dbch *dbch;
1828
1829 if((irstat & (1 << i)) != 0){
1830 dbch = &sc->ir[i];
1831 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1832 device_printf(sc->fc.dev,
1833 "dma(%d) not active\n", i);
1834 continue;
1835 }
1836 fwohci_rbuf_update(sc, i);
1837 }
1838 }
1839 }
1840 if((stat & OHCI_INT_DMA_IT )){
1841#ifndef ACK_ALL
1842 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1843#endif
1844#if __FreeBSD_version >= 500000
1845 itstat = atomic_readandclear_int(&sc->itstat);
1846#else
1847 itstat = sc->itstat;
1848 sc->itstat = 0;
1849#endif
1850 for(i = 0; i < fc->nisodma ; i++){
1851 if((itstat & (1 << i)) != 0){
1852 fwohci_tbuf_update(sc, i);
1853 }
1854 }
1855 }
1856 if((stat & OHCI_INT_DMA_PRRS )){
1857#ifndef ACK_ALL
1858 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1859#endif
1860#if 0
1861 dump_dma(sc, ARRS_CH);
1862 dump_db(sc, ARRS_CH);
1863#endif
1864 fwohci_arcv(sc, &sc->arrs, count);
1865 }
1866 if((stat & OHCI_INT_DMA_PRRQ )){
1867#ifndef ACK_ALL
1868 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1869#endif
1870#if 0
1871 dump_dma(sc, ARRQ_CH);
1872 dump_db(sc, ARRQ_CH);
1873#endif
1874 fwohci_arcv(sc, &sc->arrq, count);
1875 }
1876 if(stat & OHCI_INT_PHY_SID){
1877 u_int32_t *buf, node_id;
1878 int plen;
1879
1880#ifndef ACK_ALL
1881 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1882#endif
1883 /* Enable bus reset interrupt */
1884 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1885 /* Allow async. request to us */
1886 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1887 /* XXX insecure ?? */
1888 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1889 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1890 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1891 /* Set ATRetries register */
1892 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1893/*
1894** Checking whether the node is root or not. If root, turn on
1895** cycle master.
1896*/
1897 node_id = OREAD(sc, FWOHCI_NODEID);
1898 plen = OREAD(sc, OHCI_SID_CNT);
1899
1900 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1901 node_id, (plen >> 16) & 0xff);
1902 if (!(node_id & OHCI_NODE_VALID)) {
1903 printf("Bus reset failure\n");
1904 goto sidout;
1905 }
1906 if (node_id & OHCI_NODE_ROOT) {
1907 printf("CYCLEMASTER mode\n");
1908 OWRITE(sc, OHCI_LNKCTL,
1909 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1910 } else {
1911 printf("non CYCLEMASTER mode\n");
1912 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1913 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1914 }
1915 fc->nodeid = node_id & 0x3f;
1916
1917 if (plen & OHCI_SID_ERR) {
1918 device_printf(fc->dev, "SID Error\n");
1919 goto sidout;
1920 }
1921 plen &= OHCI_SID_CNT_MASK;
1922 if (plen < 4 || plen > OHCI_SIDSIZE) {
1923 device_printf(fc->dev, "invalid SID len = %d\n", plen);
1924 goto sidout;
1925 }
1926 plen -= 4; /* chop control info */
1927 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
1928 if (buf == NULL) {
1929 device_printf(fc->dev, "malloc failed\n");
1930 goto sidout;
1931 }
1932 for (i = 0; i < plen / 4; i ++)
1933 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1934#if 1
1935 /* pending all pre-bus_reset packets */
1936 fwohci_txd(sc, &sc->atrq);
1937 fwohci_txd(sc, &sc->atrs);
1938 fwohci_arcv(sc, &sc->arrs, -1);
1939 fwohci_arcv(sc, &sc->arrq, -1);
1940 fw_drain_txq(fc);
1941#endif
1942 fw_sidrcv(fc, buf, plen);
1943 free(buf, M_FW);
1944 }
1945sidout:
1946 if((stat & OHCI_INT_DMA_ATRQ )){
1947#ifndef ACK_ALL
1948 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1949#endif
1950 fwohci_txd(sc, &(sc->atrq));
1951 }
1952 if((stat & OHCI_INT_DMA_ATRS )){
1953#ifndef ACK_ALL
1954 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1955#endif
1956 fwohci_txd(sc, &(sc->atrs));
1957 }
1958 if((stat & OHCI_INT_PW_ERR )){
1959#ifndef ACK_ALL
1960 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1961#endif
1962 device_printf(fc->dev, "posted write error\n");
1963 }
1964 if((stat & OHCI_INT_ERR )){
1965#ifndef ACK_ALL
1966 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1967#endif
1968 device_printf(fc->dev, "unrecoverable error\n");
1969 }
1970 if((stat & OHCI_INT_PHY_INT)) {
1971#ifndef ACK_ALL
1972 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1973#endif
1974 device_printf(fc->dev, "phy int\n");
1975 }
1976
1977 return;
1978}
1979
1980#if FWOHCI_TASKQUEUE
1981static void
1982fwohci_complete(void *arg, int pending)
1983{
1984 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1985 u_int32_t stat;
1986
1987again:
1988 stat = atomic_readandclear_int(&sc->intstat);
1989 if (stat)
1990 fwohci_intr_body(sc, stat, -1);
1991 else
1992 return;
1993 goto again;
1994}
1995#endif
1996
1997static u_int32_t
1998fwochi_check_stat(struct fwohci_softc *sc)
1999{
2000 u_int32_t stat, irstat, itstat;
2001
2002 stat = OREAD(sc, FWOHCI_INTSTAT);
2003 if (stat == 0xffffffff) {
2004 device_printf(sc->fc.dev,
2005 "device physically ejected?\n");
2006 return(stat);
2007 }
2008#ifdef ACK_ALL
2009 if (stat)
2010 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
2011#endif
2012 if (stat & OHCI_INT_DMA_IR) {
2013 irstat = OREAD(sc, OHCI_IR_STAT);
2014 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2015 atomic_set_int(&sc->irstat, irstat);
2016 }
2017 if (stat & OHCI_INT_DMA_IT) {
2018 itstat = OREAD(sc, OHCI_IT_STAT);
2019 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2020 atomic_set_int(&sc->itstat, itstat);
2021 }
2022 return(stat);
2023}
2024
2025void
2026fwohci_intr(void *arg)
2027{
2028 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2029 u_int32_t stat;
2030#if !FWOHCI_TASKQUEUE
2031 u_int32_t bus_reset = 0;
2032#endif
2033
2034 if (!(sc->intmask & OHCI_INT_EN)) {
2035 /* polling mode */
2036 return;
2037 }
2038
2039#if !FWOHCI_TASKQUEUE
2040again:
2041#endif
2042 stat = fwochi_check_stat(sc);
2043 if (stat == 0 || stat == 0xffffffff)
2044 return;
2045#if FWOHCI_TASKQUEUE
2046 atomic_set_int(&sc->intstat, stat);
2047 /* XXX mask bus reset intr. during bus reset phase */
2048 if (stat)
2049 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete);
2050#else
2051 /* We cannot clear bus reset event during bus reset phase */
2052 if ((stat & ~bus_reset) == 0)
2053 return;
2054 bus_reset = stat & OHCI_INT_PHY_BUS_R;
2055 fwohci_intr_body(sc, stat, -1);
2056 goto again;
2057#endif
2058}
2059
2060void
2061fwohci_poll(struct firewire_comm *fc, int quick, int count)
2062{
2063 int s;
2064 u_int32_t stat;
2065 struct fwohci_softc *sc;
2066
2067
2068 sc = (struct fwohci_softc *)fc;
2069 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2070 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2071 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2072#if 0
2073 if (!quick) {
2074#else
2075 if (1) {
2076#endif
2077 stat = fwochi_check_stat(sc);
2078 if (stat == 0 || stat == 0xffffffff)
2079 return;
2080 }
2081 s = splfw();
2082 fwohci_intr_body(sc, stat, count);
2083 splx(s);
2084}
2085
2086static void
2087fwohci_set_intr(struct firewire_comm *fc, int enable)
2088{
2089 struct fwohci_softc *sc;
2090
2091 sc = (struct fwohci_softc *)fc;
2092 if (bootverbose)
2093 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2094 if (enable) {
2095 sc->intmask |= OHCI_INT_EN;
2096 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2097 } else {
2098 sc->intmask &= ~OHCI_INT_EN;
2099 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2100 }
2101}
2102
2103static void
2104fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2105{
2106 struct firewire_comm *fc = &sc->fc;
| 1636
1637#if 1 /* XXX for if_fwe */
1638 if (chunk->mbuf != NULL) {
1639 db_tr = (struct fwohcidb_tr *)(chunk->start);
1640 db_tr->dbcnt = 1;
1641 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1642 chunk->mbuf, fwohci_execute_db2, db_tr,
1643 /* flags */0);
1644 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1645 OHCI_UPDATE | OHCI_INPUT_LAST |
1646 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1647 }
1648#endif
1649 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1650 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1651 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1652 if (prev != NULL) {
1653 db = ((struct fwohcidb_tr *)(prev->end))->db;
1654 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1655 }
1656 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1657 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1658 prev = chunk;
1659 }
1660 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1661 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1662 splx(s);
1663 stat = OREAD(sc, OHCI_IRCTL(dmach));
1664 if (stat & OHCI_CNTL_DMA_ACTIVE)
1665 return 0;
1666 if (stat & OHCI_CNTL_DMA_RUN) {
1667 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1668 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1669 }
1670
1671 if (firewire_debug)
1672 printf("start IR DMA 0x%x\n", stat);
1673 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1674 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1675 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1676 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1677 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1678 OWRITE(sc, OHCI_IRCMD(dmach),
1679 ((struct fwohcidb_tr *)(first->start))->bus_addr
1680 | dbch->ndesc);
1681 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1682 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1683#if 0
1684 dump_db(sc, IRX_CH + dmach);
1685#endif
1686 return err;
1687}
1688
1689int
1690fwohci_stop(struct fwohci_softc *sc, device_t dev)
1691{
1692 u_int i;
1693
1694/* Now stopping all DMA channel */
1695 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1696 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1697 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1698 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1699
1700 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1701 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1702 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1703 }
1704
1705/* FLUSH FIFO and reset Transmitter/Reciever */
1706 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1707
1708/* Stop interrupt */
1709 OWRITE(sc, FWOHCI_INTMASKCLR,
1710 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1711 | OHCI_INT_PHY_INT
1712 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1713 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1714 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1715 | OHCI_INT_PHY_BUS_R);
1716
1717 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1718 fw_drain_txq(&sc->fc);
1719
1720/* XXX Link down? Bus reset? */
1721 return 0;
1722}
1723
1724int
1725fwohci_resume(struct fwohci_softc *sc, device_t dev)
1726{
1727 int i;
1728 struct fw_xferq *ir;
1729 struct fw_bulkxfer *chunk;
1730
1731 fwohci_reset(sc, dev);
1732 /* XXX resume isochronus receive automatically. (how about TX?) */
1733 for(i = 0; i < sc->fc.nisodma; i ++) {
1734 ir = &sc->ir[i].xferq;
1735 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1736 device_printf(sc->fc.dev,
1737 "resume iso receive ch: %d\n", i);
1738 ir->flag &= ~FWXFERQ_RUNNING;
1739 /* requeue stdma to stfree */
1740 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1741 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1742 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1743 }
1744 sc->fc.irx_enable(&sc->fc, i);
1745 }
1746 }
1747
1748 bus_generic_resume(dev);
1749 sc->fc.ibr(&sc->fc);
1750 return 0;
1751}
1752
1753#define ACK_ALL
1754static void
1755fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1756{
1757 u_int32_t irstat, itstat;
1758 u_int i;
1759 struct firewire_comm *fc = (struct firewire_comm *)sc;
1760
1761#ifdef OHCI_DEBUG
1762 if(stat & OREAD(sc, FWOHCI_INTMASK))
1763 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1764 stat & OHCI_INT_EN ? "DMA_EN ":"",
1765 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1766 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1767 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1768 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1769 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1770 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1771 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1772 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1773 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1774 stat & OHCI_INT_PHY_SID ? "SID ":"",
1775 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1776 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1777 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1778 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1779 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1780 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1781 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1782 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1783 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1784 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1785 stat, OREAD(sc, FWOHCI_INTMASK)
1786 );
1787#endif
1788/* Bus reset */
1789 if(stat & OHCI_INT_PHY_BUS_R ){
1790 if (fc->status == FWBUSRESET)
1791 goto busresetout;
1792 /* Disable bus reset interrupt until sid recv. */
1793 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1794
1795 device_printf(fc->dev, "BUS reset\n");
1796 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1797 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1798
1799 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1800 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1801 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1802 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1803
1804#ifndef ACK_ALL
1805 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1806#endif
1807 fw_busreset(fc);
1808 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1809 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
1810 }
1811busresetout:
1812 if((stat & OHCI_INT_DMA_IR )){
1813#ifndef ACK_ALL
1814 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1815#endif
1816#if __FreeBSD_version >= 500000
1817 irstat = atomic_readandclear_int(&sc->irstat);
1818#else
1819 irstat = sc->irstat;
1820 sc->irstat = 0;
1821#endif
1822 for(i = 0; i < fc->nisodma ; i++){
1823 struct fwohci_dbch *dbch;
1824
1825 if((irstat & (1 << i)) != 0){
1826 dbch = &sc->ir[i];
1827 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1828 device_printf(sc->fc.dev,
1829 "dma(%d) not active\n", i);
1830 continue;
1831 }
1832 fwohci_rbuf_update(sc, i);
1833 }
1834 }
1835 }
1836 if((stat & OHCI_INT_DMA_IT )){
1837#ifndef ACK_ALL
1838 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1839#endif
1840#if __FreeBSD_version >= 500000
1841 itstat = atomic_readandclear_int(&sc->itstat);
1842#else
1843 itstat = sc->itstat;
1844 sc->itstat = 0;
1845#endif
1846 for(i = 0; i < fc->nisodma ; i++){
1847 if((itstat & (1 << i)) != 0){
1848 fwohci_tbuf_update(sc, i);
1849 }
1850 }
1851 }
1852 if((stat & OHCI_INT_DMA_PRRS )){
1853#ifndef ACK_ALL
1854 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1855#endif
1856#if 0
1857 dump_dma(sc, ARRS_CH);
1858 dump_db(sc, ARRS_CH);
1859#endif
1860 fwohci_arcv(sc, &sc->arrs, count);
1861 }
1862 if((stat & OHCI_INT_DMA_PRRQ )){
1863#ifndef ACK_ALL
1864 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1865#endif
1866#if 0
1867 dump_dma(sc, ARRQ_CH);
1868 dump_db(sc, ARRQ_CH);
1869#endif
1870 fwohci_arcv(sc, &sc->arrq, count);
1871 }
1872 if(stat & OHCI_INT_PHY_SID){
1873 u_int32_t *buf, node_id;
1874 int plen;
1875
1876#ifndef ACK_ALL
1877 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1878#endif
1879 /* Enable bus reset interrupt */
1880 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1881 /* Allow async. request to us */
1882 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1883 /* XXX insecure ?? */
1884 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1885 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1886 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1887 /* Set ATRetries register */
1888 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1889/*
1890** Checking whether the node is root or not. If root, turn on
1891** cycle master.
1892*/
1893 node_id = OREAD(sc, FWOHCI_NODEID);
1894 plen = OREAD(sc, OHCI_SID_CNT);
1895
1896 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1897 node_id, (plen >> 16) & 0xff);
1898 if (!(node_id & OHCI_NODE_VALID)) {
1899 printf("Bus reset failure\n");
1900 goto sidout;
1901 }
1902 if (node_id & OHCI_NODE_ROOT) {
1903 printf("CYCLEMASTER mode\n");
1904 OWRITE(sc, OHCI_LNKCTL,
1905 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1906 } else {
1907 printf("non CYCLEMASTER mode\n");
1908 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1909 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1910 }
1911 fc->nodeid = node_id & 0x3f;
1912
1913 if (plen & OHCI_SID_ERR) {
1914 device_printf(fc->dev, "SID Error\n");
1915 goto sidout;
1916 }
1917 plen &= OHCI_SID_CNT_MASK;
1918 if (plen < 4 || plen > OHCI_SIDSIZE) {
1919 device_printf(fc->dev, "invalid SID len = %d\n", plen);
1920 goto sidout;
1921 }
1922 plen -= 4; /* chop control info */
1923 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
1924 if (buf == NULL) {
1925 device_printf(fc->dev, "malloc failed\n");
1926 goto sidout;
1927 }
1928 for (i = 0; i < plen / 4; i ++)
1929 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1930#if 1
1931 /* pending all pre-bus_reset packets */
1932 fwohci_txd(sc, &sc->atrq);
1933 fwohci_txd(sc, &sc->atrs);
1934 fwohci_arcv(sc, &sc->arrs, -1);
1935 fwohci_arcv(sc, &sc->arrq, -1);
1936 fw_drain_txq(fc);
1937#endif
1938 fw_sidrcv(fc, buf, plen);
1939 free(buf, M_FW);
1940 }
1941sidout:
1942 if((stat & OHCI_INT_DMA_ATRQ )){
1943#ifndef ACK_ALL
1944 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1945#endif
1946 fwohci_txd(sc, &(sc->atrq));
1947 }
1948 if((stat & OHCI_INT_DMA_ATRS )){
1949#ifndef ACK_ALL
1950 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1951#endif
1952 fwohci_txd(sc, &(sc->atrs));
1953 }
1954 if((stat & OHCI_INT_PW_ERR )){
1955#ifndef ACK_ALL
1956 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1957#endif
1958 device_printf(fc->dev, "posted write error\n");
1959 }
1960 if((stat & OHCI_INT_ERR )){
1961#ifndef ACK_ALL
1962 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1963#endif
1964 device_printf(fc->dev, "unrecoverable error\n");
1965 }
1966 if((stat & OHCI_INT_PHY_INT)) {
1967#ifndef ACK_ALL
1968 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1969#endif
1970 device_printf(fc->dev, "phy int\n");
1971 }
1972
1973 return;
1974}
1975
1976#if FWOHCI_TASKQUEUE
1977static void
1978fwohci_complete(void *arg, int pending)
1979{
1980 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1981 u_int32_t stat;
1982
1983again:
1984 stat = atomic_readandclear_int(&sc->intstat);
1985 if (stat)
1986 fwohci_intr_body(sc, stat, -1);
1987 else
1988 return;
1989 goto again;
1990}
1991#endif
1992
1993static u_int32_t
1994fwochi_check_stat(struct fwohci_softc *sc)
1995{
1996 u_int32_t stat, irstat, itstat;
1997
1998 stat = OREAD(sc, FWOHCI_INTSTAT);
1999 if (stat == 0xffffffff) {
2000 device_printf(sc->fc.dev,
2001 "device physically ejected?\n");
2002 return(stat);
2003 }
2004#ifdef ACK_ALL
2005 if (stat)
2006 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
2007#endif
2008 if (stat & OHCI_INT_DMA_IR) {
2009 irstat = OREAD(sc, OHCI_IR_STAT);
2010 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2011 atomic_set_int(&sc->irstat, irstat);
2012 }
2013 if (stat & OHCI_INT_DMA_IT) {
2014 itstat = OREAD(sc, OHCI_IT_STAT);
2015 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2016 atomic_set_int(&sc->itstat, itstat);
2017 }
2018 return(stat);
2019}
2020
2021void
2022fwohci_intr(void *arg)
2023{
2024 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2025 u_int32_t stat;
2026#if !FWOHCI_TASKQUEUE
2027 u_int32_t bus_reset = 0;
2028#endif
2029
2030 if (!(sc->intmask & OHCI_INT_EN)) {
2031 /* polling mode */
2032 return;
2033 }
2034
2035#if !FWOHCI_TASKQUEUE
2036again:
2037#endif
2038 stat = fwochi_check_stat(sc);
2039 if (stat == 0 || stat == 0xffffffff)
2040 return;
2041#if FWOHCI_TASKQUEUE
2042 atomic_set_int(&sc->intstat, stat);
2043 /* XXX mask bus reset intr. during bus reset phase */
2044 if (stat)
2045 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete);
2046#else
2047 /* We cannot clear bus reset event during bus reset phase */
2048 if ((stat & ~bus_reset) == 0)
2049 return;
2050 bus_reset = stat & OHCI_INT_PHY_BUS_R;
2051 fwohci_intr_body(sc, stat, -1);
2052 goto again;
2053#endif
2054}
2055
2056void
2057fwohci_poll(struct firewire_comm *fc, int quick, int count)
2058{
2059 int s;
2060 u_int32_t stat;
2061 struct fwohci_softc *sc;
2062
2063
2064 sc = (struct fwohci_softc *)fc;
2065 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2066 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2067 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2068#if 0
2069 if (!quick) {
2070#else
2071 if (1) {
2072#endif
2073 stat = fwochi_check_stat(sc);
2074 if (stat == 0 || stat == 0xffffffff)
2075 return;
2076 }
2077 s = splfw();
2078 fwohci_intr_body(sc, stat, count);
2079 splx(s);
2080}
2081
2082static void
2083fwohci_set_intr(struct firewire_comm *fc, int enable)
2084{
2085 struct fwohci_softc *sc;
2086
2087 sc = (struct fwohci_softc *)fc;
2088 if (bootverbose)
2089 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2090 if (enable) {
2091 sc->intmask |= OHCI_INT_EN;
2092 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2093 } else {
2094 sc->intmask &= ~OHCI_INT_EN;
2095 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2096 }
2097}
2098
2099static void
2100fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2101{
2102 struct firewire_comm *fc = &sc->fc;
|
2107 volatile struct fwohcidb *db;
| 2103 struct fwohcidb *db;
|
2108 struct fw_bulkxfer *chunk;
2109 struct fw_xferq *it;
2110 u_int32_t stat, count;
2111 int s, w=0, ldesc;
2112
2113 it = fc->it[dmach];
2114 ldesc = sc->it[dmach].ndesc - 1;
2115 s = splfw(); /* unnecessary ? */
2116 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2117 if (firewire_debug)
2118 dump_db(sc, ITX_CH + dmach);
2119 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2120 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2121 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2122 >> OHCI_STATUS_SHIFT;
2123 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2124 /* timestamp */
2125 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2126 & OHCI_COUNT_MASK;
2127 if (stat == 0)
2128 break;
2129 STAILQ_REMOVE_HEAD(&it->stdma, link);
2130 switch (stat & FWOHCIEV_MASK){
2131 case FWOHCIEV_ACKCOMPL:
2132#if 0
2133 device_printf(fc->dev, "0x%08x\n", count);
2134#endif
2135 break;
2136 default:
2137 device_printf(fc->dev,
2138 "Isochronous transmit err %02x(%s)\n",
2139 stat, fwohcicode[stat & 0x1f]);
2140 }
2141 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2142 w++;
2143 }
2144 splx(s);
2145 if (w)
2146 wakeup(it);
2147}
2148
2149static void
2150fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2151{
2152 struct firewire_comm *fc = &sc->fc;
| 2104 struct fw_bulkxfer *chunk;
2105 struct fw_xferq *it;
2106 u_int32_t stat, count;
2107 int s, w=0, ldesc;
2108
2109 it = fc->it[dmach];
2110 ldesc = sc->it[dmach].ndesc - 1;
2111 s = splfw(); /* unnecessary ? */
2112 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2113 if (firewire_debug)
2114 dump_db(sc, ITX_CH + dmach);
2115 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2116 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2117 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2118 >> OHCI_STATUS_SHIFT;
2119 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2120 /* timestamp */
2121 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2122 & OHCI_COUNT_MASK;
2123 if (stat == 0)
2124 break;
2125 STAILQ_REMOVE_HEAD(&it->stdma, link);
2126 switch (stat & FWOHCIEV_MASK){
2127 case FWOHCIEV_ACKCOMPL:
2128#if 0
2129 device_printf(fc->dev, "0x%08x\n", count);
2130#endif
2131 break;
2132 default:
2133 device_printf(fc->dev,
2134 "Isochronous transmit err %02x(%s)\n",
2135 stat, fwohcicode[stat & 0x1f]);
2136 }
2137 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2138 w++;
2139 }
2140 splx(s);
2141 if (w)
2142 wakeup(it);
2143}
2144
2145static void
2146fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2147{
2148 struct firewire_comm *fc = &sc->fc;
|
2153 volatile struct fwohcidb_tr *db_tr;
| 2149 struct fwohcidb_tr *db_tr;
|
2154 struct fw_bulkxfer *chunk;
2155 struct fw_xferq *ir;
2156 u_int32_t stat;
2157 int s, w=0, ldesc;
2158
2159 ir = fc->ir[dmach];
2160 ldesc = sc->ir[dmach].ndesc - 1;
2161#if 0
2162 dump_db(sc, dmach);
2163#endif
2164 s = splfw();
2165 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2166 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2167 db_tr = (struct fwohcidb_tr *)chunk->end;
2168 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2169 >> OHCI_STATUS_SHIFT;
2170 if (stat == 0)
2171 break;
2172
2173 if (chunk->mbuf != NULL) {
2174 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2175 BUS_DMASYNC_POSTREAD);
2176 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2177 } else if (ir->buf != NULL) {
2178 fwdma_sync_multiseg(ir->buf, chunk->poffset,
2179 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2180 } else {
2181 /* XXX */
2182 printf("fwohci_rbuf_update: this shouldn't happend\n");
2183 }
2184
2185 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2186 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2187 switch (stat & FWOHCIEV_MASK) {
2188 case FWOHCIEV_ACKCOMPL:
2189 chunk->resp = 0;
2190 break;
2191 default:
2192 chunk->resp = EINVAL;
2193 device_printf(fc->dev,
2194 "Isochronous receive err %02x(%s)\n",
2195 stat, fwohcicode[stat & 0x1f]);
2196 }
2197 w++;
2198 }
2199 splx(s);
2200 if (w) {
2201 if (ir->flag & FWXFERQ_HANDLER)
2202 ir->hand(ir);
2203 else
2204 wakeup(ir);
2205 }
2206}
2207
2208void
2209dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2210{
2211 u_int32_t off, cntl, stat, cmd, match;
2212
2213 if(ch == 0){
2214 off = OHCI_ATQOFF;
2215 }else if(ch == 1){
2216 off = OHCI_ATSOFF;
2217 }else if(ch == 2){
2218 off = OHCI_ARQOFF;
2219 }else if(ch == 3){
2220 off = OHCI_ARSOFF;
2221 }else if(ch < IRX_CH){
2222 off = OHCI_ITCTL(ch - ITX_CH);
2223 }else{
2224 off = OHCI_IRCTL(ch - IRX_CH);
2225 }
2226 cntl = stat = OREAD(sc, off);
2227 cmd = OREAD(sc, off + 0xc);
2228 match = OREAD(sc, off + 0x10);
2229
2230 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2231 ch,
2232 cntl,
2233 cmd,
2234 match);
2235 stat &= 0xffff ;
2236 if (stat) {
2237 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2238 ch,
2239 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2240 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2241 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2242 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2243 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2244 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2245 fwohcicode[stat & 0x1f],
2246 stat & 0x1f
2247 );
2248 }else{
2249 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2250 }
2251}
2252
2253void
2254dump_db(struct fwohci_softc *sc, u_int32_t ch)
2255{
2256 struct fwohci_dbch *dbch;
2257 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
| 2150 struct fw_bulkxfer *chunk;
2151 struct fw_xferq *ir;
2152 u_int32_t stat;
2153 int s, w=0, ldesc;
2154
2155 ir = fc->ir[dmach];
2156 ldesc = sc->ir[dmach].ndesc - 1;
2157#if 0
2158 dump_db(sc, dmach);
2159#endif
2160 s = splfw();
2161 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2162 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2163 db_tr = (struct fwohcidb_tr *)chunk->end;
2164 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2165 >> OHCI_STATUS_SHIFT;
2166 if (stat == 0)
2167 break;
2168
2169 if (chunk->mbuf != NULL) {
2170 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2171 BUS_DMASYNC_POSTREAD);
2172 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2173 } else if (ir->buf != NULL) {
2174 fwdma_sync_multiseg(ir->buf, chunk->poffset,
2175 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2176 } else {
2177 /* XXX */
2178 printf("fwohci_rbuf_update: this shouldn't happend\n");
2179 }
2180
2181 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2182 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2183 switch (stat & FWOHCIEV_MASK) {
2184 case FWOHCIEV_ACKCOMPL:
2185 chunk->resp = 0;
2186 break;
2187 default:
2188 chunk->resp = EINVAL;
2189 device_printf(fc->dev,
2190 "Isochronous receive err %02x(%s)\n",
2191 stat, fwohcicode[stat & 0x1f]);
2192 }
2193 w++;
2194 }
2195 splx(s);
2196 if (w) {
2197 if (ir->flag & FWXFERQ_HANDLER)
2198 ir->hand(ir);
2199 else
2200 wakeup(ir);
2201 }
2202}
2203
2204void
2205dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2206{
2207 u_int32_t off, cntl, stat, cmd, match;
2208
2209 if(ch == 0){
2210 off = OHCI_ATQOFF;
2211 }else if(ch == 1){
2212 off = OHCI_ATSOFF;
2213 }else if(ch == 2){
2214 off = OHCI_ARQOFF;
2215 }else if(ch == 3){
2216 off = OHCI_ARSOFF;
2217 }else if(ch < IRX_CH){
2218 off = OHCI_ITCTL(ch - ITX_CH);
2219 }else{
2220 off = OHCI_IRCTL(ch - IRX_CH);
2221 }
2222 cntl = stat = OREAD(sc, off);
2223 cmd = OREAD(sc, off + 0xc);
2224 match = OREAD(sc, off + 0x10);
2225
2226 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2227 ch,
2228 cntl,
2229 cmd,
2230 match);
2231 stat &= 0xffff ;
2232 if (stat) {
2233 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2234 ch,
2235 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2236 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2237 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2238 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2239 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2240 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2241 fwohcicode[stat & 0x1f],
2242 stat & 0x1f
2243 );
2244 }else{
2245 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2246 }
2247}
2248
2249void
2250dump_db(struct fwohci_softc *sc, u_int32_t ch)
2251{
2252 struct fwohci_dbch *dbch;
2253 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
|
2258 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL;
| 2254 struct fwohcidb *curr = NULL, *prev, *next = NULL;
|
2259 int idb, jdb;
2260 u_int32_t cmd, off;
2261 if(ch == 0){
2262 off = OHCI_ATQOFF;
2263 dbch = &sc->atrq;
2264 }else if(ch == 1){
2265 off = OHCI_ATSOFF;
2266 dbch = &sc->atrs;
2267 }else if(ch == 2){
2268 off = OHCI_ARQOFF;
2269 dbch = &sc->arrq;
2270 }else if(ch == 3){
2271 off = OHCI_ARSOFF;
2272 dbch = &sc->arrs;
2273 }else if(ch < IRX_CH){
2274 off = OHCI_ITCTL(ch - ITX_CH);
2275 dbch = &sc->it[ch - ITX_CH];
2276 }else {
2277 off = OHCI_IRCTL(ch - IRX_CH);
2278 dbch = &sc->ir[ch - IRX_CH];
2279 }
2280 cmd = OREAD(sc, off + 0xc);
2281
2282 if( dbch->ndb == 0 ){
2283 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2284 return;
2285 }
2286 pp = dbch->top;
2287 prev = pp->db;
2288 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2289 if(pp == NULL){
2290 curr = NULL;
2291 goto outdb;
2292 }
2293 cp = STAILQ_NEXT(pp, link);
2294 if(cp == NULL){
2295 curr = NULL;
2296 goto outdb;
2297 }
2298 np = STAILQ_NEXT(cp, link);
2299 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2300 if ((cmd & 0xfffffff0) == cp->bus_addr) {
2301 curr = cp->db;
2302 if(np != NULL){
2303 next = np->db;
2304 }else{
2305 next = NULL;
2306 }
2307 goto outdb;
2308 }
2309 }
2310 pp = STAILQ_NEXT(pp, link);
2311 prev = pp->db;
2312 }
2313outdb:
2314 if( curr != NULL){
2315#if 0
2316 printf("Prev DB %d\n", ch);
2317 print_db(pp, prev, ch, dbch->ndesc);
2318#endif
2319 printf("Current DB %d\n", ch);
2320 print_db(cp, curr, ch, dbch->ndesc);
2321#if 0
2322 printf("Next DB %d\n", ch);
2323 print_db(np, next, ch, dbch->ndesc);
2324#endif
2325 }else{
2326 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2327 }
2328 return;
2329}
2330
2331void
| 2255 int idb, jdb;
2256 u_int32_t cmd, off;
2257 if(ch == 0){
2258 off = OHCI_ATQOFF;
2259 dbch = &sc->atrq;
2260 }else if(ch == 1){
2261 off = OHCI_ATSOFF;
2262 dbch = &sc->atrs;
2263 }else if(ch == 2){
2264 off = OHCI_ARQOFF;
2265 dbch = &sc->arrq;
2266 }else if(ch == 3){
2267 off = OHCI_ARSOFF;
2268 dbch = &sc->arrs;
2269 }else if(ch < IRX_CH){
2270 off = OHCI_ITCTL(ch - ITX_CH);
2271 dbch = &sc->it[ch - ITX_CH];
2272 }else {
2273 off = OHCI_IRCTL(ch - IRX_CH);
2274 dbch = &sc->ir[ch - IRX_CH];
2275 }
2276 cmd = OREAD(sc, off + 0xc);
2277
2278 if( dbch->ndb == 0 ){
2279 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2280 return;
2281 }
2282 pp = dbch->top;
2283 prev = pp->db;
2284 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2285 if(pp == NULL){
2286 curr = NULL;
2287 goto outdb;
2288 }
2289 cp = STAILQ_NEXT(pp, link);
2290 if(cp == NULL){
2291 curr = NULL;
2292 goto outdb;
2293 }
2294 np = STAILQ_NEXT(cp, link);
2295 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2296 if ((cmd & 0xfffffff0) == cp->bus_addr) {
2297 curr = cp->db;
2298 if(np != NULL){
2299 next = np->db;
2300 }else{
2301 next = NULL;
2302 }
2303 goto outdb;
2304 }
2305 }
2306 pp = STAILQ_NEXT(pp, link);
2307 prev = pp->db;
2308 }
2309outdb:
2310 if( curr != NULL){
2311#if 0
2312 printf("Prev DB %d\n", ch);
2313 print_db(pp, prev, ch, dbch->ndesc);
2314#endif
2315 printf("Current DB %d\n", ch);
2316 print_db(cp, curr, ch, dbch->ndesc);
2317#if 0
2318 printf("Next DB %d\n", ch);
2319 print_db(np, next, ch, dbch->ndesc);
2320#endif
2321 }else{
2322 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2323 }
2324 return;
2325}
2326
2327void
|
2332print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db,
| 2328print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
|
2333 u_int32_t ch, u_int32_t max)
2334{
2335 fwohcireg_t stat;
2336 int i, key;
2337 u_int32_t cmd, res;
2338
2339 if(db == NULL){
2340 printf("No Descriptor is found\n");
2341 return;
2342 }
2343
2344 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2345 ch,
2346 "Current",
2347 "OP ",
2348 "KEY",
2349 "INT",
2350 "BR ",
2351 "len",
2352 "Addr",
2353 "Depend",
2354 "Stat",
2355 "Cnt");
2356 for( i = 0 ; i <= max ; i ++){
2357 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2358 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2359 key = cmd & OHCI_KEY_MASK;
2360 stat = res >> OHCI_STATUS_SHIFT;
2361#if __FreeBSD_version >= 500000
2362 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2363 (uintmax_t)db_tr->bus_addr,
2364#else
2365 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2366 db_tr->bus_addr,
2367#endif
2368 dbcode[(cmd >> 28) & 0xf],
2369 dbkey[(cmd >> 24) & 0x7],
2370 dbcond[(cmd >> 20) & 0x3],
2371 dbcond[(cmd >> 18) & 0x3],
2372 cmd & OHCI_COUNT_MASK,
2373 FWOHCI_DMA_READ(db[i].db.desc.addr),
2374 FWOHCI_DMA_READ(db[i].db.desc.depend),
2375 stat,
2376 res & OHCI_COUNT_MASK);
2377 if(stat & 0xff00){
2378 printf(" %s%s%s%s%s%s %s(%x)\n",
2379 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2380 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2381 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2382 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2383 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2384 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2385 fwohcicode[stat & 0x1f],
2386 stat & 0x1f
2387 );
2388 }else{
2389 printf(" Nostat\n");
2390 }
2391 if(key == OHCI_KEY_ST2 ){
2392 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2393 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2394 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2395 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2396 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2397 }
2398 if(key == OHCI_KEY_DEVICE){
2399 return;
2400 }
2401 if((cmd & OHCI_BRANCH_MASK)
2402 == OHCI_BRANCH_ALWAYS){
2403 return;
2404 }
2405 if((cmd & OHCI_CMD_MASK)
2406 == OHCI_OUTPUT_LAST){
2407 return;
2408 }
2409 if((cmd & OHCI_CMD_MASK)
2410 == OHCI_INPUT_LAST){
2411 return;
2412 }
2413 if(key == OHCI_KEY_ST2 ){
2414 i++;
2415 }
2416 }
2417 return;
2418}
2419
2420void
2421fwohci_ibr(struct firewire_comm *fc)
2422{
2423 struct fwohci_softc *sc;
2424 u_int32_t fun;
2425
2426 device_printf(fc->dev, "Initiate bus reset\n");
2427 sc = (struct fwohci_softc *)fc;
2428
2429 /*
2430 * Set root hold-off bit so that non cyclemaster capable node
2431 * shouldn't became the root node.
2432 */
2433#if 1
2434 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2435 fun |= FW_PHY_IBR | FW_PHY_RHB;
2436 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2437#else /* Short bus reset */
2438 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2439 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2440 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2441#endif
2442}
2443
2444void
2445fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2446{
2447 struct fwohcidb_tr *db_tr, *fdb_tr;
2448 struct fwohci_dbch *dbch;
| 2329 u_int32_t ch, u_int32_t max)
2330{
2331 fwohcireg_t stat;
2332 int i, key;
2333 u_int32_t cmd, res;
2334
2335 if(db == NULL){
2336 printf("No Descriptor is found\n");
2337 return;
2338 }
2339
2340 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2341 ch,
2342 "Current",
2343 "OP ",
2344 "KEY",
2345 "INT",
2346 "BR ",
2347 "len",
2348 "Addr",
2349 "Depend",
2350 "Stat",
2351 "Cnt");
2352 for( i = 0 ; i <= max ; i ++){
2353 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2354 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2355 key = cmd & OHCI_KEY_MASK;
2356 stat = res >> OHCI_STATUS_SHIFT;
2357#if __FreeBSD_version >= 500000
2358 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2359 (uintmax_t)db_tr->bus_addr,
2360#else
2361 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2362 db_tr->bus_addr,
2363#endif
2364 dbcode[(cmd >> 28) & 0xf],
2365 dbkey[(cmd >> 24) & 0x7],
2366 dbcond[(cmd >> 20) & 0x3],
2367 dbcond[(cmd >> 18) & 0x3],
2368 cmd & OHCI_COUNT_MASK,
2369 FWOHCI_DMA_READ(db[i].db.desc.addr),
2370 FWOHCI_DMA_READ(db[i].db.desc.depend),
2371 stat,
2372 res & OHCI_COUNT_MASK);
2373 if(stat & 0xff00){
2374 printf(" %s%s%s%s%s%s %s(%x)\n",
2375 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2376 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2377 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2378 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2379 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2380 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2381 fwohcicode[stat & 0x1f],
2382 stat & 0x1f
2383 );
2384 }else{
2385 printf(" Nostat\n");
2386 }
2387 if(key == OHCI_KEY_ST2 ){
2388 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2389 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2390 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2391 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2392 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2393 }
2394 if(key == OHCI_KEY_DEVICE){
2395 return;
2396 }
2397 if((cmd & OHCI_BRANCH_MASK)
2398 == OHCI_BRANCH_ALWAYS){
2399 return;
2400 }
2401 if((cmd & OHCI_CMD_MASK)
2402 == OHCI_OUTPUT_LAST){
2403 return;
2404 }
2405 if((cmd & OHCI_CMD_MASK)
2406 == OHCI_INPUT_LAST){
2407 return;
2408 }
2409 if(key == OHCI_KEY_ST2 ){
2410 i++;
2411 }
2412 }
2413 return;
2414}
2415
2416void
2417fwohci_ibr(struct firewire_comm *fc)
2418{
2419 struct fwohci_softc *sc;
2420 u_int32_t fun;
2421
2422 device_printf(fc->dev, "Initiate bus reset\n");
2423 sc = (struct fwohci_softc *)fc;
2424
2425 /*
2426 * Set root hold-off bit so that non cyclemaster capable node
2427 * shouldn't became the root node.
2428 */
2429#if 1
2430 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2431 fun |= FW_PHY_IBR | FW_PHY_RHB;
2432 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2433#else /* Short bus reset */
2434 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2435 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2436 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2437#endif
2438}
2439
2440void
2441fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2442{
2443 struct fwohcidb_tr *db_tr, *fdb_tr;
2444 struct fwohci_dbch *dbch;
|
2449 volatile struct fwohcidb *db;
| 2445 struct fwohcidb *db;
|
2450 struct fw_pkt *fp;
| 2446 struct fw_pkt *fp;
|
2451 volatile struct fwohci_txpkthdr *ohcifp;
| 2447 struct fwohci_txpkthdr *ohcifp;
|
2452 unsigned short chtag;
2453 int idb;
2454
2455 dbch = &sc->it[dmach];
2456 chtag = sc->it[dmach].xferq.flag & 0xff;
2457
2458 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2459 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2460/*
2461device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2462*/
2463 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2464 db = db_tr->db;
2465 fp = (struct fw_pkt *)db_tr->buf;
| 2448 unsigned short chtag;
2449 int idb;
2450
2451 dbch = &sc->it[dmach];
2452 chtag = sc->it[dmach].xferq.flag & 0xff;
2453
2454 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2455 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2456/*
2457device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2458*/
2459 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2460 db = db_tr->db;
2461 fp = (struct fw_pkt *)db_tr->buf;
|
2466 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed;
| 2462 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
|
2467 ohcifp->mode.ld[0] = fp->mode.ld[0];
2468 ohcifp->mode.common.spd = 0 & 0x7;
2469 ohcifp->mode.stream.len = fp->mode.stream.len;
2470 ohcifp->mode.stream.chtag = chtag;
2471 ohcifp->mode.stream.tcode = 0xa;
2472#if BYTE_ORDER == BIG_ENDIAN
2473 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2474 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2475#endif
2476
2477 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2478 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2479 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2480#if 0 /* if bulkxfer->npackets changes */
2481 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2482 | OHCI_UPDATE
2483 | OHCI_BRANCH_ALWAYS;
2484 db[0].db.desc.depend =
2485 = db[dbch->ndesc - 1].db.desc.depend
2486 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2487#else
2488 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2489 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2490#endif
2491 bulkxfer->end = (caddr_t)db_tr;
2492 db_tr = STAILQ_NEXT(db_tr, link);
2493 }
2494 db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2495 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2496 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2497#if 0 /* if bulkxfer->npackets changes */
2498 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2499 /* OHCI 1.1 and above */
2500 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2501#endif
2502/*
2503 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2504 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2505device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2506*/
2507 return;
2508}
2509
2510static int
2511fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2512 int poffset)
2513{
| 2463 ohcifp->mode.ld[0] = fp->mode.ld[0];
2464 ohcifp->mode.common.spd = 0 & 0x7;
2465 ohcifp->mode.stream.len = fp->mode.stream.len;
2466 ohcifp->mode.stream.chtag = chtag;
2467 ohcifp->mode.stream.tcode = 0xa;
2468#if BYTE_ORDER == BIG_ENDIAN
2469 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2470 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2471#endif
2472
2473 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2474 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2475 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2476#if 0 /* if bulkxfer->npackets changes */
2477 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2478 | OHCI_UPDATE
2479 | OHCI_BRANCH_ALWAYS;
2480 db[0].db.desc.depend =
2481 = db[dbch->ndesc - 1].db.desc.depend
2482 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2483#else
2484 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2485 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2486#endif
2487 bulkxfer->end = (caddr_t)db_tr;
2488 db_tr = STAILQ_NEXT(db_tr, link);
2489 }
2490 db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2491 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2492 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2493#if 0 /* if bulkxfer->npackets changes */
2494 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2495 /* OHCI 1.1 and above */
2496 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2497#endif
2498/*
2499 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2500 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2501device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2502*/
2503 return;
2504}
2505
2506static int
2507fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2508 int poffset)
2509{
|
2514 volatile struct fwohcidb *db = db_tr->db;
| 2510 struct fwohcidb *db = db_tr->db;
|
2515 struct fw_xferq *it;
2516 int err = 0;
2517
2518 it = &dbch->xferq;
2519 if(it->buf == 0){
2520 err = EINVAL;
2521 return err;
2522 }
2523 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2524 db_tr->dbcnt = 3;
2525
2526 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2527 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2528 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
| 2511 struct fw_xferq *it;
2512 int err = 0;
2513
2514 it = &dbch->xferq;
2515 if(it->buf == 0){
2516 err = EINVAL;
2517 return err;
2518 }
2519 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2520 db_tr->dbcnt = 3;
2521
2522 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2523 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2524 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
|
2529 bzero((void *)(uintptr_t)(volatile void *)
2530 &db[1].db.immed[0], sizeof(db[1].db.immed));
| 2525 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
|
2531 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2532 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2533
2534 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2535 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2536#if 1
2537 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2538 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2539#endif
2540 return 0;
2541}
2542
2543int
2544fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2545 int poffset, struct fwdma_alloc *dummy_dma)
2546{
| 2526 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2527 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2528
2529 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2530 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2531#if 1
2532 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2533 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2534#endif
2535 return 0;
2536}
2537
2538int
2539fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2540 int poffset, struct fwdma_alloc *dummy_dma)
2541{
|
2547 volatile struct fwohcidb *db = db_tr->db;
| 2542 struct fwohcidb *db = db_tr->db;
|
2548 struct fw_xferq *ir;
2549 int i, ldesc;
2550 bus_addr_t dbuf[2];
2551 int dsiz[2];
2552
2553 ir = &dbch->xferq;
2554 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2555 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map,
2556 ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2557 if (db_tr->buf == NULL)
2558 return(ENOMEM);
2559 db_tr->dbcnt = 1;
2560 dsiz[0] = ir->psize;
2561 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2562 BUS_DMASYNC_PREREAD);
2563 } else {
2564 db_tr->dbcnt = 0;
2565 if (dummy_dma != NULL) {
2566 dsiz[db_tr->dbcnt] = sizeof(u_int32_t);
2567 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2568 }
2569 dsiz[db_tr->dbcnt] = ir->psize;
2570 if (ir->buf != NULL) {
2571 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2572 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2573 }
2574 db_tr->dbcnt++;
2575 }
2576 for(i = 0 ; i < db_tr->dbcnt ; i++){
2577 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2578 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2579 if (ir->flag & FWXFERQ_STREAM) {
2580 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2581 }
2582 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2583 }
2584 ldesc = db_tr->dbcnt - 1;
2585 if (ir->flag & FWXFERQ_STREAM) {
2586 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2587 }
2588 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2589 return 0;
2590}
2591
2592
2593static int
2594fwohci_arcv_swap(struct fw_pkt *fp, int len)
2595{
2596 struct fw_pkt *fp0;
2597 u_int32_t ld0;
| 2543 struct fw_xferq *ir;
2544 int i, ldesc;
2545 bus_addr_t dbuf[2];
2546 int dsiz[2];
2547
2548 ir = &dbch->xferq;
2549 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2550 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map,
2551 ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2552 if (db_tr->buf == NULL)
2553 return(ENOMEM);
2554 db_tr->dbcnt = 1;
2555 dsiz[0] = ir->psize;
2556 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2557 BUS_DMASYNC_PREREAD);
2558 } else {
2559 db_tr->dbcnt = 0;
2560 if (dummy_dma != NULL) {
2561 dsiz[db_tr->dbcnt] = sizeof(u_int32_t);
2562 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2563 }
2564 dsiz[db_tr->dbcnt] = ir->psize;
2565 if (ir->buf != NULL) {
2566 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2567 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2568 }
2569 db_tr->dbcnt++;
2570 }
2571 for(i = 0 ; i < db_tr->dbcnt ; i++){
2572 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2573 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2574 if (ir->flag & FWXFERQ_STREAM) {
2575 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2576 }
2577 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2578 }
2579 ldesc = db_tr->dbcnt - 1;
2580 if (ir->flag & FWXFERQ_STREAM) {
2581 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2582 }
2583 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2584 return 0;
2585}
2586
2587
2588static int
2589fwohci_arcv_swap(struct fw_pkt *fp, int len)
2590{
2591 struct fw_pkt *fp0;
2592 u_int32_t ld0;
|
2598 int slen;
| 2593 int slen, hlen;
|
2599#if BYTE_ORDER == BIG_ENDIAN
2600 int i;
2601#endif
2602
2603 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2604#if 0
2605 printf("ld0: x%08x\n", ld0);
2606#endif
2607 fp0 = (struct fw_pkt *)&ld0;
| 2594#if BYTE_ORDER == BIG_ENDIAN
2595 int i;
2596#endif
2597
2598 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2599#if 0
2600 printf("ld0: x%08x\n", ld0);
2601#endif
2602 fp0 = (struct fw_pkt *)&ld0;
|
| 2603 /* determine length to swap */
|
2608 switch (fp0->mode.common.tcode) {
2609 case FWTCODE_RREQQ:
2610 case FWTCODE_WRES:
2611 case FWTCODE_WREQQ:
2612 case FWTCODE_RRESQ:
2613 case FWOHCITCODE_PHY:
2614 slen = 12;
2615 break;
2616 case FWTCODE_RREQB:
2617 case FWTCODE_WREQB:
2618 case FWTCODE_LREQ:
2619 case FWTCODE_RRESB:
2620 case FWTCODE_LRES:
2621 slen = 16;
2622 break;
2623 default:
2624 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2625 return(0);
2626 }
| 2604 switch (fp0->mode.common.tcode) {
2605 case FWTCODE_RREQQ:
2606 case FWTCODE_WRES:
2607 case FWTCODE_WREQQ:
2608 case FWTCODE_RRESQ:
2609 case FWOHCITCODE_PHY:
2610 slen = 12;
2611 break;
2612 case FWTCODE_RREQB:
2613 case FWTCODE_WREQB:
2614 case FWTCODE_LREQ:
2615 case FWTCODE_RRESB:
2616 case FWTCODE_LRES:
2617 slen = 16;
2618 break;
2619 default:
2620 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2621 return(0);
2622 }
|
2627 if (slen > len) {
| 2623 hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2624 if (hlen > len) {
|
2628 if (firewire_debug)
2629 printf("splitted header\n");
| 2625 if (firewire_debug)
2626 printf("splitted header\n");
|
2630 return(-slen);
| 2627 return(-hlen);
|
2631 }
2632#if BYTE_ORDER == BIG_ENDIAN
2633 for(i = 0; i < slen/4; i ++)
2634 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2635#endif
| 2628 }
2629#if BYTE_ORDER == BIG_ENDIAN
2630 for(i = 0; i < slen/4; i ++)
2631 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2632#endif
|
2636 return(slen);
| 2633 return(hlen);
|
2637}
2638
| 2634}
2635
|
2639#define PLEN(x) roundup2(x, sizeof(u_int32_t))
| |
2640static int
2641fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2642{
| 2636static int
2637fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2638{
|
| 2639 struct tcode_info *info;
|
2643 int r;
2644
| 2640 int r;
2641
|
2645 switch(fp->mode.common.tcode){
2646 case FWTCODE_RREQQ:
2647 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t);
2648 break;
2649 case FWTCODE_WRES:
2650 r = sizeof(fp->mode.wres) + sizeof(u_int32_t);
2651 break;
2652 case FWTCODE_WREQQ:
2653 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t);
2654 break;
2655 case FWTCODE_RREQB:
2656 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t);
2657 break;
2658 case FWTCODE_RRESQ:
2659 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t);
2660 break;
2661 case FWTCODE_WREQB:
2662 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len)
2663 + sizeof(u_int32_t);
2664 break;
2665 case FWTCODE_LREQ:
2666 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len)
2667 + sizeof(u_int32_t);
2668 break;
2669 case FWTCODE_RRESB:
2670 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len)
2671 + sizeof(u_int32_t);
2672 break;
2673 case FWTCODE_LRES:
2674 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len)
2675 + sizeof(u_int32_t);
2676 break;
2677 case FWOHCITCODE_PHY:
2678 r = 16;
2679 break;
2680 default:
| 2642 info = &tinfo[fp->mode.common.tcode];
2643 r = info->hdr_len + sizeof(u_int32_t);
2644 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2645 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t));
2646
2647 if (r == sizeof(u_int32_t))
2648 /* XXX */
|
2681 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2682 fp->mode.common.tcode);
| 2649 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2650 fp->mode.common.tcode);
|
2683 r = 0;
2684 }
| 2651
|
2685 if (r > dbch->xferq.psize) {
2686 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2687 /* panic ? */
2688 }
| 2652 if (r > dbch->xferq.psize) {
2653 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2654 /* panic ? */
2655 }
|
| 2656
|
2689 return r;
2690}
2691
2692static void
2693fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
2694{
| 2657 return r;
2658}
2659
2660static void
2661fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
2662{
|
2695 volatile struct fwohcidb *db = &db_tr->db[0];
| 2663 struct fwohcidb *db = &db_tr->db[0];
|
2696
2697 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2698 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2699 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2700 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2701 dbch->bottom = db_tr;
2702}
2703
2704static void
2705fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2706{
2707 struct fwohcidb_tr *db_tr;
2708 struct iovec vec[2];
2709 struct fw_pkt pktbuf;
2710 int nvec;
2711 struct fw_pkt *fp;
2712 u_int8_t *ld;
2713 u_int32_t stat, off, status;
2714 u_int spd;
2715 int len, plen, hlen, pcnt, offset;
2716 int s;
2717 caddr_t buf;
2718 int resCount;
2719
2720 if(&sc->arrq == dbch){
2721 off = OHCI_ARQOFF;
2722 }else if(&sc->arrs == dbch){
2723 off = OHCI_ARSOFF;
2724 }else{
2725 return;
2726 }
2727
2728 s = splfw();
2729 db_tr = dbch->top;
2730 pcnt = 0;
2731 /* XXX we cannot handle a packet which lies in more than two buf */
2732 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2733 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2734 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2735 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2736#if 0
2737 printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2738#endif
2739 while (status & OHCI_CNTL_DMA_ACTIVE) {
2740 len = dbch->xferq.psize - resCount;
2741 ld = (u_int8_t *)db_tr->buf;
2742 if (dbch->pdb_tr == NULL) {
2743 len -= dbch->buf_offset;
2744 ld += dbch->buf_offset;
2745 }
2746 if (len > 0)
2747 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2748 BUS_DMASYNC_POSTREAD);
2749 while (len > 0 ) {
2750 if (count >= 0 && count-- == 0)
2751 goto out;
2752 if(dbch->pdb_tr != NULL){
2753 /* we have a fragment in previous buffer */
2754 int rlen;
2755
2756 offset = dbch->buf_offset;
2757 if (offset < 0)
2758 offset = - offset;
2759 buf = dbch->pdb_tr->buf + offset;
2760 rlen = dbch->xferq.psize - offset;
2761 if (firewire_debug)
2762 printf("rlen=%d, offset=%d\n",
2763 rlen, dbch->buf_offset);
2764 if (dbch->buf_offset < 0) {
2765 /* splitted in header, pull up */
2766 char *p;
2767
2768 p = (char *)&pktbuf;
2769 bcopy(buf, p, rlen);
2770 p += rlen;
2771 /* this must be too long but harmless */
2772 rlen = sizeof(pktbuf) - rlen;
2773 if (rlen < 0)
2774 printf("why rlen < 0\n");
2775 bcopy(db_tr->buf, p, rlen);
2776 ld += rlen;
2777 len -= rlen;
2778 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2779 if (hlen < 0) {
2780 printf("hlen < 0 shouldn't happen");
2781 }
2782 offset = sizeof(pktbuf);
2783 vec[0].iov_base = (char *)&pktbuf;
2784 vec[0].iov_len = offset;
2785 } else {
2786 /* splitted in payload */
2787 offset = rlen;
2788 vec[0].iov_base = buf;
2789 vec[0].iov_len = rlen;
2790 }
2791 fp=(struct fw_pkt *)vec[0].iov_base;
2792 nvec = 1;
2793 } else {
2794 /* no fragment in previous buffer */
2795 fp=(struct fw_pkt *)ld;
2796 hlen = fwohci_arcv_swap(fp, len);
2797 if (hlen == 0)
2798 /* XXX need reset */
2799 goto out;
2800 if (hlen < 0) {
2801 dbch->pdb_tr = db_tr;
2802 dbch->buf_offset = - dbch->buf_offset;
2803 /* sanity check */
2804 if (resCount != 0)
2805 printf("resCount != 0 !?\n");
2806 goto out;
2807 }
2808 offset = 0;
2809 nvec = 0;
2810 }
2811 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2812 if (plen < 0) {
2813 /* minimum header size + trailer
2814 = sizeof(fw_pkt) so this shouldn't happens */
| 2664
2665 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2666 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2667 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2668 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2669 dbch->bottom = db_tr;
2670}
2671
2672static void
2673fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2674{
2675 struct fwohcidb_tr *db_tr;
2676 struct iovec vec[2];
2677 struct fw_pkt pktbuf;
2678 int nvec;
2679 struct fw_pkt *fp;
2680 u_int8_t *ld;
2681 u_int32_t stat, off, status;
2682 u_int spd;
2683 int len, plen, hlen, pcnt, offset;
2684 int s;
2685 caddr_t buf;
2686 int resCount;
2687
2688 if(&sc->arrq == dbch){
2689 off = OHCI_ARQOFF;
2690 }else if(&sc->arrs == dbch){
2691 off = OHCI_ARSOFF;
2692 }else{
2693 return;
2694 }
2695
2696 s = splfw();
2697 db_tr = dbch->top;
2698 pcnt = 0;
2699 /* XXX we cannot handle a packet which lies in more than two buf */
2700 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2701 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2702 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2703 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2704#if 0
2705 printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2706#endif
2707 while (status & OHCI_CNTL_DMA_ACTIVE) {
2708 len = dbch->xferq.psize - resCount;
2709 ld = (u_int8_t *)db_tr->buf;
2710 if (dbch->pdb_tr == NULL) {
2711 len -= dbch->buf_offset;
2712 ld += dbch->buf_offset;
2713 }
2714 if (len > 0)
2715 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2716 BUS_DMASYNC_POSTREAD);
2717 while (len > 0 ) {
2718 if (count >= 0 && count-- == 0)
2719 goto out;
2720 if(dbch->pdb_tr != NULL){
2721 /* we have a fragment in previous buffer */
2722 int rlen;
2723
2724 offset = dbch->buf_offset;
2725 if (offset < 0)
2726 offset = - offset;
2727 buf = dbch->pdb_tr->buf + offset;
2728 rlen = dbch->xferq.psize - offset;
2729 if (firewire_debug)
2730 printf("rlen=%d, offset=%d\n",
2731 rlen, dbch->buf_offset);
2732 if (dbch->buf_offset < 0) {
2733 /* splitted in header, pull up */
2734 char *p;
2735
2736 p = (char *)&pktbuf;
2737 bcopy(buf, p, rlen);
2738 p += rlen;
2739 /* this must be too long but harmless */
2740 rlen = sizeof(pktbuf) - rlen;
2741 if (rlen < 0)
2742 printf("why rlen < 0\n");
2743 bcopy(db_tr->buf, p, rlen);
2744 ld += rlen;
2745 len -= rlen;
2746 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2747 if (hlen < 0) {
2748 printf("hlen < 0 shouldn't happen");
2749 }
2750 offset = sizeof(pktbuf);
2751 vec[0].iov_base = (char *)&pktbuf;
2752 vec[0].iov_len = offset;
2753 } else {
2754 /* splitted in payload */
2755 offset = rlen;
2756 vec[0].iov_base = buf;
2757 vec[0].iov_len = rlen;
2758 }
2759 fp=(struct fw_pkt *)vec[0].iov_base;
2760 nvec = 1;
2761 } else {
2762 /* no fragment in previous buffer */
2763 fp=(struct fw_pkt *)ld;
2764 hlen = fwohci_arcv_swap(fp, len);
2765 if (hlen == 0)
2766 /* XXX need reset */
2767 goto out;
2768 if (hlen < 0) {
2769 dbch->pdb_tr = db_tr;
2770 dbch->buf_offset = - dbch->buf_offset;
2771 /* sanity check */
2772 if (resCount != 0)
2773 printf("resCount != 0 !?\n");
2774 goto out;
2775 }
2776 offset = 0;
2777 nvec = 0;
2778 }
2779 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2780 if (plen < 0) {
2781 /* minimum header size + trailer
2782 = sizeof(fw_pkt) so this shouldn't happens */
|
2815 printf("plen is negative! offset=%d\n", offset);
| 2783 printf("plen(%d) is negative! offset=%d\n",
2784 plen, offset);
|
2816 goto out;
2817 }
2818 if (plen > 0) {
2819 len -= plen;
2820 if (len < 0) {
2821 dbch->pdb_tr = db_tr;
2822 if (firewire_debug)
2823 printf("splitted payload\n");
2824 /* sanity check */
2825 if (resCount != 0)
2826 printf("resCount != 0 !?\n");
2827 goto out;
2828 }
2829 vec[nvec].iov_base = ld;
2830 vec[nvec].iov_len = plen;
2831 nvec ++;
2832 ld += plen;
2833 }
2834 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf;
2835 if (nvec == 0)
2836 printf("nvec == 0\n");
2837
2838/* DMA result-code will be written at the tail of packet */
2839#if BYTE_ORDER == BIG_ENDIAN
2840 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2841#else
2842 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2843#endif
2844#if 0
| 2785 goto out;
2786 }
2787 if (plen > 0) {
2788 len -= plen;
2789 if (len < 0) {
2790 dbch->pdb_tr = db_tr;
2791 if (firewire_debug)
2792 printf("splitted payload\n");
2793 /* sanity check */
2794 if (resCount != 0)
2795 printf("resCount != 0 !?\n");
2796 goto out;
2797 }
2798 vec[nvec].iov_base = ld;
2799 vec[nvec].iov_len = plen;
2800 nvec ++;
2801 ld += plen;
2802 }
2803 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf;
2804 if (nvec == 0)
2805 printf("nvec == 0\n");
2806
2807/* DMA result-code will be written at the tail of packet */
2808#if BYTE_ORDER == BIG_ENDIAN
2809 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2810#else
2811 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2812#endif
2813#if 0
|
2845 printf("plen: %d, stat %x\n", plen ,stat);
| 2814 printf("plen: %d, stat %x\n",
2815 plen ,stat);
|
2846#endif
2847 spd = (stat >> 5) & 0x3;
2848 stat &= 0x1f;
2849 switch(stat){
2850 case FWOHCIEV_ACKPEND:
2851#if 0
2852 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2853#endif
2854 /* fall through */
2855 case FWOHCIEV_ACKCOMPL:
| 2816#endif
2817 spd = (stat >> 5) & 0x3;
2818 stat &= 0x1f;
2819 switch(stat){
2820 case FWOHCIEV_ACKPEND:
2821#if 0
2822 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2823#endif
2824 /* fall through */
2825 case FWOHCIEV_ACKCOMPL:
|
| 2826 {
2827 struct fw_rcv_buf rb;
2828
|
2856 if ((vec[nvec-1].iov_len -=
2857 sizeof(struct fwohci_trailer)) == 0)
2858 nvec--;
| 2829 if ((vec[nvec-1].iov_len -=
2830 sizeof(struct fwohci_trailer)) == 0)
2831 nvec--;
|
2859 fw_rcv(&sc->fc, vec, nvec, 0, spd);
2860 break;
| 2832 rb.fc = &sc->fc;
2833 rb.vec = vec;
2834 rb.nvec = nvec;
2835 rb.spd = spd;
2836 fw_rcv(&rb);
2837 break;
2838 }
|
2861 case FWOHCIEV_BUSRST:
2862 if (sc->fc.status != FWBUSRESET)
2863 printf("got BUSRST packet!?\n");
2864 break;
2865 default:
2866 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2867#if 0 /* XXX */
2868 goto out;
2869#endif
2870 break;
2871 }
2872 pcnt ++;
2873 if (dbch->pdb_tr != NULL) {
2874 fwohci_arcv_free_buf(dbch, dbch->pdb_tr);
2875 dbch->pdb_tr = NULL;
2876 }
2877
2878 }
2879out:
2880 if (resCount == 0) {
2881 /* done on this buffer */
2882 if (dbch->pdb_tr == NULL) {
2883 fwohci_arcv_free_buf(dbch, db_tr);
2884 dbch->buf_offset = 0;
2885 } else
2886 if (dbch->pdb_tr != db_tr)
2887 printf("pdb_tr != db_tr\n");
2888 db_tr = STAILQ_NEXT(db_tr, link);
2889 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2890 >> OHCI_STATUS_SHIFT;
2891 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2892 & OHCI_COUNT_MASK;
2893 /* XXX check buffer overrun */
2894 dbch->top = db_tr;
2895 } else {
2896 dbch->buf_offset = dbch->xferq.psize - resCount;
2897 break;
2898 }
2899 /* XXX make sure DMA is not dead */
2900 }
2901#if 0
2902 if (pcnt < 1)
2903 printf("fwohci_arcv: no packets\n");
2904#endif
2905 splx(s);
2906}
| 2839 case FWOHCIEV_BUSRST:
2840 if (sc->fc.status != FWBUSRESET)
2841 printf("got BUSRST packet!?\n");
2842 break;
2843 default:
2844 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2845#if 0 /* XXX */
2846 goto out;
2847#endif
2848 break;
2849 }
2850 pcnt ++;
2851 if (dbch->pdb_tr != NULL) {
2852 fwohci_arcv_free_buf(dbch, dbch->pdb_tr);
2853 dbch->pdb_tr = NULL;
2854 }
2855
2856 }
2857out:
2858 if (resCount == 0) {
2859 /* done on this buffer */
2860 if (dbch->pdb_tr == NULL) {
2861 fwohci_arcv_free_buf(dbch, db_tr);
2862 dbch->buf_offset = 0;
2863 } else
2864 if (dbch->pdb_tr != db_tr)
2865 printf("pdb_tr != db_tr\n");
2866 db_tr = STAILQ_NEXT(db_tr, link);
2867 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2868 >> OHCI_STATUS_SHIFT;
2869 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2870 & OHCI_COUNT_MASK;
2871 /* XXX check buffer overrun */
2872 dbch->top = db_tr;
2873 } else {
2874 dbch->buf_offset = dbch->xferq.psize - resCount;
2875 break;
2876 }
2877 /* XXX make sure DMA is not dead */
2878 }
2879#if 0
2880 if (pcnt < 1)
2881 printf("fwohci_arcv: no packets\n");
2882#endif
2883 splx(s);
2884}
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