34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4
42#define IRX_CH 0x24
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/types.h>
47#include <sys/mbuf.h>
48#include <sys/mman.h>
49#include <sys/socket.h>
50#include <sys/socketvar.h>
51#include <sys/signalvar.h>
52#include <sys/malloc.h>
53#include <sys/uio.h>
54#include <sys/sockio.h>
55#include <sys/bus.h>
56#include <sys/kernel.h>
57#include <sys/conf.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
61#include <sys/rman.h>
62
63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */
64#include <machine/clock.h>
65#include <pci/pcivar.h>
66#include <pci/pcireg.h>
67#include <vm/vm.h>
68#include <vm/vm_extern.h>
69#include <vm/pmap.h> /* for vtophys proto */
70
71#include <dev/firewire/firewire.h>
72#include <dev/firewire/firewirereg.h>
73#include <dev/firewire/fwohcireg.h>
74#include <dev/firewire/fwohcivar.h>
75#include <dev/firewire/firewire_phy.h>
76
77#undef OHCI_DEBUG
78
79static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
80 "STOR","LOAD","NOP ","STOP",};
81static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
82 "UNDEF","REG","SYS","DEV"};
83char fwohcicode[32][0x20]={
84 "No stat","Undef","long","miss Ack err",
85 "underrun","overrun","desc err", "data read err",
86 "data write err","bus reset","timeout","tcode err",
87 "Undef","Undef","unknown event","flushed",
88 "Undef","ack complete","ack pend","Undef",
89 "ack busy_X","ack busy_A","ack busy_B","Undef",
90 "Undef","Undef","Undef","ack tardy",
91 "Undef","ack data_err","ack type_err",""};
92#define MAX_SPEED 2
93extern char linkspeed[MAX_SPEED+1][0x10];
94static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
95u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
96
97static struct tcode_info tinfo[] = {
98/* hdr_len block flag*/
99/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
100/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
101/* 2 WRES */ {12, FWTI_RES},
102/* 3 XXX */ { 0, 0},
103/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
104/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
105/* 6 RRESQ */ {16, FWTI_RES},
106/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
107/* 8 CYCS */ { 0, 0},
108/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
109/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
110/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
111/* c XXX */ { 0, 0},
112/* d XXX */ { 0, 0},
113/* e PHY */ {12, FWTI_REQ},
114/* f XXX */ { 0, 0}
115};
116
117#define OHCI_WRITE_SIGMASK 0xffff0000
118#define OHCI_READ_SIGMASK 0xffff0000
119
120#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
121#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
122
123static void fwohci_ibr __P((struct firewire_comm *));
124static void fwohci_db_init __P((struct fwohci_dbch *));
125static void fwohci_db_free __P((struct fwohci_dbch *));
126static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
127static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
128static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *));
129static void fwohci_start_atq __P((struct firewire_comm *));
130static void fwohci_start_ats __P((struct firewire_comm *));
131static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *));
132static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *));
133static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *));
134static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *));
135static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t));
136static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t));
137static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
138static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
139static int fwohci_irx_enable __P((struct firewire_comm *, int));
140static int fwohci_irxpp_enable __P((struct firewire_comm *, int));
141static int fwohci_irxbuf_enable __P((struct firewire_comm *, int));
142static int fwohci_irx_disable __P((struct firewire_comm *, int));
143static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *));
144static int fwohci_itxbuf_enable __P((struct firewire_comm *, int));
145static int fwohci_itx_disable __P((struct firewire_comm *, int));
146static void fwohci_timeout __P((void *));
147static void fwohci_poll __P((struct firewire_comm *, int, int));
148static void fwohci_set_intr __P((struct firewire_comm *, int));
149static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *));
150static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *));
151static void dump_db __P((struct fwohci_softc *, u_int32_t));
152static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t));
153static void dump_dma __P((struct fwohci_softc *, u_int32_t));
154static u_int32_t fwohci_cyctimer __P((struct firewire_comm *));
155static void fwohci_rbuf_update __P((struct fwohci_softc *, int));
156static void fwohci_tbuf_update __P((struct fwohci_softc *, int));
157void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *));
158
159/*
160 * memory allocated for DMA programs
161 */
162#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
163
164/* #define NDB 1024 */
165#define NDB FWMAXQUEUE
166#define NDVDB (DVBUF * NDB)
167
168#define OHCI_VERSION 0x00
169#define OHCI_CROMHDR 0x18
170#define OHCI_BUS_OPT 0x20
171#define OHCI_BUSIRMC (1 << 31)
172#define OHCI_BUSCMC (1 << 30)
173#define OHCI_BUSISC (1 << 29)
174#define OHCI_BUSBMC (1 << 28)
175#define OHCI_BUSPMC (1 << 27)
176#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
177 OHCI_BUSBMC | OHCI_BUSPMC
178
179#define OHCI_EUID_HI 0x24
180#define OHCI_EUID_LO 0x28
181
182#define OHCI_CROMPTR 0x34
183#define OHCI_HCCCTL 0x50
184#define OHCI_HCCCTLCLR 0x54
185#define OHCI_AREQHI 0x100
186#define OHCI_AREQHICLR 0x104
187#define OHCI_AREQLO 0x108
188#define OHCI_AREQLOCLR 0x10c
189#define OHCI_PREQHI 0x110
190#define OHCI_PREQHICLR 0x114
191#define OHCI_PREQLO 0x118
192#define OHCI_PREQLOCLR 0x11c
193#define OHCI_PREQUPPER 0x120
194
195#define OHCI_SID_BUF 0x64
196#define OHCI_SID_CNT 0x68
197#define OHCI_SID_CNT_MASK 0xffc
198
199#define OHCI_IT_STAT 0x90
200#define OHCI_IT_STATCLR 0x94
201#define OHCI_IT_MASK 0x98
202#define OHCI_IT_MASKCLR 0x9c
203
204#define OHCI_IR_STAT 0xa0
205#define OHCI_IR_STATCLR 0xa4
206#define OHCI_IR_MASK 0xa8
207#define OHCI_IR_MASKCLR 0xac
208
209#define OHCI_LNKCTL 0xe0
210#define OHCI_LNKCTLCLR 0xe4
211
212#define OHCI_PHYACCESS 0xec
213#define OHCI_CYCLETIMER 0xf0
214
215#define OHCI_DMACTL(off) (off)
216#define OHCI_DMACTLCLR(off) (off + 4)
217#define OHCI_DMACMD(off) (off + 0xc)
218#define OHCI_DMAMATCH(off) (off + 0x10)
219
220#define OHCI_ATQOFF 0x180
221#define OHCI_ATQCTL OHCI_ATQOFF
222#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
223#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
224#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
225
226#define OHCI_ATSOFF 0x1a0
227#define OHCI_ATSCTL OHCI_ATSOFF
228#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
229#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
230#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
231
232#define OHCI_ARQOFF 0x1c0
233#define OHCI_ARQCTL OHCI_ARQOFF
234#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
235#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
236#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
237
238#define OHCI_ARSOFF 0x1e0
239#define OHCI_ARSCTL OHCI_ARSOFF
240#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
241#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
242#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
243
244#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
245#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
246#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
247#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
248
249#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
250#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
251#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
252#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
253#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
254
255d_ioctl_t fwohci_ioctl;
256
257/*
258 * Communication with PHY device
259 */
260static u_int32_t
261fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
262{
263 u_int32_t fun;
264
265 addr &= 0xf;
266 data &= 0xff;
267
268 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
269 OWRITE(sc, OHCI_PHYACCESS, fun);
270 DELAY(100);
271
272 return(fwphy_rddata( sc, addr));
273}
274
275static u_int32_t
276fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
277{
278 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
279 int i;
280 u_int32_t bm;
281
282#define OHCI_CSR_DATA 0x0c
283#define OHCI_CSR_COMP 0x10
284#define OHCI_CSR_CONT 0x14
285#define OHCI_BUS_MANAGER_ID 0
286
287 OWRITE(sc, OHCI_CSR_DATA, node);
288 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
289 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
290 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
291 DELAY(100);
292 bm = OREAD(sc, OHCI_CSR_DATA);
293 if((bm & 0x3f) == 0x3f)
294 bm = node;
295 if (bootverbose)
296 device_printf(sc->fc.dev,
297 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
298
299 return(bm);
300}
301
302static u_int32_t
303fwphy_rddata(struct fwohci_softc *sc, u_int addr)
304{
305 u_int32_t fun, stat;
306 u_int i, retry = 0;
307
308 addr &= 0xf;
309#define MAX_RETRY 100
310again:
311 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
312 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
313 OWRITE(sc, OHCI_PHYACCESS, fun);
314 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
315 fun = OREAD(sc, OHCI_PHYACCESS);
316 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
317 break;
318 DELAY(1000);
319 }
320 if(i >= MAX_RETRY) {
321 device_printf(sc->fc.dev, "cannot read phy\n");
322#if 0
323 return 0; /* XXX */
324#else
325 if (++retry < MAX_RETRY) {
326 DELAY(1000);
327 goto again;
328 }
329#endif
330 }
331 /* Make sure that SCLK is started */
332 stat = OREAD(sc, FWOHCI_INTSTAT);
333 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
335 if (++retry < MAX_RETRY) {
336 DELAY(1000);
337 goto again;
338 }
339 }
340 if (bootverbose || retry >= MAX_RETRY)
341 device_printf(sc->fc.dev,
342 "fwphy_rddata: loop=%d, retry=%d\n", i, retry);
343#undef MAX_RETRY
344 return((fun >> PHYDEV_RDDATA )& 0xff);
345}
346/* Device specific ioctl. */
347int
348fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
349{
350 struct firewire_softc *sc;
351 struct fwohci_softc *fc;
352 int unit = DEV2UNIT(dev);
353 int err = 0;
354 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
355 u_int32_t *dmach = (u_int32_t *) data;
356
357 sc = devclass_get_softc(firewire_devclass, unit);
358 if(sc == NULL){
359 return(EINVAL);
360 }
361 fc = (struct fwohci_softc *)sc->fc;
362
363 if (!data)
364 return(EINVAL);
365
366 switch (cmd) {
367 case FWOHCI_WRREG:
368#define OHCI_MAX_REG 0x800
369 if(reg->addr <= OHCI_MAX_REG){
370 OWRITE(fc, reg->addr, reg->data);
371 reg->data = OREAD(fc, reg->addr);
372 }else{
373 err = EINVAL;
374 }
375 break;
376 case FWOHCI_RDREG:
377 if(reg->addr <= OHCI_MAX_REG){
378 reg->data = OREAD(fc, reg->addr);
379 }else{
380 err = EINVAL;
381 }
382 break;
383/* Read DMA descriptors for debug */
384 case DUMPDMA:
385 if(*dmach <= OHCI_MAX_DMA_CH ){
386 dump_dma(fc, *dmach);
387 dump_db(fc, *dmach);
388 }else{
389 err = EINVAL;
390 }
391 break;
392 default:
393 break;
394 }
395 return err;
396}
397
398static int
399fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
400{
401 u_int32_t reg, reg2;
402 int e1394a = 1;
403/*
404 * probe PHY parameters
405 * 0. to prove PHY version, whether compliance of 1394a.
406 * 1. to probe maximum speed supported by the PHY and
407 * number of port supported by core-logic.
408 * It is not actually available port on your PC .
409 */
410 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
411#if 0
412 /* XXX wait for SCLK. */
413 DELAY(100000);
414#endif
415 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
416
417 if((reg >> 5) != 7 ){
418 sc->fc.mode &= ~FWPHYASYST;
419 sc->fc.nport = reg & FW_PHY_NP;
420 sc->fc.speed = reg & FW_PHY_SPD >> 6;
421 if (sc->fc.speed > MAX_SPEED) {
422 device_printf(dev, "invalid speed %d (fixed to %d).\n",
423 sc->fc.speed, MAX_SPEED);
424 sc->fc.speed = MAX_SPEED;
425 }
426 device_printf(dev,
427 "Phy 1394 only %s, %d ports.\n",
428 linkspeed[sc->fc.speed], sc->fc.nport);
429 }else{
430 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
431 sc->fc.mode |= FWPHYASYST;
432 sc->fc.nport = reg & FW_PHY_NP;
433 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
434 if (sc->fc.speed > MAX_SPEED) {
435 device_printf(dev, "invalid speed %d (fixed to %d).\n",
436 sc->fc.speed, MAX_SPEED);
437 sc->fc.speed = MAX_SPEED;
438 }
439 device_printf(dev,
440 "Phy 1394a available %s, %d ports.\n",
441 linkspeed[sc->fc.speed], sc->fc.nport);
442
443 /* check programPhyEnable */
444 reg2 = fwphy_rddata(sc, 5);
445#if 0
446 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
447#else /* XXX force to enable 1394a */
448 if (e1394a) {
449#endif
450 if (bootverbose)
451 device_printf(dev,
452 "Enable 1394a Enhancements\n");
453 /* enable EAA EMC */
454 reg2 |= 0x03;
455 /* set aPhyEnhanceEnable */
456 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
457 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
458 } else {
459 /* for safe */
460 reg2 &= ~0x83;
461 }
462 reg2 = fwphy_wrdata(sc, 5, reg2);
463 }
464
465 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
466 if((reg >> 5) == 7 ){
467 reg = fwphy_rddata(sc, 4);
468 reg |= 1 << 6;
469 fwphy_wrdata(sc, 4, reg);
470 reg = fwphy_rddata(sc, 4);
471 }
472 return 0;
473}
474
475
476void
477fwohci_reset(struct fwohci_softc *sc, device_t dev)
478{
479 int i, max_rec, speed;
480 u_int32_t reg, reg2;
481 struct fwohcidb_tr *db_tr;
482
483 /* Disable interrupt */
484 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
485
486 /* Now stopping all DMA channel */
487 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
488 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
489 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
490 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
491
492 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
493 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
494 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
495 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
496 }
497
498 /* FLUSH FIFO and reset Transmitter/Reciever */
499 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
500 if (bootverbose)
501 device_printf(dev, "resetting OHCI...");
502 i = 0;
503 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
504 if (i++ > 100) break;
505 DELAY(1000);
506 }
507 if (bootverbose)
508 printf("done (loop=%d)\n", i);
509
510 /* Probe phy */
511 fwohci_probe_phy(sc, dev);
512
513 /* Probe link */
514 reg = OREAD(sc, OHCI_BUS_OPT);
515 reg2 = reg | OHCI_BUSFNC;
516 max_rec = (reg & 0x0000f000) >> 12;
517 speed = (reg & 0x00000007);
518 device_printf(dev, "Link %s, max_rec %d bytes.\n",
519 linkspeed[speed], MAXREC(max_rec));
520 /* XXX fix max_rec */
521 sc->fc.maxrec = sc->fc.speed + 8;
522 if (max_rec != sc->fc.maxrec) {
523 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
524 device_printf(dev, "max_rec %d -> %d\n",
525 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
526 }
527 if (bootverbose)
528 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
529 OWRITE(sc, OHCI_BUS_OPT, reg2);
530
531 /* Initialize registers */
532 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
533 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
534 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
535 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
536 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
537 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
538 fw_busreset(&sc->fc);
539
540 /* Enable link */
541 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
542
543 /* Force to start async RX DMA */
544 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
545 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
546 fwohci_rx_enable(sc, &sc->arrq);
547 fwohci_rx_enable(sc, &sc->arrs);
548
549 /* Initialize async TX */
550 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
551 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
552 /* AT Retries */
553 OWRITE(sc, FWOHCI_RETRY,
554 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
555 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
556 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
557 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
558 db_tr->xfer = NULL;
559 }
560 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
561 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
562 db_tr->xfer = NULL;
563 }
564
565
566 /* Enable interrupt */
567 OWRITE(sc, FWOHCI_INTMASK,
568 OHCI_INT_ERR | OHCI_INT_PHY_SID
569 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
570 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
571 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
572 fwohci_set_intr(&sc->fc, 1);
573
574}
575
576int
577fwohci_init(struct fwohci_softc *sc, device_t dev)
578{
579 int i;
580 u_int32_t reg;
581
582 reg = OREAD(sc, OHCI_VERSION);
583 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
584 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1);
585
586/* XXX: Available Isochrounous DMA channel probe */
587 for( i = 0 ; i < 0x20 ; i ++ ){
588 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN);
589 reg = OREAD(sc, OHCI_IRCTL(i));
590 if(!(reg & OHCI_CNTL_DMA_RUN)) break;
591 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN);
592 reg = OREAD(sc, OHCI_ITCTL(i));
593 if(!(reg & OHCI_CNTL_DMA_RUN)) break;
594 }
595 sc->fc.nisodma = i;
596 device_printf(dev, "No. of Isochronous channel is %d.\n", i);
597
598 sc->fc.arq = &sc->arrq.xferq;
599 sc->fc.ars = &sc->arrs.xferq;
600 sc->fc.atq = &sc->atrq.xferq;
601 sc->fc.ats = &sc->atrs.xferq;
602
603 sc->arrq.xferq.start = NULL;
604 sc->arrs.xferq.start = NULL;
605 sc->atrq.xferq.start = fwohci_start_atq;
606 sc->atrs.xferq.start = fwohci_start_ats;
607
608 sc->arrq.xferq.drain = NULL;
609 sc->arrs.xferq.drain = NULL;
610 sc->atrq.xferq.drain = fwohci_drain_atq;
611 sc->atrs.xferq.drain = fwohci_drain_ats;
612
613 sc->arrq.ndesc = 1;
614 sc->arrs.ndesc = 1;
615 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */
616 sc->atrs.ndesc = 6 / 2;
617
618 sc->arrq.ndb = NDB;
619 sc->arrs.ndb = NDB / 2;
620 sc->atrq.ndb = NDB;
621 sc->atrs.ndb = NDB / 2;
622
623 sc->arrq.dummy = NULL;
624 sc->arrs.dummy = NULL;
625 sc->atrq.dummy = NULL;
626 sc->atrs.dummy = NULL;
627 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
628 sc->fc.it[i] = &sc->it[i].xferq;
629 sc->fc.ir[i] = &sc->ir[i].xferq;
630 sc->it[i].ndb = 0;
631 sc->ir[i].ndb = 0;
632 }
633
634 sc->fc.tcode = tinfo;
635
636 sc->cromptr = (u_int32_t *)
637 contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0);
638
639 if(sc->cromptr == NULL){
640 device_printf(dev, "cromptr alloc failed.");
641 return ENOMEM;
642 }
643 sc->fc.dev = dev;
644 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]);
645
646 sc->fc.config_rom[1] = 0x31333934;
647 sc->fc.config_rom[2] = 0xf000a002;
648 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
649 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
650 sc->fc.config_rom[5] = 0;
651 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
652
653 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
654
655
656/* SID recieve buffer must allign 2^11 */
657#define OHCI_SIDSIZE (1 << 11)
658 sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE,
659 0x10000, 0xffffffff, OHCI_SIDSIZE);
660 if (sc->fc.sid_buf == NULL) {
661 device_printf(dev, "sid_buf alloc failed.\n");
662 return ENOMEM;
663 }
664
665
666 fwohci_db_init(&sc->arrq);
667 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
668 return ENOMEM;
669
670 fwohci_db_init(&sc->arrs);
671 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
672 return ENOMEM;
673
674 fwohci_db_init(&sc->atrq);
675 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
676 return ENOMEM;
677
678 fwohci_db_init(&sc->atrs);
679 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
680 return ENOMEM;
681
682 reg = OREAD(sc, FWOHCIGUID_H);
683 for( i = 0 ; i < 4 ; i ++){
684 sc->fc.eui[3 - i] = reg & 0xff;
685 reg = reg >> 8;
686 }
687 reg = OREAD(sc, FWOHCIGUID_L);
688 for( i = 0 ; i < 4 ; i ++){
689 sc->fc.eui[7 - i] = reg & 0xff;
690 reg = reg >> 8;
691 }
692 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
693 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3],
694 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]);
695 sc->fc.ioctl = fwohci_ioctl;
696 sc->fc.cyctimer = fwohci_cyctimer;
697 sc->fc.set_bmr = fwohci_set_bus_manager;
698 sc->fc.ibr = fwohci_ibr;
699 sc->fc.irx_enable = fwohci_irx_enable;
700 sc->fc.irx_disable = fwohci_irx_disable;
701
702 sc->fc.itx_enable = fwohci_itxbuf_enable;
703 sc->fc.itx_disable = fwohci_itx_disable;
704 sc->fc.irx_post = fwohci_irx_post;
705 sc->fc.itx_post = NULL;
706 sc->fc.timeout = fwohci_timeout;
707 sc->fc.poll = fwohci_poll;
708 sc->fc.set_intr = fwohci_set_intr;
709
710 fw_init(&sc->fc);
711 fwohci_reset(sc, dev);
712
713 return 0;
714}
715
716void
717fwohci_timeout(void *arg)
718{
719 struct fwohci_softc *sc;
720
721 sc = (struct fwohci_softc *)arg;
722 sc->fc.timeouthandle = timeout(fwohci_timeout,
723 (void *)sc, FW_XFERTIMEOUT * hz * 10);
724}
725
726u_int32_t
727fwohci_cyctimer(struct firewire_comm *fc)
728{
729 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
730 return(OREAD(sc, OHCI_CYCLETIMER));
731}
732
733int
734fwohci_detach(struct fwohci_softc *sc, device_t dev)
735{
736 int i;
737
738 if (sc->fc.sid_buf != NULL)
739 contigfree((void *)(uintptr_t)sc->fc.sid_buf,
740 OHCI_SIDSIZE, M_DEVBUF);
741 if (sc->cromptr != NULL)
742 contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF);
743
744 fwohci_db_free(&sc->arrq);
745 fwohci_db_free(&sc->arrs);
746
747 fwohci_db_free(&sc->atrq);
748 fwohci_db_free(&sc->atrs);
749
750 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
751 fwohci_db_free(&sc->it[i]);
752 fwohci_db_free(&sc->ir[i]);
753 }
754
755 return 0;
756}
757
758#define LAST_DB(dbtr, db) do { \
759 struct fwohcidb_tr *_dbtr = (dbtr); \
760 int _cnt = _dbtr->dbcnt; \
761 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
762} while (0)
763
764static void
765fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
766{
767 int i, s;
768 int tcode, hdr_len, hdr_off, len;
769 int fsegment = -1;
770 u_int32_t off;
771 struct fw_xfer *xfer;
772 struct fw_pkt *fp;
773 volatile struct fwohci_txpkthdr *ohcifp;
774 struct fwohcidb_tr *db_tr;
775 volatile struct fwohcidb *db;
776 struct mbuf *m;
777 struct tcode_info *info;
778 static int maxdesc=0;
779
780 if(&sc->atrq == dbch){
781 off = OHCI_ATQOFF;
782 }else if(&sc->atrs == dbch){
783 off = OHCI_ATSOFF;
784 }else{
785 return;
786 }
787
788 if (dbch->flags & FWOHCI_DBCH_FULL)
789 return;
790
791 s = splfw();
792 db_tr = dbch->top;
793txloop:
794 xfer = STAILQ_FIRST(&dbch->xferq.q);
795 if(xfer == NULL){
796 goto kick;
797 }
798 if(dbch->xferq.queued == 0 ){
799 device_printf(sc->fc.dev, "TX queue empty\n");
800 }
801 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
802 db_tr->xfer = xfer;
803 xfer->state = FWXF_START;
804 dbch->xferq.packets++;
805
806 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off);
807 tcode = fp->mode.common.tcode;
808
809 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
810 info = &tinfo[tcode];
811 hdr_len = hdr_off = info->hdr_len;
812 /* fw_asyreq must pass valid send.len */
813 len = xfer->send.len;
814 for( i = 0 ; i < hdr_off ; i+= 4){
815 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]);
816 }
817 ohcifp->mode.common.spd = xfer->spd;
818 if (tcode == FWTCODE_STREAM ){
819 hdr_len = 8;
820 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
821 } else if (tcode == FWTCODE_PHY) {
822 hdr_len = 12;
823 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]);
824 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]);
825 ohcifp->mode.common.spd = 0;
826 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
827 } else {
828 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst);
829 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
830 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
831 }
832 db = &db_tr->db[0];
833 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len;
834 db->db.desc.status = 0;
835/* Specify bound timer of asy. responce */
836 if(&sc->atrs == dbch){
837 db->db.desc.count
838 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13);
839 }
840
841 db_tr->dbcnt = 2;
842 db = &db_tr->db[db_tr->dbcnt];
843 if(len > hdr_off){
844 if (xfer->mbuf == NULL) {
845 db->db.desc.addr
846 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off;
847 db->db.desc.cmd
848 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff);
849 db->db.desc.status = 0;
850
851 db_tr->dbcnt++;
852 } else {
853 /* XXX we assume mbuf chain is shorter than ndesc */
854 for (m = xfer->mbuf; m != NULL; m = m->m_next) {
855 if (m->m_len == 0)
856 /* unrecoverable error could ocurre. */
857 continue;
858 if (db_tr->dbcnt >= dbch->ndesc) {
859 device_printf(sc->fc.dev,
860 "dbch->ndesc is too small"
861 ", trancated.\n");
862 break;
863 }
864 db->db.desc.addr
865 = vtophys(mtod(m, caddr_t));
866 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len;
867 db->db.desc.status = 0;
868 db++;
869 db_tr->dbcnt++;
870 }
871 }
872 }
873 if (maxdesc < db_tr->dbcnt) {
874 maxdesc = db_tr->dbcnt;
875 if (bootverbose)
876 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
877 }
878 /* last db */
879 LAST_DB(db_tr, db);
880 db->db.desc.cmd |= OHCI_OUTPUT_LAST
881 | OHCI_INTERRUPT_ALWAYS
882 | OHCI_BRANCH_ALWAYS;
883 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db);
884
885 if(fsegment == -1 )
886 fsegment = db_tr->dbcnt;
887 if (dbch->pdb_tr != NULL) {
888 LAST_DB(dbch->pdb_tr, db);
889 db->db.desc.depend |= db_tr->dbcnt;
890 }
891 dbch->pdb_tr = db_tr;
892 db_tr = STAILQ_NEXT(db_tr, link);
893 if(db_tr != dbch->bottom){
894 goto txloop;
895 } else {
896 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
897 dbch->flags |= FWOHCI_DBCH_FULL;
898 }
899kick:
900 if (firewire_debug) printf("kick\n");
901 /* kick asy q */
902
903 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
904 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
905 } else {
906 if (bootverbose)
907 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
908 OREAD(sc, OHCI_DMACTL(off)));
909 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment);
910 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
911 dbch->xferq.flag |= FWXFERQ_RUNNING;
912 }
913
914 dbch->top = db_tr;
915 splx(s);
916 return;
917}
918
919static void
920fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer)
921{
922 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
923 fwohci_drain(&sc->fc, xfer, &(sc->atrq));
924 return;
925}
926
927static void
928fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer)
929{
930 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
931 fwohci_drain(&sc->fc, xfer, &(sc->atrs));
932 return;
933}
934
935static void
936fwohci_start_atq(struct firewire_comm *fc)
937{
938 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
939 fwohci_start( sc, &(sc->atrq));
940 return;
941}
942
943static void
944fwohci_start_ats(struct firewire_comm *fc)
945{
946 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
947 fwohci_start( sc, &(sc->atrs));
948 return;
949}
950
951void
952fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
953{
954 int s, err = 0;
955 struct fwohcidb_tr *tr;
956 volatile struct fwohcidb *db;
957 struct fw_xfer *xfer;
958 u_int32_t off;
959 u_int stat;
960 int packets;
961 struct firewire_comm *fc = (struct firewire_comm *)sc;
962 if(&sc->atrq == dbch){
963 off = OHCI_ATQOFF;
964 }else if(&sc->atrs == dbch){
965 off = OHCI_ATSOFF;
966 }else{
967 return;
968 }
969 s = splfw();
970 tr = dbch->bottom;
971 packets = 0;
972 while(dbch->xferq.queued > 0){
973 LAST_DB(tr, db);
974 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){
975 if (fc->status != FWBUSRESET)
976 /* maybe out of order?? */
977 goto out;
978 }
979 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) {
980#ifdef OHCI_DEBUG
981 dump_dma(sc, ch);
982 dump_db(sc, ch);
983#endif
984/* Stop DMA */
985 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
986 device_printf(sc->fc.dev, "force reset AT FIFO\n");
987 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
988 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
989 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
990 }
991 stat = db->db.desc.status & FWOHCIEV_MASK;
992 switch(stat){
993 case FWOHCIEV_ACKCOMPL:
994 case FWOHCIEV_ACKPEND:
995 err = 0;
996 break;
997 case FWOHCIEV_ACKBSA:
998 case FWOHCIEV_ACKBSB:
999 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1000 case FWOHCIEV_ACKBSX:
1001 err = EBUSY;
1002 break;
1003 case FWOHCIEV_FLUSHED:
1004 case FWOHCIEV_ACKTARD:
1005 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1006 err = EAGAIN;
1007 break;
1008 case FWOHCIEV_MISSACK:
1009 case FWOHCIEV_UNDRRUN:
1010 case FWOHCIEV_OVRRUN:
1011 case FWOHCIEV_DESCERR:
1012 case FWOHCIEV_DTRDERR:
1013 case FWOHCIEV_TIMEOUT:
1014 case FWOHCIEV_TCODERR:
1015 case FWOHCIEV_UNKNOWN:
1016 case FWOHCIEV_ACKDERR:
1017 case FWOHCIEV_ACKTERR:
1018 default:
1019 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1020 stat, fwohcicode[stat]);
1021 err = EINVAL;
1022 break;
1023 }
1024 if(tr->xfer != NULL){
1025 xfer = tr->xfer;
1026 xfer->state = FWXF_SENT;
1027 if(err == EBUSY && fc->status != FWBUSRESET){
1028 xfer->state = FWXF_BUSY;
1029 switch(xfer->act_type){
1030 case FWACT_XFER:
1031 xfer->resp = err;
1032 if(xfer->retry_req != NULL){
1033 xfer->retry_req(xfer);
1034 }
1035 break;
1036 default:
1037 break;
1038 }
1039 } else if( stat != FWOHCIEV_ACKPEND){
1040 if (stat != FWOHCIEV_ACKCOMPL)
1041 xfer->state = FWXF_SENTERR;
1042 xfer->resp = err;
1043 switch(xfer->act_type){
1044 case FWACT_XFER:
1045 fw_xfer_done(xfer);
1046 break;
1047 default:
1048 break;
1049 }
1050 }
1051 dbch->xferq.queued --;
1052 }
1053 tr->xfer = NULL;
1054
1055 packets ++;
1056 tr = STAILQ_NEXT(tr, link);
1057 dbch->bottom = tr;
1058 }
1059out:
1060 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1061 printf("make free slot\n");
1062 dbch->flags &= ~FWOHCI_DBCH_FULL;
1063 fwohci_start(sc, dbch);
1064 }
1065 splx(s);
1066}
1067
1068static void
1069fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch)
1070{
1071 int i, s;
1072 struct fwohcidb_tr *tr;
1073
1074 if(xfer->state != FWXF_START) return;
1075
1076 s = splfw();
1077 tr = dbch->bottom;
1078 for( i = 0 ; i <= dbch->xferq.queued ; i ++){
1079 if(tr->xfer == xfer){
1080 s = splfw();
1081 tr->xfer = NULL;
1082 dbch->xferq.queued --;
1083#if 1
1084 /* XXX */
1085 if (tr == dbch->bottom)
1086 dbch->bottom = STAILQ_NEXT(tr, link);
1087#endif
1088 if (dbch->flags & FWOHCI_DBCH_FULL) {
1089 printf("fwohci_drain: make slot\n");
1090 dbch->flags &= ~FWOHCI_DBCH_FULL;
1091 fwohci_start((struct fwohci_softc *)fc, dbch);
1092 }
1093
1094 splx(s);
1095 break;
1096 }
1097 tr = STAILQ_NEXT(tr, link);
1098 }
1099 splx(s);
1100 return;
1101}
1102
1103static void
1104fwohci_db_free(struct fwohci_dbch *dbch)
1105{
1106 struct fwohcidb_tr *db_tr;
1107 int idb;
1108
1109 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1110 return;
1111
1112 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1113 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0;
1114 idb < dbch->ndb;
1115 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1116 if (db_tr->buf != NULL) {
1117 free(db_tr->buf, M_DEVBUF);
1118 db_tr->buf = NULL;
1119 }
1120 }
1121 }
1122 dbch->ndb = 0;
1123 db_tr = STAILQ_FIRST(&dbch->db_trq);
1124 contigfree((void *)(uintptr_t)(volatile void *)db_tr->db,
1125 sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF);
1126 free(db_tr, M_DEVBUF);
1127 STAILQ_INIT(&dbch->db_trq);
1128 dbch->flags &= ~FWOHCI_DBCH_INIT;
1129}
1130
1131static void
1132fwohci_db_init(struct fwohci_dbch *dbch)
1133{
1134 int idb;
1135 struct fwohcidb *db;
1136 struct fwohcidb_tr *db_tr;
1137
1138
1139 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1140 goto out;
1141
1142 /* allocate DB entries and attach one to each DMA channels */
1143 /* DB entry must start at 16 bytes bounary. */
1144 STAILQ_INIT(&dbch->db_trq);
1145 db_tr = (struct fwohcidb_tr *)
1146 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1147 M_DEVBUF, M_DONTWAIT | M_ZERO);
1148 if(db_tr == NULL){
1149 printf("fwohci_db_init: malloc failed\n");
1150 return;
1151 }
1152 db = (struct fwohcidb *)
1153 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb,
1154 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul);
1155 if(db == NULL){
1156 printf("fwohci_db_init: contigmalloc failed\n");
1157 free(db_tr, M_DEVBUF);
1158 return;
1159 }
1160 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb);
1161 /* Attach DB to DMA ch. */
1162 for(idb = 0 ; idb < dbch->ndb ; idb++){
1163 db_tr->dbcnt = 0;
1164 db_tr->db = &db[idb * dbch->ndesc];
1165 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1166 if (!(dbch->xferq.flag & FWXFERQ_PACKET) &&
1167 dbch->xferq.bnpacket != 0) {
1168 /* XXX what those for? */
1169 if (idb % dbch->xferq.bnpacket == 0)
1170 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1171 ].start = (caddr_t)db_tr;
1172 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1173 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1174 ].end = (caddr_t)db_tr;
1175 }
1176 db_tr++;
1177 }
1178 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1179 = STAILQ_FIRST(&dbch->db_trq);
1180out:
1181 dbch->frag.buf = NULL;
1182 dbch->frag.len = 0;
1183 dbch->frag.plen = 0;
1184 dbch->xferq.queued = 0;
1185 dbch->pdb_tr = NULL;
1186 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1187 dbch->bottom = dbch->top;
1188 dbch->flags = FWOHCI_DBCH_INIT;
1189}
1190
1191static int
1192fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1193{
1194 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1195 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1196 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1197 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1198 fwohci_db_free(&sc->it[dmach]);
1199 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1200 return 0;
1201}
1202
1203static int
1204fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1205{
1206 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1207
1208 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1209 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1210 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1211 if(sc->ir[dmach].dummy != NULL){
1212 free(sc->ir[dmach].dummy, M_DEVBUF);
1213 }
1214 sc->ir[dmach].dummy = NULL;
1215 fwohci_db_free(&sc->ir[dmach]);
1216 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1217 return 0;
1218}
1219
1220static void
1221fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1222{
1223 qld[0] = ntohl(qld[0]);
1224 return;
1225}
1226
1227static int
1228fwohci_irxpp_enable(struct firewire_comm *fc, int dmach)
1229{
1230 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1231 int err = 0;
1232 unsigned short tag, ich;
1233
1234 tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1235 ich = sc->ir[dmach].xferq.flag & 0x3f;
1236
1237#if 0
1238 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){
1239 wakeup(fc->ir[dmach]);
1240 return err;
1241 }
1242#endif
1243
1244 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1245 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1246 sc->ir[dmach].xferq.queued = 0;
1247 sc->ir[dmach].ndb = NDB;
1248 sc->ir[dmach].xferq.psize = FWPMAX_S400;
1249 sc->ir[dmach].ndesc = 1;
1250 fwohci_db_init(&sc->ir[dmach]);
1251 err = fwohci_rx_enable(sc, &sc->ir[dmach]);
1252 }
1253 if(err){
1254 device_printf(sc->fc.dev, "err in IRX setting\n");
1255 return err;
1256 }
1257 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1258 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1259 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1260 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1261 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1262 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000);
1263 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1264 OWRITE(sc, OHCI_IRCMD(dmach),
1265 vtophys(sc->ir[dmach].top->db) | 1);
1266 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1267 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1268 }
1269 return err;
1270}
1271
1272static int
1273fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1274{
1275 int err = 0;
1276 int idb, z, i, dmach = 0;
1277 u_int32_t off = NULL;
1278 struct fwohcidb_tr *db_tr;
1279
1280 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1281 err = EINVAL;
1282 return err;
1283 }
1284 z = dbch->ndesc;
1285 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1286 if( &sc->it[dmach] == dbch){
1287 off = OHCI_ITOFF(dmach);
1288 break;
1289 }
1290 }
1291 if(off == NULL){
1292 err = EINVAL;
1293 return err;
1294 }
1295 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1296 return err;
1297 dbch->xferq.flag |= FWXFERQ_RUNNING;
1298 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1299 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1300 }
1301 db_tr = dbch->top;
1302 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1303 fwohci_add_tx_buf(db_tr,
1304 dbch->xferq.psize, dbch->xferq.flag,
1305 dbch->xferq.buf + dbch->xferq.psize * idb);
1306 if(STAILQ_NEXT(db_tr, link) == NULL){
1307 break;
1308 }
1309 db_tr->db[0].db.desc.depend
1310 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1311 db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1312 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1313 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1314 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1315 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1316 |= OHCI_INTERRUPT_ALWAYS;
1317 db_tr->db[0].db.desc.depend &= ~0xf;
1318 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1319 ~0xf;
1320 }
1321 }
1322 db_tr = STAILQ_NEXT(db_tr, link);
1323 }
1324 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1325 return err;
1326}
1327
1328static int
1329fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1330{
1331 int err = 0;
1332 int idb, z, i, dmach = 0;
1333 u_int32_t off = NULL;
1334 struct fwohcidb_tr *db_tr;
1335
1336 z = dbch->ndesc;
1337 if(&sc->arrq == dbch){
1338 off = OHCI_ARQOFF;
1339 }else if(&sc->arrs == dbch){
1340 off = OHCI_ARSOFF;
1341 }else{
1342 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1343 if( &sc->ir[dmach] == dbch){
1344 off = OHCI_IROFF(dmach);
1345 break;
1346 }
1347 }
1348 }
1349 if(off == NULL){
1350 err = EINVAL;
1351 return err;
1352 }
1353 if(dbch->xferq.flag & FWXFERQ_STREAM){
1354 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1355 return err;
1356 }else{
1357 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1358 err = EBUSY;
1359 return err;
1360 }
1361 }
1362 dbch->xferq.flag |= FWXFERQ_RUNNING;
1363 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1364 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1365 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1366 }
1367 db_tr = dbch->top;
1368 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1369 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1370 fwohci_add_rx_buf(db_tr,
1371 dbch->xferq.psize, dbch->xferq.flag, 0, NULL);
1372 }else{
1373 fwohci_add_rx_buf(db_tr,
1374 dbch->xferq.psize, dbch->xferq.flag,
1375 dbch->xferq.buf + dbch->xferq.psize * idb,
1376 dbch->dummy + sizeof(u_int32_t) * idb);
1377 }
1378 if(STAILQ_NEXT(db_tr, link) == NULL){
1379 break;
1380 }
1381 db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1382 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1383 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1384 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1385 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1386 |= OHCI_INTERRUPT_ALWAYS;
1387 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1388 ~0xf;
1389 }
1390 }
1391 db_tr = STAILQ_NEXT(db_tr, link);
1392 }
1393 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1394 dbch->buf_offset = 0;
1395 if(dbch->xferq.flag & FWXFERQ_STREAM){
1396 return err;
1397 }else{
1398 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z);
1399 }
1400 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1401 return err;
1402}
1403
1404static int
1405fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1406{
1407 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1408 int err = 0;
1409 unsigned short tag, ich;
1410 struct fwohci_dbch *dbch;
1411 struct fw_pkt *fp;
1412 struct fwohcidb_tr *db_tr;
1413
1414 tag = (sc->it[dmach].xferq.flag >> 6) & 3;
1415 ich = sc->it[dmach].xferq.flag & 0x3f;
1416 dbch = &sc->it[dmach];
1417 if(dbch->ndb == 0){
1418 dbch->xferq.queued = 0;
1419 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk;
1420 dbch->ndesc = 3;
1421 fwohci_db_init(dbch);
1422 err = fwohci_tx_enable(sc, dbch);
1423 }
1424 if(err)
1425 return err;
1426 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){
1427 if(dbch->xferq.stdma2 != NULL){
1428 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1429 ((struct fwohcidb_tr *)
1430 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1431 |= OHCI_BRANCH_ALWAYS;
1432 ((struct fwohcidb_tr *)
1433 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1434 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1435 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1436 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1437 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1438 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1439 }
1440 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1441 fw_tbuf_update(&sc->fc, dmach, 0);
1442 if(dbch->xferq.stdma == NULL){
1443 return err;
1444 }
1445 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1446 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1447 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1448 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1449 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000);
1450 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma);
1451 if(dbch->xferq.stdma2 != NULL){
1452 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1453 ((struct fwohcidb_tr *)
1454 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1455 |= OHCI_BRANCH_ALWAYS;
1456 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1457 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1458 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1459 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1460 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1461 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1462 }else{
1463 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1464 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1465 }
1466 OWRITE(sc, OHCI_ITCMD(dmach),
1467 vtophys(((struct fwohcidb_tr *)
1468 (dbch->xferq.stdma->start))->db) | dbch->ndesc);
1469 if(dbch->xferq.flag & FWXFERQ_DV){
1470 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start;
1471 fp = (struct fw_pkt *)db_tr->buf;
1472 fp->mode.ld[2] = htonl(0x80000000 +
1473 ((fc->cyctimer(fc) + 0x3000) & 0xf000));
1474 }
1475
1476 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1477 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1478 }
1479 return err;
1480}
1481
1482static int
1483fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
1484{
1485 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1486 int err = 0;
1487 unsigned short tag, ich;
| 34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4
42#define IRX_CH 0x24
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/types.h>
47#include <sys/mbuf.h>
48#include <sys/mman.h>
49#include <sys/socket.h>
50#include <sys/socketvar.h>
51#include <sys/signalvar.h>
52#include <sys/malloc.h>
53#include <sys/uio.h>
54#include <sys/sockio.h>
55#include <sys/bus.h>
56#include <sys/kernel.h>
57#include <sys/conf.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
61#include <sys/rman.h>
62
63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */
64#include <machine/clock.h>
65#include <pci/pcivar.h>
66#include <pci/pcireg.h>
67#include <vm/vm.h>
68#include <vm/vm_extern.h>
69#include <vm/pmap.h> /* for vtophys proto */
70
71#include <dev/firewire/firewire.h>
72#include <dev/firewire/firewirereg.h>
73#include <dev/firewire/fwohcireg.h>
74#include <dev/firewire/fwohcivar.h>
75#include <dev/firewire/firewire_phy.h>
76
77#undef OHCI_DEBUG
78
79static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
80 "STOR","LOAD","NOP ","STOP",};
81static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
82 "UNDEF","REG","SYS","DEV"};
83char fwohcicode[32][0x20]={
84 "No stat","Undef","long","miss Ack err",
85 "underrun","overrun","desc err", "data read err",
86 "data write err","bus reset","timeout","tcode err",
87 "Undef","Undef","unknown event","flushed",
88 "Undef","ack complete","ack pend","Undef",
89 "ack busy_X","ack busy_A","ack busy_B","Undef",
90 "Undef","Undef","Undef","ack tardy",
91 "Undef","ack data_err","ack type_err",""};
92#define MAX_SPEED 2
93extern char linkspeed[MAX_SPEED+1][0x10];
94static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
95u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
96
97static struct tcode_info tinfo[] = {
98/* hdr_len block flag*/
99/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
100/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
101/* 2 WRES */ {12, FWTI_RES},
102/* 3 XXX */ { 0, 0},
103/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
104/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
105/* 6 RRESQ */ {16, FWTI_RES},
106/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
107/* 8 CYCS */ { 0, 0},
108/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
109/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
110/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
111/* c XXX */ { 0, 0},
112/* d XXX */ { 0, 0},
113/* e PHY */ {12, FWTI_REQ},
114/* f XXX */ { 0, 0}
115};
116
117#define OHCI_WRITE_SIGMASK 0xffff0000
118#define OHCI_READ_SIGMASK 0xffff0000
119
120#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
121#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
122
123static void fwohci_ibr __P((struct firewire_comm *));
124static void fwohci_db_init __P((struct fwohci_dbch *));
125static void fwohci_db_free __P((struct fwohci_dbch *));
126static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
127static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int));
128static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *));
129static void fwohci_start_atq __P((struct firewire_comm *));
130static void fwohci_start_ats __P((struct firewire_comm *));
131static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *));
132static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *));
133static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *));
134static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *));
135static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t));
136static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t));
137static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
138static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *));
139static int fwohci_irx_enable __P((struct firewire_comm *, int));
140static int fwohci_irxpp_enable __P((struct firewire_comm *, int));
141static int fwohci_irxbuf_enable __P((struct firewire_comm *, int));
142static int fwohci_irx_disable __P((struct firewire_comm *, int));
143static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *));
144static int fwohci_itxbuf_enable __P((struct firewire_comm *, int));
145static int fwohci_itx_disable __P((struct firewire_comm *, int));
146static void fwohci_timeout __P((void *));
147static void fwohci_poll __P((struct firewire_comm *, int, int));
148static void fwohci_set_intr __P((struct firewire_comm *, int));
149static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *));
150static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *));
151static void dump_db __P((struct fwohci_softc *, u_int32_t));
152static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t));
153static void dump_dma __P((struct fwohci_softc *, u_int32_t));
154static u_int32_t fwohci_cyctimer __P((struct firewire_comm *));
155static void fwohci_rbuf_update __P((struct fwohci_softc *, int));
156static void fwohci_tbuf_update __P((struct fwohci_softc *, int));
157void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *));
158
159/*
160 * memory allocated for DMA programs
161 */
162#define DMA_PROG_ALLOC (8 * PAGE_SIZE)
163
164/* #define NDB 1024 */
165#define NDB FWMAXQUEUE
166#define NDVDB (DVBUF * NDB)
167
168#define OHCI_VERSION 0x00
169#define OHCI_CROMHDR 0x18
170#define OHCI_BUS_OPT 0x20
171#define OHCI_BUSIRMC (1 << 31)
172#define OHCI_BUSCMC (1 << 30)
173#define OHCI_BUSISC (1 << 29)
174#define OHCI_BUSBMC (1 << 28)
175#define OHCI_BUSPMC (1 << 27)
176#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
177 OHCI_BUSBMC | OHCI_BUSPMC
178
179#define OHCI_EUID_HI 0x24
180#define OHCI_EUID_LO 0x28
181
182#define OHCI_CROMPTR 0x34
183#define OHCI_HCCCTL 0x50
184#define OHCI_HCCCTLCLR 0x54
185#define OHCI_AREQHI 0x100
186#define OHCI_AREQHICLR 0x104
187#define OHCI_AREQLO 0x108
188#define OHCI_AREQLOCLR 0x10c
189#define OHCI_PREQHI 0x110
190#define OHCI_PREQHICLR 0x114
191#define OHCI_PREQLO 0x118
192#define OHCI_PREQLOCLR 0x11c
193#define OHCI_PREQUPPER 0x120
194
195#define OHCI_SID_BUF 0x64
196#define OHCI_SID_CNT 0x68
197#define OHCI_SID_CNT_MASK 0xffc
198
199#define OHCI_IT_STAT 0x90
200#define OHCI_IT_STATCLR 0x94
201#define OHCI_IT_MASK 0x98
202#define OHCI_IT_MASKCLR 0x9c
203
204#define OHCI_IR_STAT 0xa0
205#define OHCI_IR_STATCLR 0xa4
206#define OHCI_IR_MASK 0xa8
207#define OHCI_IR_MASKCLR 0xac
208
209#define OHCI_LNKCTL 0xe0
210#define OHCI_LNKCTLCLR 0xe4
211
212#define OHCI_PHYACCESS 0xec
213#define OHCI_CYCLETIMER 0xf0
214
215#define OHCI_DMACTL(off) (off)
216#define OHCI_DMACTLCLR(off) (off + 4)
217#define OHCI_DMACMD(off) (off + 0xc)
218#define OHCI_DMAMATCH(off) (off + 0x10)
219
220#define OHCI_ATQOFF 0x180
221#define OHCI_ATQCTL OHCI_ATQOFF
222#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
223#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
224#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
225
226#define OHCI_ATSOFF 0x1a0
227#define OHCI_ATSCTL OHCI_ATSOFF
228#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
229#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
230#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
231
232#define OHCI_ARQOFF 0x1c0
233#define OHCI_ARQCTL OHCI_ARQOFF
234#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
235#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
236#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
237
238#define OHCI_ARSOFF 0x1e0
239#define OHCI_ARSCTL OHCI_ARSOFF
240#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
241#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
242#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
243
244#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
245#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
246#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
247#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
248
249#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
250#define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
251#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
252#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
253#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
254
255d_ioctl_t fwohci_ioctl;
256
257/*
258 * Communication with PHY device
259 */
260static u_int32_t
261fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
262{
263 u_int32_t fun;
264
265 addr &= 0xf;
266 data &= 0xff;
267
268 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
269 OWRITE(sc, OHCI_PHYACCESS, fun);
270 DELAY(100);
271
272 return(fwphy_rddata( sc, addr));
273}
274
275static u_int32_t
276fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
277{
278 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
279 int i;
280 u_int32_t bm;
281
282#define OHCI_CSR_DATA 0x0c
283#define OHCI_CSR_COMP 0x10
284#define OHCI_CSR_CONT 0x14
285#define OHCI_BUS_MANAGER_ID 0
286
287 OWRITE(sc, OHCI_CSR_DATA, node);
288 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
289 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
290 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
291 DELAY(100);
292 bm = OREAD(sc, OHCI_CSR_DATA);
293 if((bm & 0x3f) == 0x3f)
294 bm = node;
295 if (bootverbose)
296 device_printf(sc->fc.dev,
297 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
298
299 return(bm);
300}
301
302static u_int32_t
303fwphy_rddata(struct fwohci_softc *sc, u_int addr)
304{
305 u_int32_t fun, stat;
306 u_int i, retry = 0;
307
308 addr &= 0xf;
309#define MAX_RETRY 100
310again:
311 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
312 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
313 OWRITE(sc, OHCI_PHYACCESS, fun);
314 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
315 fun = OREAD(sc, OHCI_PHYACCESS);
316 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
317 break;
318 DELAY(1000);
319 }
320 if(i >= MAX_RETRY) {
321 device_printf(sc->fc.dev, "cannot read phy\n");
322#if 0
323 return 0; /* XXX */
324#else
325 if (++retry < MAX_RETRY) {
326 DELAY(1000);
327 goto again;
328 }
329#endif
330 }
331 /* Make sure that SCLK is started */
332 stat = OREAD(sc, FWOHCI_INTSTAT);
333 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
335 if (++retry < MAX_RETRY) {
336 DELAY(1000);
337 goto again;
338 }
339 }
340 if (bootverbose || retry >= MAX_RETRY)
341 device_printf(sc->fc.dev,
342 "fwphy_rddata: loop=%d, retry=%d\n", i, retry);
343#undef MAX_RETRY
344 return((fun >> PHYDEV_RDDATA )& 0xff);
345}
346/* Device specific ioctl. */
347int
348fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
349{
350 struct firewire_softc *sc;
351 struct fwohci_softc *fc;
352 int unit = DEV2UNIT(dev);
353 int err = 0;
354 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
355 u_int32_t *dmach = (u_int32_t *) data;
356
357 sc = devclass_get_softc(firewire_devclass, unit);
358 if(sc == NULL){
359 return(EINVAL);
360 }
361 fc = (struct fwohci_softc *)sc->fc;
362
363 if (!data)
364 return(EINVAL);
365
366 switch (cmd) {
367 case FWOHCI_WRREG:
368#define OHCI_MAX_REG 0x800
369 if(reg->addr <= OHCI_MAX_REG){
370 OWRITE(fc, reg->addr, reg->data);
371 reg->data = OREAD(fc, reg->addr);
372 }else{
373 err = EINVAL;
374 }
375 break;
376 case FWOHCI_RDREG:
377 if(reg->addr <= OHCI_MAX_REG){
378 reg->data = OREAD(fc, reg->addr);
379 }else{
380 err = EINVAL;
381 }
382 break;
383/* Read DMA descriptors for debug */
384 case DUMPDMA:
385 if(*dmach <= OHCI_MAX_DMA_CH ){
386 dump_dma(fc, *dmach);
387 dump_db(fc, *dmach);
388 }else{
389 err = EINVAL;
390 }
391 break;
392 default:
393 break;
394 }
395 return err;
396}
397
398static int
399fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
400{
401 u_int32_t reg, reg2;
402 int e1394a = 1;
403/*
404 * probe PHY parameters
405 * 0. to prove PHY version, whether compliance of 1394a.
406 * 1. to probe maximum speed supported by the PHY and
407 * number of port supported by core-logic.
408 * It is not actually available port on your PC .
409 */
410 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
411#if 0
412 /* XXX wait for SCLK. */
413 DELAY(100000);
414#endif
415 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
416
417 if((reg >> 5) != 7 ){
418 sc->fc.mode &= ~FWPHYASYST;
419 sc->fc.nport = reg & FW_PHY_NP;
420 sc->fc.speed = reg & FW_PHY_SPD >> 6;
421 if (sc->fc.speed > MAX_SPEED) {
422 device_printf(dev, "invalid speed %d (fixed to %d).\n",
423 sc->fc.speed, MAX_SPEED);
424 sc->fc.speed = MAX_SPEED;
425 }
426 device_printf(dev,
427 "Phy 1394 only %s, %d ports.\n",
428 linkspeed[sc->fc.speed], sc->fc.nport);
429 }else{
430 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
431 sc->fc.mode |= FWPHYASYST;
432 sc->fc.nport = reg & FW_PHY_NP;
433 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
434 if (sc->fc.speed > MAX_SPEED) {
435 device_printf(dev, "invalid speed %d (fixed to %d).\n",
436 sc->fc.speed, MAX_SPEED);
437 sc->fc.speed = MAX_SPEED;
438 }
439 device_printf(dev,
440 "Phy 1394a available %s, %d ports.\n",
441 linkspeed[sc->fc.speed], sc->fc.nport);
442
443 /* check programPhyEnable */
444 reg2 = fwphy_rddata(sc, 5);
445#if 0
446 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
447#else /* XXX force to enable 1394a */
448 if (e1394a) {
449#endif
450 if (bootverbose)
451 device_printf(dev,
452 "Enable 1394a Enhancements\n");
453 /* enable EAA EMC */
454 reg2 |= 0x03;
455 /* set aPhyEnhanceEnable */
456 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
457 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
458 } else {
459 /* for safe */
460 reg2 &= ~0x83;
461 }
462 reg2 = fwphy_wrdata(sc, 5, reg2);
463 }
464
465 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
466 if((reg >> 5) == 7 ){
467 reg = fwphy_rddata(sc, 4);
468 reg |= 1 << 6;
469 fwphy_wrdata(sc, 4, reg);
470 reg = fwphy_rddata(sc, 4);
471 }
472 return 0;
473}
474
475
476void
477fwohci_reset(struct fwohci_softc *sc, device_t dev)
478{
479 int i, max_rec, speed;
480 u_int32_t reg, reg2;
481 struct fwohcidb_tr *db_tr;
482
483 /* Disable interrupt */
484 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
485
486 /* Now stopping all DMA channel */
487 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
488 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
489 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
490 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
491
492 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
493 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
494 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
495 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
496 }
497
498 /* FLUSH FIFO and reset Transmitter/Reciever */
499 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
500 if (bootverbose)
501 device_printf(dev, "resetting OHCI...");
502 i = 0;
503 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
504 if (i++ > 100) break;
505 DELAY(1000);
506 }
507 if (bootverbose)
508 printf("done (loop=%d)\n", i);
509
510 /* Probe phy */
511 fwohci_probe_phy(sc, dev);
512
513 /* Probe link */
514 reg = OREAD(sc, OHCI_BUS_OPT);
515 reg2 = reg | OHCI_BUSFNC;
516 max_rec = (reg & 0x0000f000) >> 12;
517 speed = (reg & 0x00000007);
518 device_printf(dev, "Link %s, max_rec %d bytes.\n",
519 linkspeed[speed], MAXREC(max_rec));
520 /* XXX fix max_rec */
521 sc->fc.maxrec = sc->fc.speed + 8;
522 if (max_rec != sc->fc.maxrec) {
523 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
524 device_printf(dev, "max_rec %d -> %d\n",
525 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
526 }
527 if (bootverbose)
528 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
529 OWRITE(sc, OHCI_BUS_OPT, reg2);
530
531 /* Initialize registers */
532 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
533 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0]));
534 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
535 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
536 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
537 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
538 fw_busreset(&sc->fc);
539
540 /* Enable link */
541 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
542
543 /* Force to start async RX DMA */
544 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
545 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
546 fwohci_rx_enable(sc, &sc->arrq);
547 fwohci_rx_enable(sc, &sc->arrs);
548
549 /* Initialize async TX */
550 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
551 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
552 /* AT Retries */
553 OWRITE(sc, FWOHCI_RETRY,
554 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
555 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
556 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
557 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
558 db_tr->xfer = NULL;
559 }
560 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
561 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
562 db_tr->xfer = NULL;
563 }
564
565
566 /* Enable interrupt */
567 OWRITE(sc, FWOHCI_INTMASK,
568 OHCI_INT_ERR | OHCI_INT_PHY_SID
569 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
570 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
571 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
572 fwohci_set_intr(&sc->fc, 1);
573
574}
575
576int
577fwohci_init(struct fwohci_softc *sc, device_t dev)
578{
579 int i;
580 u_int32_t reg;
581
582 reg = OREAD(sc, OHCI_VERSION);
583 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
584 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1);
585
586/* XXX: Available Isochrounous DMA channel probe */
587 for( i = 0 ; i < 0x20 ; i ++ ){
588 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN);
589 reg = OREAD(sc, OHCI_IRCTL(i));
590 if(!(reg & OHCI_CNTL_DMA_RUN)) break;
591 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN);
592 reg = OREAD(sc, OHCI_ITCTL(i));
593 if(!(reg & OHCI_CNTL_DMA_RUN)) break;
594 }
595 sc->fc.nisodma = i;
596 device_printf(dev, "No. of Isochronous channel is %d.\n", i);
597
598 sc->fc.arq = &sc->arrq.xferq;
599 sc->fc.ars = &sc->arrs.xferq;
600 sc->fc.atq = &sc->atrq.xferq;
601 sc->fc.ats = &sc->atrs.xferq;
602
603 sc->arrq.xferq.start = NULL;
604 sc->arrs.xferq.start = NULL;
605 sc->atrq.xferq.start = fwohci_start_atq;
606 sc->atrs.xferq.start = fwohci_start_ats;
607
608 sc->arrq.xferq.drain = NULL;
609 sc->arrs.xferq.drain = NULL;
610 sc->atrq.xferq.drain = fwohci_drain_atq;
611 sc->atrs.xferq.drain = fwohci_drain_ats;
612
613 sc->arrq.ndesc = 1;
614 sc->arrs.ndesc = 1;
615 sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */
616 sc->atrs.ndesc = 6 / 2;
617
618 sc->arrq.ndb = NDB;
619 sc->arrs.ndb = NDB / 2;
620 sc->atrq.ndb = NDB;
621 sc->atrs.ndb = NDB / 2;
622
623 sc->arrq.dummy = NULL;
624 sc->arrs.dummy = NULL;
625 sc->atrq.dummy = NULL;
626 sc->atrs.dummy = NULL;
627 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
628 sc->fc.it[i] = &sc->it[i].xferq;
629 sc->fc.ir[i] = &sc->ir[i].xferq;
630 sc->it[i].ndb = 0;
631 sc->ir[i].ndb = 0;
632 }
633
634 sc->fc.tcode = tinfo;
635
636 sc->cromptr = (u_int32_t *)
637 contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0);
638
639 if(sc->cromptr == NULL){
640 device_printf(dev, "cromptr alloc failed.");
641 return ENOMEM;
642 }
643 sc->fc.dev = dev;
644 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]);
645
646 sc->fc.config_rom[1] = 0x31333934;
647 sc->fc.config_rom[2] = 0xf000a002;
648 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
649 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
650 sc->fc.config_rom[5] = 0;
651 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
652
653 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
654
655
656/* SID recieve buffer must allign 2^11 */
657#define OHCI_SIDSIZE (1 << 11)
658 sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE,
659 0x10000, 0xffffffff, OHCI_SIDSIZE);
660 if (sc->fc.sid_buf == NULL) {
661 device_printf(dev, "sid_buf alloc failed.\n");
662 return ENOMEM;
663 }
664
665
666 fwohci_db_init(&sc->arrq);
667 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
668 return ENOMEM;
669
670 fwohci_db_init(&sc->arrs);
671 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
672 return ENOMEM;
673
674 fwohci_db_init(&sc->atrq);
675 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
676 return ENOMEM;
677
678 fwohci_db_init(&sc->atrs);
679 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
680 return ENOMEM;
681
682 reg = OREAD(sc, FWOHCIGUID_H);
683 for( i = 0 ; i < 4 ; i ++){
684 sc->fc.eui[3 - i] = reg & 0xff;
685 reg = reg >> 8;
686 }
687 reg = OREAD(sc, FWOHCIGUID_L);
688 for( i = 0 ; i < 4 ; i ++){
689 sc->fc.eui[7 - i] = reg & 0xff;
690 reg = reg >> 8;
691 }
692 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
693 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3],
694 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]);
695 sc->fc.ioctl = fwohci_ioctl;
696 sc->fc.cyctimer = fwohci_cyctimer;
697 sc->fc.set_bmr = fwohci_set_bus_manager;
698 sc->fc.ibr = fwohci_ibr;
699 sc->fc.irx_enable = fwohci_irx_enable;
700 sc->fc.irx_disable = fwohci_irx_disable;
701
702 sc->fc.itx_enable = fwohci_itxbuf_enable;
703 sc->fc.itx_disable = fwohci_itx_disable;
704 sc->fc.irx_post = fwohci_irx_post;
705 sc->fc.itx_post = NULL;
706 sc->fc.timeout = fwohci_timeout;
707 sc->fc.poll = fwohci_poll;
708 sc->fc.set_intr = fwohci_set_intr;
709
710 fw_init(&sc->fc);
711 fwohci_reset(sc, dev);
712
713 return 0;
714}
715
716void
717fwohci_timeout(void *arg)
718{
719 struct fwohci_softc *sc;
720
721 sc = (struct fwohci_softc *)arg;
722 sc->fc.timeouthandle = timeout(fwohci_timeout,
723 (void *)sc, FW_XFERTIMEOUT * hz * 10);
724}
725
726u_int32_t
727fwohci_cyctimer(struct firewire_comm *fc)
728{
729 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
730 return(OREAD(sc, OHCI_CYCLETIMER));
731}
732
733int
734fwohci_detach(struct fwohci_softc *sc, device_t dev)
735{
736 int i;
737
738 if (sc->fc.sid_buf != NULL)
739 contigfree((void *)(uintptr_t)sc->fc.sid_buf,
740 OHCI_SIDSIZE, M_DEVBUF);
741 if (sc->cromptr != NULL)
742 contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF);
743
744 fwohci_db_free(&sc->arrq);
745 fwohci_db_free(&sc->arrs);
746
747 fwohci_db_free(&sc->atrq);
748 fwohci_db_free(&sc->atrs);
749
750 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
751 fwohci_db_free(&sc->it[i]);
752 fwohci_db_free(&sc->ir[i]);
753 }
754
755 return 0;
756}
757
758#define LAST_DB(dbtr, db) do { \
759 struct fwohcidb_tr *_dbtr = (dbtr); \
760 int _cnt = _dbtr->dbcnt; \
761 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
762} while (0)
763
764static void
765fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
766{
767 int i, s;
768 int tcode, hdr_len, hdr_off, len;
769 int fsegment = -1;
770 u_int32_t off;
771 struct fw_xfer *xfer;
772 struct fw_pkt *fp;
773 volatile struct fwohci_txpkthdr *ohcifp;
774 struct fwohcidb_tr *db_tr;
775 volatile struct fwohcidb *db;
776 struct mbuf *m;
777 struct tcode_info *info;
778 static int maxdesc=0;
779
780 if(&sc->atrq == dbch){
781 off = OHCI_ATQOFF;
782 }else if(&sc->atrs == dbch){
783 off = OHCI_ATSOFF;
784 }else{
785 return;
786 }
787
788 if (dbch->flags & FWOHCI_DBCH_FULL)
789 return;
790
791 s = splfw();
792 db_tr = dbch->top;
793txloop:
794 xfer = STAILQ_FIRST(&dbch->xferq.q);
795 if(xfer == NULL){
796 goto kick;
797 }
798 if(dbch->xferq.queued == 0 ){
799 device_printf(sc->fc.dev, "TX queue empty\n");
800 }
801 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
802 db_tr->xfer = xfer;
803 xfer->state = FWXF_START;
804 dbch->xferq.packets++;
805
806 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off);
807 tcode = fp->mode.common.tcode;
808
809 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
810 info = &tinfo[tcode];
811 hdr_len = hdr_off = info->hdr_len;
812 /* fw_asyreq must pass valid send.len */
813 len = xfer->send.len;
814 for( i = 0 ; i < hdr_off ; i+= 4){
815 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]);
816 }
817 ohcifp->mode.common.spd = xfer->spd;
818 if (tcode == FWTCODE_STREAM ){
819 hdr_len = 8;
820 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
821 } else if (tcode == FWTCODE_PHY) {
822 hdr_len = 12;
823 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]);
824 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]);
825 ohcifp->mode.common.spd = 0;
826 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
827 } else {
828 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst);
829 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
830 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
831 }
832 db = &db_tr->db[0];
833 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len;
834 db->db.desc.status = 0;
835/* Specify bound timer of asy. responce */
836 if(&sc->atrs == dbch){
837 db->db.desc.count
838 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13);
839 }
840
841 db_tr->dbcnt = 2;
842 db = &db_tr->db[db_tr->dbcnt];
843 if(len > hdr_off){
844 if (xfer->mbuf == NULL) {
845 db->db.desc.addr
846 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off;
847 db->db.desc.cmd
848 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff);
849 db->db.desc.status = 0;
850
851 db_tr->dbcnt++;
852 } else {
853 /* XXX we assume mbuf chain is shorter than ndesc */
854 for (m = xfer->mbuf; m != NULL; m = m->m_next) {
855 if (m->m_len == 0)
856 /* unrecoverable error could ocurre. */
857 continue;
858 if (db_tr->dbcnt >= dbch->ndesc) {
859 device_printf(sc->fc.dev,
860 "dbch->ndesc is too small"
861 ", trancated.\n");
862 break;
863 }
864 db->db.desc.addr
865 = vtophys(mtod(m, caddr_t));
866 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len;
867 db->db.desc.status = 0;
868 db++;
869 db_tr->dbcnt++;
870 }
871 }
872 }
873 if (maxdesc < db_tr->dbcnt) {
874 maxdesc = db_tr->dbcnt;
875 if (bootverbose)
876 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
877 }
878 /* last db */
879 LAST_DB(db_tr, db);
880 db->db.desc.cmd |= OHCI_OUTPUT_LAST
881 | OHCI_INTERRUPT_ALWAYS
882 | OHCI_BRANCH_ALWAYS;
883 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db);
884
885 if(fsegment == -1 )
886 fsegment = db_tr->dbcnt;
887 if (dbch->pdb_tr != NULL) {
888 LAST_DB(dbch->pdb_tr, db);
889 db->db.desc.depend |= db_tr->dbcnt;
890 }
891 dbch->pdb_tr = db_tr;
892 db_tr = STAILQ_NEXT(db_tr, link);
893 if(db_tr != dbch->bottom){
894 goto txloop;
895 } else {
896 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
897 dbch->flags |= FWOHCI_DBCH_FULL;
898 }
899kick:
900 if (firewire_debug) printf("kick\n");
901 /* kick asy q */
902
903 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
904 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
905 } else {
906 if (bootverbose)
907 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
908 OREAD(sc, OHCI_DMACTL(off)));
909 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment);
910 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
911 dbch->xferq.flag |= FWXFERQ_RUNNING;
912 }
913
914 dbch->top = db_tr;
915 splx(s);
916 return;
917}
918
919static void
920fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer)
921{
922 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
923 fwohci_drain(&sc->fc, xfer, &(sc->atrq));
924 return;
925}
926
927static void
928fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer)
929{
930 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
931 fwohci_drain(&sc->fc, xfer, &(sc->atrs));
932 return;
933}
934
935static void
936fwohci_start_atq(struct firewire_comm *fc)
937{
938 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
939 fwohci_start( sc, &(sc->atrq));
940 return;
941}
942
943static void
944fwohci_start_ats(struct firewire_comm *fc)
945{
946 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
947 fwohci_start( sc, &(sc->atrs));
948 return;
949}
950
951void
952fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
953{
954 int s, err = 0;
955 struct fwohcidb_tr *tr;
956 volatile struct fwohcidb *db;
957 struct fw_xfer *xfer;
958 u_int32_t off;
959 u_int stat;
960 int packets;
961 struct firewire_comm *fc = (struct firewire_comm *)sc;
962 if(&sc->atrq == dbch){
963 off = OHCI_ATQOFF;
964 }else if(&sc->atrs == dbch){
965 off = OHCI_ATSOFF;
966 }else{
967 return;
968 }
969 s = splfw();
970 tr = dbch->bottom;
971 packets = 0;
972 while(dbch->xferq.queued > 0){
973 LAST_DB(tr, db);
974 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){
975 if (fc->status != FWBUSRESET)
976 /* maybe out of order?? */
977 goto out;
978 }
979 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) {
980#ifdef OHCI_DEBUG
981 dump_dma(sc, ch);
982 dump_db(sc, ch);
983#endif
984/* Stop DMA */
985 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
986 device_printf(sc->fc.dev, "force reset AT FIFO\n");
987 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
988 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
989 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
990 }
991 stat = db->db.desc.status & FWOHCIEV_MASK;
992 switch(stat){
993 case FWOHCIEV_ACKCOMPL:
994 case FWOHCIEV_ACKPEND:
995 err = 0;
996 break;
997 case FWOHCIEV_ACKBSA:
998 case FWOHCIEV_ACKBSB:
999 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1000 case FWOHCIEV_ACKBSX:
1001 err = EBUSY;
1002 break;
1003 case FWOHCIEV_FLUSHED:
1004 case FWOHCIEV_ACKTARD:
1005 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1006 err = EAGAIN;
1007 break;
1008 case FWOHCIEV_MISSACK:
1009 case FWOHCIEV_UNDRRUN:
1010 case FWOHCIEV_OVRRUN:
1011 case FWOHCIEV_DESCERR:
1012 case FWOHCIEV_DTRDERR:
1013 case FWOHCIEV_TIMEOUT:
1014 case FWOHCIEV_TCODERR:
1015 case FWOHCIEV_UNKNOWN:
1016 case FWOHCIEV_ACKDERR:
1017 case FWOHCIEV_ACKTERR:
1018 default:
1019 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1020 stat, fwohcicode[stat]);
1021 err = EINVAL;
1022 break;
1023 }
1024 if(tr->xfer != NULL){
1025 xfer = tr->xfer;
1026 xfer->state = FWXF_SENT;
1027 if(err == EBUSY && fc->status != FWBUSRESET){
1028 xfer->state = FWXF_BUSY;
1029 switch(xfer->act_type){
1030 case FWACT_XFER:
1031 xfer->resp = err;
1032 if(xfer->retry_req != NULL){
1033 xfer->retry_req(xfer);
1034 }
1035 break;
1036 default:
1037 break;
1038 }
1039 } else if( stat != FWOHCIEV_ACKPEND){
1040 if (stat != FWOHCIEV_ACKCOMPL)
1041 xfer->state = FWXF_SENTERR;
1042 xfer->resp = err;
1043 switch(xfer->act_type){
1044 case FWACT_XFER:
1045 fw_xfer_done(xfer);
1046 break;
1047 default:
1048 break;
1049 }
1050 }
1051 dbch->xferq.queued --;
1052 }
1053 tr->xfer = NULL;
1054
1055 packets ++;
1056 tr = STAILQ_NEXT(tr, link);
1057 dbch->bottom = tr;
1058 }
1059out:
1060 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1061 printf("make free slot\n");
1062 dbch->flags &= ~FWOHCI_DBCH_FULL;
1063 fwohci_start(sc, dbch);
1064 }
1065 splx(s);
1066}
1067
1068static void
1069fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch)
1070{
1071 int i, s;
1072 struct fwohcidb_tr *tr;
1073
1074 if(xfer->state != FWXF_START) return;
1075
1076 s = splfw();
1077 tr = dbch->bottom;
1078 for( i = 0 ; i <= dbch->xferq.queued ; i ++){
1079 if(tr->xfer == xfer){
1080 s = splfw();
1081 tr->xfer = NULL;
1082 dbch->xferq.queued --;
1083#if 1
1084 /* XXX */
1085 if (tr == dbch->bottom)
1086 dbch->bottom = STAILQ_NEXT(tr, link);
1087#endif
1088 if (dbch->flags & FWOHCI_DBCH_FULL) {
1089 printf("fwohci_drain: make slot\n");
1090 dbch->flags &= ~FWOHCI_DBCH_FULL;
1091 fwohci_start((struct fwohci_softc *)fc, dbch);
1092 }
1093
1094 splx(s);
1095 break;
1096 }
1097 tr = STAILQ_NEXT(tr, link);
1098 }
1099 splx(s);
1100 return;
1101}
1102
1103static void
1104fwohci_db_free(struct fwohci_dbch *dbch)
1105{
1106 struct fwohcidb_tr *db_tr;
1107 int idb;
1108
1109 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1110 return;
1111
1112 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1113 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0;
1114 idb < dbch->ndb;
1115 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1116 if (db_tr->buf != NULL) {
1117 free(db_tr->buf, M_DEVBUF);
1118 db_tr->buf = NULL;
1119 }
1120 }
1121 }
1122 dbch->ndb = 0;
1123 db_tr = STAILQ_FIRST(&dbch->db_trq);
1124 contigfree((void *)(uintptr_t)(volatile void *)db_tr->db,
1125 sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF);
1126 free(db_tr, M_DEVBUF);
1127 STAILQ_INIT(&dbch->db_trq);
1128 dbch->flags &= ~FWOHCI_DBCH_INIT;
1129}
1130
1131static void
1132fwohci_db_init(struct fwohci_dbch *dbch)
1133{
1134 int idb;
1135 struct fwohcidb *db;
1136 struct fwohcidb_tr *db_tr;
1137
1138
1139 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1140 goto out;
1141
1142 /* allocate DB entries and attach one to each DMA channels */
1143 /* DB entry must start at 16 bytes bounary. */
1144 STAILQ_INIT(&dbch->db_trq);
1145 db_tr = (struct fwohcidb_tr *)
1146 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1147 M_DEVBUF, M_DONTWAIT | M_ZERO);
1148 if(db_tr == NULL){
1149 printf("fwohci_db_init: malloc failed\n");
1150 return;
1151 }
1152 db = (struct fwohcidb *)
1153 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb,
1154 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul);
1155 if(db == NULL){
1156 printf("fwohci_db_init: contigmalloc failed\n");
1157 free(db_tr, M_DEVBUF);
1158 return;
1159 }
1160 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb);
1161 /* Attach DB to DMA ch. */
1162 for(idb = 0 ; idb < dbch->ndb ; idb++){
1163 db_tr->dbcnt = 0;
1164 db_tr->db = &db[idb * dbch->ndesc];
1165 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1166 if (!(dbch->xferq.flag & FWXFERQ_PACKET) &&
1167 dbch->xferq.bnpacket != 0) {
1168 /* XXX what those for? */
1169 if (idb % dbch->xferq.bnpacket == 0)
1170 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1171 ].start = (caddr_t)db_tr;
1172 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1173 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1174 ].end = (caddr_t)db_tr;
1175 }
1176 db_tr++;
1177 }
1178 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1179 = STAILQ_FIRST(&dbch->db_trq);
1180out:
1181 dbch->frag.buf = NULL;
1182 dbch->frag.len = 0;
1183 dbch->frag.plen = 0;
1184 dbch->xferq.queued = 0;
1185 dbch->pdb_tr = NULL;
1186 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1187 dbch->bottom = dbch->top;
1188 dbch->flags = FWOHCI_DBCH_INIT;
1189}
1190
1191static int
1192fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1193{
1194 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1195 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1196 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1197 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1198 fwohci_db_free(&sc->it[dmach]);
1199 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1200 return 0;
1201}
1202
1203static int
1204fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1205{
1206 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1207
1208 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1209 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1210 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1211 if(sc->ir[dmach].dummy != NULL){
1212 free(sc->ir[dmach].dummy, M_DEVBUF);
1213 }
1214 sc->ir[dmach].dummy = NULL;
1215 fwohci_db_free(&sc->ir[dmach]);
1216 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1217 return 0;
1218}
1219
1220static void
1221fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1222{
1223 qld[0] = ntohl(qld[0]);
1224 return;
1225}
1226
1227static int
1228fwohci_irxpp_enable(struct firewire_comm *fc, int dmach)
1229{
1230 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1231 int err = 0;
1232 unsigned short tag, ich;
1233
1234 tag = (sc->ir[dmach].xferq.flag >> 6) & 3;
1235 ich = sc->ir[dmach].xferq.flag & 0x3f;
1236
1237#if 0
1238 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){
1239 wakeup(fc->ir[dmach]);
1240 return err;
1241 }
1242#endif
1243
1244 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1245 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){
1246 sc->ir[dmach].xferq.queued = 0;
1247 sc->ir[dmach].ndb = NDB;
1248 sc->ir[dmach].xferq.psize = FWPMAX_S400;
1249 sc->ir[dmach].ndesc = 1;
1250 fwohci_db_init(&sc->ir[dmach]);
1251 err = fwohci_rx_enable(sc, &sc->ir[dmach]);
1252 }
1253 if(err){
1254 device_printf(sc->fc.dev, "err in IRX setting\n");
1255 return err;
1256 }
1257 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1258 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1259 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1260 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1261 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1262 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000);
1263 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1264 OWRITE(sc, OHCI_IRCMD(dmach),
1265 vtophys(sc->ir[dmach].top->db) | 1);
1266 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1267 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1268 }
1269 return err;
1270}
1271
1272static int
1273fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1274{
1275 int err = 0;
1276 int idb, z, i, dmach = 0;
1277 u_int32_t off = NULL;
1278 struct fwohcidb_tr *db_tr;
1279
1280 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1281 err = EINVAL;
1282 return err;
1283 }
1284 z = dbch->ndesc;
1285 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1286 if( &sc->it[dmach] == dbch){
1287 off = OHCI_ITOFF(dmach);
1288 break;
1289 }
1290 }
1291 if(off == NULL){
1292 err = EINVAL;
1293 return err;
1294 }
1295 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1296 return err;
1297 dbch->xferq.flag |= FWXFERQ_RUNNING;
1298 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1299 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1300 }
1301 db_tr = dbch->top;
1302 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1303 fwohci_add_tx_buf(db_tr,
1304 dbch->xferq.psize, dbch->xferq.flag,
1305 dbch->xferq.buf + dbch->xferq.psize * idb);
1306 if(STAILQ_NEXT(db_tr, link) == NULL){
1307 break;
1308 }
1309 db_tr->db[0].db.desc.depend
1310 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1311 db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1312 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1313 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1314 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1315 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1316 |= OHCI_INTERRUPT_ALWAYS;
1317 db_tr->db[0].db.desc.depend &= ~0xf;
1318 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1319 ~0xf;
1320 }
1321 }
1322 db_tr = STAILQ_NEXT(db_tr, link);
1323 }
1324 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1325 return err;
1326}
1327
1328static int
1329fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1330{
1331 int err = 0;
1332 int idb, z, i, dmach = 0;
1333 u_int32_t off = NULL;
1334 struct fwohcidb_tr *db_tr;
1335
1336 z = dbch->ndesc;
1337 if(&sc->arrq == dbch){
1338 off = OHCI_ARQOFF;
1339 }else if(&sc->arrs == dbch){
1340 off = OHCI_ARSOFF;
1341 }else{
1342 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1343 if( &sc->ir[dmach] == dbch){
1344 off = OHCI_IROFF(dmach);
1345 break;
1346 }
1347 }
1348 }
1349 if(off == NULL){
1350 err = EINVAL;
1351 return err;
1352 }
1353 if(dbch->xferq.flag & FWXFERQ_STREAM){
1354 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1355 return err;
1356 }else{
1357 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1358 err = EBUSY;
1359 return err;
1360 }
1361 }
1362 dbch->xferq.flag |= FWXFERQ_RUNNING;
1363 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1364 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1365 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1366 }
1367 db_tr = dbch->top;
1368 for( idb = 0 ; idb < dbch->ndb ; idb ++){
1369 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1370 fwohci_add_rx_buf(db_tr,
1371 dbch->xferq.psize, dbch->xferq.flag, 0, NULL);
1372 }else{
1373 fwohci_add_rx_buf(db_tr,
1374 dbch->xferq.psize, dbch->xferq.flag,
1375 dbch->xferq.buf + dbch->xferq.psize * idb,
1376 dbch->dummy + sizeof(u_int32_t) * idb);
1377 }
1378 if(STAILQ_NEXT(db_tr, link) == NULL){
1379 break;
1380 }
1381 db_tr->db[db_tr->dbcnt - 1].db.desc.depend
1382 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z;
1383 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1384 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1385 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd
1386 |= OHCI_INTERRUPT_ALWAYS;
1387 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &=
1388 ~0xf;
1389 }
1390 }
1391 db_tr = STAILQ_NEXT(db_tr, link);
1392 }
1393 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0;
1394 dbch->buf_offset = 0;
1395 if(dbch->xferq.flag & FWXFERQ_STREAM){
1396 return err;
1397 }else{
1398 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z);
1399 }
1400 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1401 return err;
1402}
1403
1404static int
1405fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1406{
1407 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1408 int err = 0;
1409 unsigned short tag, ich;
1410 struct fwohci_dbch *dbch;
1411 struct fw_pkt *fp;
1412 struct fwohcidb_tr *db_tr;
1413
1414 tag = (sc->it[dmach].xferq.flag >> 6) & 3;
1415 ich = sc->it[dmach].xferq.flag & 0x3f;
1416 dbch = &sc->it[dmach];
1417 if(dbch->ndb == 0){
1418 dbch->xferq.queued = 0;
1419 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk;
1420 dbch->ndesc = 3;
1421 fwohci_db_init(dbch);
1422 err = fwohci_tx_enable(sc, dbch);
1423 }
1424 if(err)
1425 return err;
1426 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){
1427 if(dbch->xferq.stdma2 != NULL){
1428 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1429 ((struct fwohcidb_tr *)
1430 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1431 |= OHCI_BRANCH_ALWAYS;
1432 ((struct fwohcidb_tr *)
1433 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1434 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1435 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1436 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1437 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1438 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1439 }
1440 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1441 fw_tbuf_update(&sc->fc, dmach, 0);
1442 if(dbch->xferq.stdma == NULL){
1443 return err;
1444 }
1445 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1446 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1447 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1448 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1449 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000);
1450 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma);
1451 if(dbch->xferq.stdma2 != NULL){
1452 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1453 ((struct fwohcidb_tr *)
1454 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1455 |= OHCI_BRANCH_ALWAYS;
1456 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1457 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1458 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1459 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1460 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1461 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1462 }else{
1463 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1464 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1465 }
1466 OWRITE(sc, OHCI_ITCMD(dmach),
1467 vtophys(((struct fwohcidb_tr *)
1468 (dbch->xferq.stdma->start))->db) | dbch->ndesc);
1469 if(dbch->xferq.flag & FWXFERQ_DV){
1470 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start;
1471 fp = (struct fw_pkt *)db_tr->buf;
1472 fp->mode.ld[2] = htonl(0x80000000 +
1473 ((fc->cyctimer(fc) + 0x3000) & 0xf000));
1474 }
1475
1476 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1477 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1478 }
1479 return err;
1480}
1481
1482static int
1483fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
1484{
1485 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1486 int err = 0;
1487 unsigned short tag, ich;
|
1544 return err;
1545}
1546
1547static int
1548fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1549{
1550 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1551 int err = 0;
1552
1553 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){
1554 err = fwohci_irxpp_enable(fc, dmach);
1555 return err;
1556 }else{
1557 err = fwohci_irxbuf_enable(fc, dmach);
1558 return err;
1559 }
1560}
1561
1562int
1563fwohci_shutdown(struct fwohci_softc *sc, device_t dev)
1564{
1565 u_int i;
1566
1567/* Now stopping all DMA channel */
1568 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1569 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1570 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1571 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1572
1573 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1574 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1575 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1576 }
1577
1578/* FLUSH FIFO and reset Transmitter/Reciever */
1579 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1580
1581/* Stop interrupt */
1582 OWRITE(sc, FWOHCI_INTMASKCLR,
1583 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1584 | OHCI_INT_PHY_INT
1585 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1586 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1587 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1588 | OHCI_INT_PHY_BUS_R);
1589/* XXX Link down? Bus reset? */
1590 return 0;
1591}
1592
1593int
1594fwohci_resume(struct fwohci_softc *sc, device_t dev)
1595{
1596 int i;
1597
1598 fwohci_reset(sc, dev);
1599 /* XXX resume isochronus receive automatically. (how about TX?) */
1600 for(i = 0; i < sc->fc.nisodma; i ++) {
1601 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) {
1602 device_printf(sc->fc.dev,
1603 "resume iso receive ch: %d\n", i);
1604 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING;
1605 sc->fc.irx_enable(&sc->fc, i);
1606 }
1607 }
1608
1609 bus_generic_resume(dev);
1610 sc->fc.ibr(&sc->fc);
1611 return 0;
1612}
1613
1614#define ACK_ALL
1615static void
1616fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1617{
1618 u_int32_t irstat, itstat;
1619 u_int i;
1620 struct firewire_comm *fc = (struct firewire_comm *)sc;
1621
1622#ifdef OHCI_DEBUG
1623 if(stat & OREAD(sc, FWOHCI_INTMASK))
1624 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1625 stat & OHCI_INT_EN ? "DMA_EN ":"",
1626 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1627 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1628 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1629 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1630 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1631 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1632 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1633 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1634 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1635 stat & OHCI_INT_PHY_SID ? "SID ":"",
1636 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1637 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1638 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1639 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1640 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1641 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1642 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1643 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1644 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1645 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1646 stat, OREAD(sc, FWOHCI_INTMASK)
1647 );
1648#endif
1649/* Bus reset */
1650 if(stat & OHCI_INT_PHY_BUS_R ){
1651 device_printf(fc->dev, "BUS reset\n");
1652 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1653 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1654
1655 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1656 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1657 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1658 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1659
1660#if 0
1661 for( i = 0 ; i < fc->nisodma ; i ++ ){
1662 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1663 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1664 }
1665
1666#endif
1667 fw_busreset(fc);
1668
1669 /* XXX need to wait DMA to stop */
1670#ifndef ACK_ALL
1671 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1672#endif
1673#if 1
1674 /* pending all pre-bus_reset packets */
1675 fwohci_txd(sc, &sc->atrq);
1676 fwohci_txd(sc, &sc->atrs);
1677 fwohci_arcv(sc, &sc->arrs, -1);
1678 fwohci_arcv(sc, &sc->arrq, -1);
1679#endif
1680
1681
1682 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1683 /* XXX insecure ?? */
1684 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1685 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1686 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1687
1688 }
1689 if((stat & OHCI_INT_DMA_IR )){
1690#ifndef ACK_ALL
1691 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1692#endif
1693 irstat = OREAD(sc, OHCI_IR_STAT);
1694 OWRITE(sc, OHCI_IR_STATCLR, ~0);
1695 for(i = 0; i < fc->nisodma ; i++){
1696 if((irstat & (1 << i)) != 0){
1697 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){
1698 fwohci_ircv(sc, &sc->ir[i], count);
1699 }else{
1700 fwohci_rbuf_update(sc, i);
1701 }
1702 }
1703 }
1704 }
1705 if((stat & OHCI_INT_DMA_IT )){
1706#ifndef ACK_ALL
1707 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1708#endif
1709 itstat = OREAD(sc, OHCI_IT_STAT);
1710 OWRITE(sc, OHCI_IT_STATCLR, ~0);
1711 for(i = 0; i < fc->nisodma ; i++){
1712 if((itstat & (1 << i)) != 0){
1713 fwohci_tbuf_update(sc, i);
1714 }
1715 }
1716 }
1717 if((stat & OHCI_INT_DMA_PRRS )){
1718#ifndef ACK_ALL
1719 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1720#endif
1721#if 0
1722 dump_dma(sc, ARRS_CH);
1723 dump_db(sc, ARRS_CH);
1724#endif
1725 fwohci_arcv(sc, &sc->arrs, count);
1726 }
1727 if((stat & OHCI_INT_DMA_PRRQ )){
1728#ifndef ACK_ALL
1729 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1730#endif
1731#if 0
1732 dump_dma(sc, ARRQ_CH);
1733 dump_db(sc, ARRQ_CH);
1734#endif
1735 fwohci_arcv(sc, &sc->arrq, count);
1736 }
1737 if(stat & OHCI_INT_PHY_SID){
1738 caddr_t buf;
1739 int plen;
1740
1741#ifndef ACK_ALL
1742 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1743#endif
1744/*
1745** Checking whether the node is root or not. If root, turn on
1746** cycle master.
1747*/
1748 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID));
1749 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){
1750 printf("Bus reset failure\n");
1751 goto sidout;
1752 }
1753 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){
1754 printf("CYCLEMASTER mode\n");
1755 OWRITE(sc, OHCI_LNKCTL,
1756 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1757 }else{
1758 printf("non CYCLEMASTER mode\n");
1759 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1760 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1761 }
1762 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f;
1763
1764 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK;
1765 plen -= 4; /* chop control info */
1766 buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT);
1767 if(buf == NULL) goto sidout;
1768 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1),
1769 buf, plen);
1770 fw_sidrcv(fc, buf, plen, 0);
1771 }
1772sidout:
1773 if((stat & OHCI_INT_DMA_ATRQ )){
1774#ifndef ACK_ALL
1775 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1776#endif
1777 fwohci_txd(sc, &(sc->atrq));
1778 }
1779 if((stat & OHCI_INT_DMA_ATRS )){
1780#ifndef ACK_ALL
1781 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1782#endif
1783 fwohci_txd(sc, &(sc->atrs));
1784 }
1785 if((stat & OHCI_INT_PW_ERR )){
1786#ifndef ACK_ALL
1787 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1788#endif
1789 device_printf(fc->dev, "posted write error\n");
1790 }
1791 if((stat & OHCI_INT_ERR )){
1792#ifndef ACK_ALL
1793 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1794#endif
1795 device_printf(fc->dev, "unrecoverable error\n");
1796 }
1797 if((stat & OHCI_INT_PHY_INT)) {
1798#ifndef ACK_ALL
1799 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1800#endif
1801 device_printf(fc->dev, "phy int\n");
1802 }
1803
1804 return;
1805}
1806
1807void
1808fwohci_intr(void *arg)
1809{
1810 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1811 u_int32_t stat;
1812
1813 if (!(sc->intmask & OHCI_INT_EN)) {
1814 /* polling mode */
1815 return;
1816 }
1817
1818 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) {
1819 if (stat == 0xffffffff) {
1820 device_printf(sc->fc.dev,
1821 "device physically ejected?\n");
1822 return;
1823 }
1824#ifdef ACK_ALL
1825 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1826#endif
1827 fwohci_intr_body(sc, stat, -1);
1828 }
1829}
1830
1831static void
1832fwohci_poll(struct firewire_comm *fc, int quick, int count)
1833{
1834 int s;
1835 u_int32_t stat;
1836 struct fwohci_softc *sc;
1837
1838
1839 sc = (struct fwohci_softc *)fc;
1840 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
1841 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
1842 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
1843#if 0
1844 if (!quick) {
1845#else
1846 if (1) {
1847#endif
1848 stat = OREAD(sc, FWOHCI_INTSTAT);
1849 if (stat == 0)
1850 return;
1851 if (stat == 0xffffffff) {
1852 device_printf(sc->fc.dev,
1853 "device physically ejected?\n");
1854 return;
1855 }
1856#ifdef ACK_ALL
1857 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1858#endif
1859 }
1860 s = splfw();
1861 fwohci_intr_body(sc, stat, count);
1862 splx(s);
1863}
1864
1865static void
1866fwohci_set_intr(struct firewire_comm *fc, int enable)
1867{
1868 struct fwohci_softc *sc;
1869
1870 sc = (struct fwohci_softc *)fc;
1871 if (bootverbose)
1872 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
1873 if (enable) {
1874 sc->intmask |= OHCI_INT_EN;
1875 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1876 } else {
1877 sc->intmask &= ~OHCI_INT_EN;
1878 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1879 }
1880}
1881
1882static void
1883fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
1884{
1885 int stat;
1886 struct firewire_comm *fc = &sc->fc;
1887 struct fw_pkt *fp;
1888 struct fwohci_dbch *dbch;
1889 struct fwohcidb_tr *db_tr;
1890
1891 dbch = &sc->it[dmach];
1892 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){
1893 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start;
1894/*
1895 * Overwrite highest significant 4 bits timestamp information
1896 */
1897 fp = (struct fw_pkt *)db_tr->buf;
1898 fp->mode.ld[2] |= htonl(0x80000000 |
1899 ((fc->cyctimer(fc) + 0x4000) & 0xf000));
1900 }
1901 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f;
1902 switch(stat){
1903 case FWOHCIEV_ACKCOMPL:
1904 fw_tbuf_update(fc, dmach, 1);
1905 break;
1906 default:
1907 fw_tbuf_update(fc, dmach, 0);
1908 break;
1909 }
1910 fwohci_itxbuf_enable(&sc->fc, dmach);
1911}
1912
1913static void
1914fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
1915{
1916 int stat;
1917 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f;
1918 switch(stat){
1919 case FWOHCIEV_ACKCOMPL:
1920 fw_rbuf_update(&sc->fc, dmach, 1);
1921 wakeup(sc->fc.ir[dmach]);
1922 fwohci_irx_enable(&sc->fc, dmach);
1923 break;
1924 default:
| 1545 return err;
1546}
1547
1548static int
1549fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1550{
1551 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1552 int err = 0;
1553
1554 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){
1555 err = fwohci_irxpp_enable(fc, dmach);
1556 return err;
1557 }else{
1558 err = fwohci_irxbuf_enable(fc, dmach);
1559 return err;
1560 }
1561}
1562
1563int
1564fwohci_shutdown(struct fwohci_softc *sc, device_t dev)
1565{
1566 u_int i;
1567
1568/* Now stopping all DMA channel */
1569 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1570 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1571 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1572 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1573
1574 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1575 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1576 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1577 }
1578
1579/* FLUSH FIFO and reset Transmitter/Reciever */
1580 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1581
1582/* Stop interrupt */
1583 OWRITE(sc, FWOHCI_INTMASKCLR,
1584 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1585 | OHCI_INT_PHY_INT
1586 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1587 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1588 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1589 | OHCI_INT_PHY_BUS_R);
1590/* XXX Link down? Bus reset? */
1591 return 0;
1592}
1593
1594int
1595fwohci_resume(struct fwohci_softc *sc, device_t dev)
1596{
1597 int i;
1598
1599 fwohci_reset(sc, dev);
1600 /* XXX resume isochronus receive automatically. (how about TX?) */
1601 for(i = 0; i < sc->fc.nisodma; i ++) {
1602 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) {
1603 device_printf(sc->fc.dev,
1604 "resume iso receive ch: %d\n", i);
1605 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING;
1606 sc->fc.irx_enable(&sc->fc, i);
1607 }
1608 }
1609
1610 bus_generic_resume(dev);
1611 sc->fc.ibr(&sc->fc);
1612 return 0;
1613}
1614
1615#define ACK_ALL
1616static void
1617fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1618{
1619 u_int32_t irstat, itstat;
1620 u_int i;
1621 struct firewire_comm *fc = (struct firewire_comm *)sc;
1622
1623#ifdef OHCI_DEBUG
1624 if(stat & OREAD(sc, FWOHCI_INTMASK))
1625 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1626 stat & OHCI_INT_EN ? "DMA_EN ":"",
1627 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1628 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1629 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1630 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1631 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1632 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1633 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1634 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1635 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1636 stat & OHCI_INT_PHY_SID ? "SID ":"",
1637 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1638 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1639 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1640 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1641 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1642 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1643 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1644 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1645 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1646 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1647 stat, OREAD(sc, FWOHCI_INTMASK)
1648 );
1649#endif
1650/* Bus reset */
1651 if(stat & OHCI_INT_PHY_BUS_R ){
1652 device_printf(fc->dev, "BUS reset\n");
1653 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1654 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1655
1656 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1657 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1658 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1659 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1660
1661#if 0
1662 for( i = 0 ; i < fc->nisodma ; i ++ ){
1663 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1664 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1665 }
1666
1667#endif
1668 fw_busreset(fc);
1669
1670 /* XXX need to wait DMA to stop */
1671#ifndef ACK_ALL
1672 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1673#endif
1674#if 1
1675 /* pending all pre-bus_reset packets */
1676 fwohci_txd(sc, &sc->atrq);
1677 fwohci_txd(sc, &sc->atrs);
1678 fwohci_arcv(sc, &sc->arrs, -1);
1679 fwohci_arcv(sc, &sc->arrq, -1);
1680#endif
1681
1682
1683 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1684 /* XXX insecure ?? */
1685 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1686 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1687 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1688
1689 }
1690 if((stat & OHCI_INT_DMA_IR )){
1691#ifndef ACK_ALL
1692 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1693#endif
1694 irstat = OREAD(sc, OHCI_IR_STAT);
1695 OWRITE(sc, OHCI_IR_STATCLR, ~0);
1696 for(i = 0; i < fc->nisodma ; i++){
1697 if((irstat & (1 << i)) != 0){
1698 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){
1699 fwohci_ircv(sc, &sc->ir[i], count);
1700 }else{
1701 fwohci_rbuf_update(sc, i);
1702 }
1703 }
1704 }
1705 }
1706 if((stat & OHCI_INT_DMA_IT )){
1707#ifndef ACK_ALL
1708 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1709#endif
1710 itstat = OREAD(sc, OHCI_IT_STAT);
1711 OWRITE(sc, OHCI_IT_STATCLR, ~0);
1712 for(i = 0; i < fc->nisodma ; i++){
1713 if((itstat & (1 << i)) != 0){
1714 fwohci_tbuf_update(sc, i);
1715 }
1716 }
1717 }
1718 if((stat & OHCI_INT_DMA_PRRS )){
1719#ifndef ACK_ALL
1720 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1721#endif
1722#if 0
1723 dump_dma(sc, ARRS_CH);
1724 dump_db(sc, ARRS_CH);
1725#endif
1726 fwohci_arcv(sc, &sc->arrs, count);
1727 }
1728 if((stat & OHCI_INT_DMA_PRRQ )){
1729#ifndef ACK_ALL
1730 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1731#endif
1732#if 0
1733 dump_dma(sc, ARRQ_CH);
1734 dump_db(sc, ARRQ_CH);
1735#endif
1736 fwohci_arcv(sc, &sc->arrq, count);
1737 }
1738 if(stat & OHCI_INT_PHY_SID){
1739 caddr_t buf;
1740 int plen;
1741
1742#ifndef ACK_ALL
1743 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1744#endif
1745/*
1746** Checking whether the node is root or not. If root, turn on
1747** cycle master.
1748*/
1749 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID));
1750 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){
1751 printf("Bus reset failure\n");
1752 goto sidout;
1753 }
1754 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){
1755 printf("CYCLEMASTER mode\n");
1756 OWRITE(sc, OHCI_LNKCTL,
1757 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1758 }else{
1759 printf("non CYCLEMASTER mode\n");
1760 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1761 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1762 }
1763 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f;
1764
1765 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK;
1766 plen -= 4; /* chop control info */
1767 buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT);
1768 if(buf == NULL) goto sidout;
1769 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1),
1770 buf, plen);
1771 fw_sidrcv(fc, buf, plen, 0);
1772 }
1773sidout:
1774 if((stat & OHCI_INT_DMA_ATRQ )){
1775#ifndef ACK_ALL
1776 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1777#endif
1778 fwohci_txd(sc, &(sc->atrq));
1779 }
1780 if((stat & OHCI_INT_DMA_ATRS )){
1781#ifndef ACK_ALL
1782 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1783#endif
1784 fwohci_txd(sc, &(sc->atrs));
1785 }
1786 if((stat & OHCI_INT_PW_ERR )){
1787#ifndef ACK_ALL
1788 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1789#endif
1790 device_printf(fc->dev, "posted write error\n");
1791 }
1792 if((stat & OHCI_INT_ERR )){
1793#ifndef ACK_ALL
1794 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1795#endif
1796 device_printf(fc->dev, "unrecoverable error\n");
1797 }
1798 if((stat & OHCI_INT_PHY_INT)) {
1799#ifndef ACK_ALL
1800 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1801#endif
1802 device_printf(fc->dev, "phy int\n");
1803 }
1804
1805 return;
1806}
1807
1808void
1809fwohci_intr(void *arg)
1810{
1811 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1812 u_int32_t stat;
1813
1814 if (!(sc->intmask & OHCI_INT_EN)) {
1815 /* polling mode */
1816 return;
1817 }
1818
1819 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) {
1820 if (stat == 0xffffffff) {
1821 device_printf(sc->fc.dev,
1822 "device physically ejected?\n");
1823 return;
1824 }
1825#ifdef ACK_ALL
1826 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1827#endif
1828 fwohci_intr_body(sc, stat, -1);
1829 }
1830}
1831
1832static void
1833fwohci_poll(struct firewire_comm *fc, int quick, int count)
1834{
1835 int s;
1836 u_int32_t stat;
1837 struct fwohci_softc *sc;
1838
1839
1840 sc = (struct fwohci_softc *)fc;
1841 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
1842 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
1843 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
1844#if 0
1845 if (!quick) {
1846#else
1847 if (1) {
1848#endif
1849 stat = OREAD(sc, FWOHCI_INTSTAT);
1850 if (stat == 0)
1851 return;
1852 if (stat == 0xffffffff) {
1853 device_printf(sc->fc.dev,
1854 "device physically ejected?\n");
1855 return;
1856 }
1857#ifdef ACK_ALL
1858 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1859#endif
1860 }
1861 s = splfw();
1862 fwohci_intr_body(sc, stat, count);
1863 splx(s);
1864}
1865
1866static void
1867fwohci_set_intr(struct firewire_comm *fc, int enable)
1868{
1869 struct fwohci_softc *sc;
1870
1871 sc = (struct fwohci_softc *)fc;
1872 if (bootverbose)
1873 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
1874 if (enable) {
1875 sc->intmask |= OHCI_INT_EN;
1876 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
1877 } else {
1878 sc->intmask &= ~OHCI_INT_EN;
1879 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
1880 }
1881}
1882
1883static void
1884fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
1885{
1886 int stat;
1887 struct firewire_comm *fc = &sc->fc;
1888 struct fw_pkt *fp;
1889 struct fwohci_dbch *dbch;
1890 struct fwohcidb_tr *db_tr;
1891
1892 dbch = &sc->it[dmach];
1893 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){
1894 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start;
1895/*
1896 * Overwrite highest significant 4 bits timestamp information
1897 */
1898 fp = (struct fw_pkt *)db_tr->buf;
1899 fp->mode.ld[2] |= htonl(0x80000000 |
1900 ((fc->cyctimer(fc) + 0x4000) & 0xf000));
1901 }
1902 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f;
1903 switch(stat){
1904 case FWOHCIEV_ACKCOMPL:
1905 fw_tbuf_update(fc, dmach, 1);
1906 break;
1907 default:
1908 fw_tbuf_update(fc, dmach, 0);
1909 break;
1910 }
1911 fwohci_itxbuf_enable(&sc->fc, dmach);
1912}
1913
1914static void
1915fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
1916{
1917 int stat;
1918 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f;
1919 switch(stat){
1920 case FWOHCIEV_ACKCOMPL:
1921 fw_rbuf_update(&sc->fc, dmach, 1);
1922 wakeup(sc->fc.ir[dmach]);
1923 fwohci_irx_enable(&sc->fc, dmach);
1924 break;
1925 default:
|
1925 break;
1926 }
1927}
1928
1929void
1930dump_dma(struct fwohci_softc *sc, u_int32_t ch)
1931{
1932 u_int32_t off, cntl, stat, cmd, match;
1933
1934 if(ch == 0){
1935 off = OHCI_ATQOFF;
1936 }else if(ch == 1){
1937 off = OHCI_ATSOFF;
1938 }else if(ch == 2){
1939 off = OHCI_ARQOFF;
1940 }else if(ch == 3){
1941 off = OHCI_ARSOFF;
1942 }else if(ch < IRX_CH){
1943 off = OHCI_ITCTL(ch - ITX_CH);
1944 }else{
1945 off = OHCI_IRCTL(ch - IRX_CH);
1946 }
1947 cntl = stat = OREAD(sc, off);
1948 cmd = OREAD(sc, off + 0xc);
1949 match = OREAD(sc, off + 0x10);
1950
1951 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n",
1952 ch,
1953 cntl,
1954 stat,
1955 cmd,
1956 match);
1957 stat &= 0xffff ;
1958 if(stat & 0xff00){
1959 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
1960 ch,
1961 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
1962 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
1963 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
1964 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
1965 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
1966 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
1967 fwohcicode[stat & 0x1f],
1968 stat & 0x1f
1969 );
1970 }else{
1971 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
1972 }
1973}
1974
1975void
1976dump_db(struct fwohci_softc *sc, u_int32_t ch)
1977{
1978 struct fwohci_dbch *dbch;
1979 struct fwohcidb_tr *cp = NULL, *pp, *np;
1980 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL;
1981 int idb, jdb;
1982 u_int32_t cmd, off;
1983 if(ch == 0){
1984 off = OHCI_ATQOFF;
1985 dbch = &sc->atrq;
1986 }else if(ch == 1){
1987 off = OHCI_ATSOFF;
1988 dbch = &sc->atrs;
1989 }else if(ch == 2){
1990 off = OHCI_ARQOFF;
1991 dbch = &sc->arrq;
1992 }else if(ch == 3){
1993 off = OHCI_ARSOFF;
1994 dbch = &sc->arrs;
1995 }else if(ch < IRX_CH){
1996 off = OHCI_ITCTL(ch - ITX_CH);
1997 dbch = &sc->it[ch - ITX_CH];
1998 }else {
1999 off = OHCI_IRCTL(ch - IRX_CH);
2000 dbch = &sc->ir[ch - IRX_CH];
2001 }
2002 cmd = OREAD(sc, off + 0xc);
2003
2004 if( dbch->ndb == 0 ){
2005 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2006 return;
2007 }
2008 pp = dbch->top;
2009 prev = pp->db;
2010 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2011 if(pp == NULL){
2012 curr = NULL;
2013 goto outdb;
2014 }
2015 cp = STAILQ_NEXT(pp, link);
2016 if(cp == NULL){
2017 curr = NULL;
2018 goto outdb;
2019 }
2020 np = STAILQ_NEXT(cp, link);
2021 if(cp == NULL) break;
2022 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2023 if((cmd & 0xfffffff0)
2024 == vtophys(&(cp->db[jdb]))){
2025 curr = cp->db;
2026 if(np != NULL){
2027 next = np->db;
2028 }else{
2029 next = NULL;
2030 }
2031 goto outdb;
2032 }
2033 }
2034 pp = STAILQ_NEXT(pp, link);
2035 prev = pp->db;
2036 }
2037outdb:
2038 if( curr != NULL){
2039 printf("Prev DB %d\n", ch);
2040 print_db(prev, ch, dbch->ndesc);
2041 printf("Current DB %d\n", ch);
2042 print_db(curr, ch, dbch->ndesc);
2043 printf("Next DB %d\n", ch);
2044 print_db(next, ch, dbch->ndesc);
2045 }else{
2046 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2047 }
2048 return;
2049}
2050
2051void
2052print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max)
2053{
2054 fwohcireg_t stat;
2055 int i, key;
2056
2057 if(db == NULL){
2058 printf("No Descriptor is found\n");
2059 return;
2060 }
2061
2062 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2063 ch,
2064 "Current",
2065 "OP ",
2066 "KEY",
2067 "INT",
2068 "BR ",
2069 "len",
2070 "Addr",
2071 "Depend",
2072 "Stat",
2073 "Cnt");
2074 for( i = 0 ; i <= max ; i ++){
2075 key = db[i].db.desc.cmd & OHCI_KEY_MASK;
2076#if __FreeBSD_version >= 500000
2077 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x",
2078#else
2079 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2080#endif
2081 vtophys(&db[i]),
2082 dbcode[(db[i].db.desc.cmd >> 28) & 0xf],
2083 dbkey[(db[i].db.desc.cmd >> 24) & 0x7],
2084 dbcond[(db[i].db.desc.cmd >> 20) & 0x3],
2085 dbcond[(db[i].db.desc.cmd >> 18) & 0x3],
2086 db[i].db.desc.cmd & 0xffff,
2087 db[i].db.desc.addr,
2088 db[i].db.desc.depend,
2089 db[i].db.desc.status,
2090 db[i].db.desc.count);
2091 stat = db[i].db.desc.status;
2092 if(stat & 0xff00){
2093 printf(" %s%s%s%s%s%s %s(%x)\n",
2094 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2095 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2096 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2097 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2098 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2099 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2100 fwohcicode[stat & 0x1f],
2101 stat & 0x1f
2102 );
2103 }else{
2104 printf(" Nostat\n");
2105 }
2106 if(key == OHCI_KEY_ST2 ){
2107 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2108 db[i+1].db.immed[0],
2109 db[i+1].db.immed[1],
2110 db[i+1].db.immed[2],
2111 db[i+1].db.immed[3]);
2112 }
2113 if(key == OHCI_KEY_DEVICE){
2114 return;
2115 }
2116 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK)
2117 == OHCI_BRANCH_ALWAYS){
2118 return;
2119 }
2120 if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2121 == OHCI_OUTPUT_LAST){
2122 return;
2123 }
2124 if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2125 == OHCI_INPUT_LAST){
2126 return;
2127 }
2128 if(key == OHCI_KEY_ST2 ){
2129 i++;
2130 }
2131 }
2132 return;
2133}
2134
2135void
2136fwohci_ibr(struct firewire_comm *fc)
2137{
2138 struct fwohci_softc *sc;
2139 u_int32_t fun;
2140
2141 sc = (struct fwohci_softc *)fc;
2142
2143 /*
2144 * Set root hold-off bit so that non cyclemaster capable node
2145 * shouldn't became the root node.
2146 */
2147 fun = fwphy_rddata(sc, FW_PHY_RHB_REG);
2148 fun |= FW_PHY_RHB;
2149 fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun);
2150#if 1
2151 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2152 fun |= FW_PHY_IBR;
2153 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2154#else
2155 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2156 fun |= FW_PHY_ISBR;
2157 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2158#endif
2159}
2160
2161void
2162fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2163{
2164 struct fwohcidb_tr *db_tr, *fdb_tr;
2165 struct fwohci_dbch *dbch;
2166 struct fw_pkt *fp;
2167 volatile struct fwohci_txpkthdr *ohcifp;
2168 unsigned short chtag;
2169 int idb;
2170
2171 dbch = &sc->it[dmach];
2172 chtag = sc->it[dmach].xferq.flag & 0xff;
2173
2174 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2175 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2176/*
2177device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db));
2178*/
2179 if(bulkxfer->flag != 0){
2180 return;
2181 }
2182 bulkxfer->flag = 1;
2183 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){
2184 db_tr->db[0].db.desc.cmd
2185 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2186 fp = (struct fw_pkt *)db_tr->buf;
2187 ohcifp = (volatile struct fwohci_txpkthdr *)
2188 db_tr->db[1].db.immed;
2189 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]);
2190 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
2191 ohcifp->mode.stream.chtag = chtag;
2192 ohcifp->mode.stream.tcode = 0xa;
2193 ohcifp->mode.stream.spd = 4;
2194 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]);
2195 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]);
2196
2197 db_tr->db[2].db.desc.cmd
2198 = OHCI_OUTPUT_LAST
2199 | OHCI_UPDATE
2200 | OHCI_BRANCH_ALWAYS
2201 | ((ntohs(fp->mode.stream.len) ) & 0xffff);
2202 db_tr->db[2].db.desc.status = 0;
2203 db_tr->db[2].db.desc.count = 0;
2204 if(dbch->xferq.flag & FWXFERQ_DV){
2205 db_tr->db[0].db.desc.depend
2206 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2207 db_tr->db[dbch->ndesc - 1].db.desc.depend
2208 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2209 }else{
2210 db_tr->db[0].db.desc.depend
2211 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2212 db_tr->db[dbch->ndesc - 1].db.desc.depend
2213 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2214 }
2215 bulkxfer->end = (caddr_t)db_tr;
2216 db_tr = STAILQ_NEXT(db_tr, link);
2217 }
2218 db_tr = (struct fwohcidb_tr *)bulkxfer->end;
2219 db_tr->db[0].db.desc.depend &= ~0xf;
2220 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
2221/**/
2222 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS;
2223 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER;
2224/**/
2225 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS;
2226
2227 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2228 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2229/*
2230device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db));
2231*/
2232 return;
2233}
2234
2235static int
2236fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size,
2237 int mode, void *buf)
2238{
2239 volatile struct fwohcidb *db = db_tr->db;
2240 int err = 0;
2241 if(buf == 0){
2242 err = EINVAL;
2243 return err;
2244 }
2245 db_tr->buf = buf;
2246 db_tr->dbcnt = 3;
2247 db_tr->dummy = NULL;
2248
2249 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2250
2251 db[2].db.desc.depend = 0;
2252 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t);
2253 db[2].db.desc.cmd = OHCI_OUTPUT_MORE;
2254
2255 db[0].db.desc.status = 0;
2256 db[0].db.desc.count = 0;
2257
2258 db[2].db.desc.status = 0;
2259 db[2].db.desc.count = 0;
2260 if( mode & FWXFERQ_STREAM ){
2261 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST;
2262 if(mode & FWXFERQ_PACKET ){
2263 db[2].db.desc.cmd
2264 |= OHCI_INTERRUPT_ALWAYS;
2265 }
2266 }
2267 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2268 return 1;
2269}
2270
2271int
2272fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode,
2273 void *buf, void *dummy)
2274{
2275 volatile struct fwohcidb *db = db_tr->db;
2276 int i;
2277 void *dbuf[2];
2278 int dsiz[2];
2279
2280 if(buf == 0){
2281 buf = malloc(size, M_DEVBUF, M_NOWAIT);
2282 if(buf == NULL) return 0;
2283 db_tr->buf = buf;
2284 db_tr->dbcnt = 1;
2285 db_tr->dummy = NULL;
2286 dsiz[0] = size;
2287 dbuf[0] = buf;
2288 }else if(dummy == NULL){
2289 db_tr->buf = buf;
2290 db_tr->dbcnt = 1;
2291 db_tr->dummy = NULL;
2292 dsiz[0] = size;
2293 dbuf[0] = buf;
2294 }else{
2295 db_tr->buf = buf;
2296 db_tr->dbcnt = 2;
2297 db_tr->dummy = dummy;
2298 dsiz[0] = sizeof(u_int32_t);
2299 dsiz[1] = size;
2300 dbuf[0] = dummy;
2301 dbuf[1] = buf;
2302 }
2303 for(i = 0 ; i < db_tr->dbcnt ; i++){
2304 db[i].db.desc.addr = vtophys(dbuf[i]) ;
2305 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i];
2306 if( mode & FWXFERQ_STREAM ){
2307 db[i].db.desc.cmd |= OHCI_UPDATE;
2308 }
2309 db[i].db.desc.status = 0;
2310 db[i].db.desc.count = dsiz[i];
2311 }
2312 if( mode & FWXFERQ_STREAM ){
2313 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST;
2314 if(mode & FWXFERQ_PACKET ){
2315 db[db_tr->dbcnt - 1].db.desc.cmd
2316 |= OHCI_INTERRUPT_ALWAYS;
2317 }
2318 }
2319 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2320 return 1;
2321}
2322
2323static void
2324fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2325{
2326 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr;
2327 struct firewire_comm *fc = (struct firewire_comm *)sc;
2328 int z = 1;
2329 struct fw_pkt *fp;
2330 u_int8_t *ld;
2331 u_int32_t off = NULL;
2332 u_int32_t stat;
2333 u_int32_t *qld;
2334 u_int32_t reg;
2335 u_int spd;
2336 u_int dmach;
2337 int len, i, plen;
2338 caddr_t buf;
2339
2340 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
2341 if( &sc->ir[dmach] == dbch){
2342 off = OHCI_IROFF(dmach);
2343 break;
2344 }
2345 }
2346 if(off == NULL){
2347 return;
2348 }
2349 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){
2350 fwohci_irx_disable(&sc->fc, dmach);
2351 return;
2352 }
2353
2354 odb_tr = NULL;
2355 db_tr = dbch->top;
2356 i = 0;
2357 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) {
2358 if (count >= 0 && count-- == 0)
2359 break;
2360 ld = (u_int8_t *)db_tr->buf;
2361 if (dbch->xferq.flag & FWXFERQ_PACKET) {
2362 /* skip timeStamp */
2363 ld += sizeof(struct fwohci_trailer);
2364 }
2365 qld = (u_int32_t *)ld;
2366 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count);
2367/*
2368{
2369device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len,
2370 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]);
2371}
2372*/
2373 fp=(struct fw_pkt *)ld;
2374 qld[0] = htonl(qld[0]);
2375 plen = sizeof(struct fw_isohdr)
2376 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t);
2377 ld += plen;
2378 len -= plen;
2379 buf = db_tr->buf;
2380 db_tr->buf = NULL;
2381 stat = reg & 0x1f;
2382 spd = reg & 0x3;
2383 switch(stat){
2384 case FWOHCIEV_ACKCOMPL:
2385 case FWOHCIEV_ACKPEND:
2386 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd);
2387 break;
2388 default:
2389 free(buf, M_DEVBUF);
2390 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat);
2391 break;
2392 }
2393 i++;
2394 fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2395 dbch->xferq.flag, 0, NULL);
2396 db_tr->db[0].db.desc.depend &= ~0xf;
2397 if(dbch->pdb_tr != NULL){
2398 dbch->pdb_tr->db[0].db.desc.depend |= z;
2399 } else {
2400 /* XXX should be rewritten in better way */
2401 dbch->bottom->db[0].db.desc.depend |= z;
2402 }
2403 dbch->pdb_tr = db_tr;
2404 db_tr = STAILQ_NEXT(db_tr, link);
2405 }
2406 dbch->top = db_tr;
2407 reg = OREAD(sc, OHCI_DMACTL(off));
2408 if (reg & OHCI_CNTL_DMA_ACTIVE)
2409 return;
2410 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n",
2411 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i);
2412 dbch->top = db_tr;
2413 fwohci_irx_enable(fc, dmach);
2414}
2415
2416#define PLEN(x) (((ntohs(x))+0x3) & ~0x3)
2417static int
2418fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen)
2419{
2420 int i;
2421
2422 for( i = 4; i < hlen ; i+=4){
2423 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]);
2424 }
2425
2426 switch(fp->mode.common.tcode){
2427 case FWTCODE_RREQQ:
2428 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t);
2429 case FWTCODE_WRES:
2430 return sizeof(fp->mode.wres) + sizeof(u_int32_t);
2431 case FWTCODE_WREQQ:
2432 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t);
2433 case FWTCODE_RREQB:
2434 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t);
2435 case FWTCODE_RRESQ:
2436 return sizeof(fp->mode.rresq) + sizeof(u_int32_t);
2437 case FWTCODE_WREQB:
2438 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len)
2439 + sizeof(u_int32_t);
2440 case FWTCODE_LREQ:
2441 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len)
2442 + sizeof(u_int32_t);
2443 case FWTCODE_RRESB:
2444 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len)
2445 + sizeof(u_int32_t);
2446 case FWTCODE_LRES:
2447 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len)
2448 + sizeof(u_int32_t);
2449 case FWOHCITCODE_PHY:
2450 return 16;
2451 }
2452 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2453 return 0;
2454}
2455
2456static void
2457fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2458{
2459 struct fwohcidb_tr *db_tr;
2460 int z = 1;
2461 struct fw_pkt *fp;
2462 u_int8_t *ld;
2463 u_int32_t stat, off;
2464 u_int spd;
2465 int len, plen, hlen, pcnt, poff = 0, rlen;
2466 int s;
2467 caddr_t buf;
2468 int resCount;
2469
2470 if(&sc->arrq == dbch){
2471 off = OHCI_ARQOFF;
2472 }else if(&sc->arrs == dbch){
2473 off = OHCI_ARSOFF;
2474 }else{
2475 return;
2476 }
2477
2478 s = splfw();
2479 db_tr = dbch->top;
2480 pcnt = 0;
2481 /* XXX we cannot handle a packet which lies in more than two buf */
2482 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) {
2483 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset;
2484 resCount = db_tr->db[0].db.desc.count;
2485 len = dbch->xferq.psize - resCount
2486 - dbch->buf_offset;
2487 while (len > 0 ) {
2488 if (count >= 0 && count-- == 0)
2489 goto out;
2490 if(dbch->frag.buf != NULL){
2491 buf = dbch->frag.buf;
2492 if (dbch->frag.plen < 0) {
2493 /* incomplete header */
2494 int hlen;
2495
2496 hlen = - dbch->frag.plen;
2497 rlen = hlen - dbch->frag.len;
2498 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen);
2499 ld += rlen;
2500 len -= rlen;
2501 dbch->frag.len += rlen;
2502#if 0
2503 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2504#endif
2505 fp=(struct fw_pkt *)dbch->frag.buf;
2506 dbch->frag.plen
2507 = fwohci_get_plen(sc, fp, hlen);
2508 if (dbch->frag.plen == 0)
2509 goto out;
2510 }
2511 rlen = dbch->frag.plen - dbch->frag.len;
2512#if 0
2513 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2514#endif
2515 bcopy(ld, dbch->frag.buf + dbch->frag.len,
2516 rlen);
2517 ld += rlen;
2518 len -= rlen;
2519 plen = dbch->frag.plen;
2520 dbch->frag.buf = NULL;
2521 dbch->frag.plen = 0;
2522 dbch->frag.len = 0;
2523 poff = 0;
2524 }else{
2525 fp=(struct fw_pkt *)ld;
2526 fp->mode.ld[0] = htonl(fp->mode.ld[0]);
2527 switch(fp->mode.common.tcode){
2528 case FWTCODE_RREQQ:
2529 case FWTCODE_WRES:
2530 case FWTCODE_WREQQ:
2531 case FWTCODE_RRESQ:
2532 case FWOHCITCODE_PHY:
2533 hlen = 12;
2534 break;
2535 case FWTCODE_RREQB:
2536 case FWTCODE_WREQB:
2537 case FWTCODE_LREQ:
2538 case FWTCODE_RRESB:
2539 case FWTCODE_LRES:
2540 hlen = 16;
2541 break;
2542 default:
2543 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2544 goto out;
2545 }
2546 if (len >= hlen) {
2547 plen = fwohci_get_plen(sc, fp, hlen);
2548 if (plen == 0)
2549 goto out;
2550 plen = (plen + 3) & ~3;
2551 len -= plen;
2552 } else {
2553 plen = -hlen;
2554 len -= hlen;
2555 }
2556 if(resCount > 0 || len > 0){
2557 buf = malloc( dbch->xferq.psize,
2558 M_DEVBUF, M_NOWAIT);
2559 if(buf == NULL){
2560 printf("cannot malloc!\n");
2561 free(db_tr->buf, M_DEVBUF);
2562 goto out;
2563 }
2564 bcopy(ld, buf, plen);
2565 poff = 0;
2566 dbch->frag.buf = NULL;
2567 dbch->frag.plen = 0;
2568 dbch->frag.len = 0;
2569 }else if(len < 0){
2570 dbch->frag.buf = db_tr->buf;
2571 if (plen < 0) {
2572#if 0
2573 printf("plen < 0:"
2574 "hlen: %d len: %d\n",
2575 hlen, len);
2576#endif
2577 dbch->frag.len = hlen + len;
2578 dbch->frag.plen = -hlen;
2579 } else {
2580 dbch->frag.len = plen + len;
2581 dbch->frag.plen = plen;
2582 }
2583 bcopy(ld, db_tr->buf, dbch->frag.len);
2584 buf = NULL;
2585 }else{
2586 buf = db_tr->buf;
2587 poff = ld - (u_int8_t *)buf;
2588 dbch->frag.buf = NULL;
2589 dbch->frag.plen = 0;
2590 dbch->frag.len = 0;
2591 }
2592 ld += plen;
2593 }
2594 if( buf != NULL){
2595/* DMA result-code will be written at the tail of packet */
2596 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2597 spd = (stat >> 5) & 0x3;
2598 stat &= 0x1f;
2599 switch(stat){
2600 case FWOHCIEV_ACKPEND:
2601#if 0
2602 printf("fwohci_arcv: ack pending..\n");
2603#endif
2604 /* fall through */
2605 case FWOHCIEV_ACKCOMPL:
2606 if( poff != 0 )
2607 bcopy(buf+poff, buf, plen - 4);
2608 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd);
2609 break;
2610 case FWOHCIEV_BUSRST:
2611 free(buf, M_DEVBUF);
2612 if (sc->fc.status != FWBUSRESET)
2613 printf("got BUSRST packet!?\n");
2614 break;
2615 default:
2616 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2617#if 0 /* XXX */
2618 goto out;
2619#endif
2620 break;
2621 }
2622 }
2623 pcnt ++;
2624 };
2625out:
2626 if (resCount == 0) {
2627 /* done on this buffer */
2628 fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2629 dbch->xferq.flag, 0, NULL);
2630 dbch->bottom->db[0].db.desc.depend |= z;
2631 dbch->bottom = db_tr;
2632 db_tr = STAILQ_NEXT(db_tr, link);
2633 dbch->top = db_tr;
2634 dbch->buf_offset = 0;
2635 } else {
2636 dbch->buf_offset = dbch->xferq.psize - resCount;
2637 break;
2638 }
2639 /* XXX make sure DMA is not dead */
2640 }
2641#if 0
2642 if (pcnt < 1)
2643 printf("fwohci_arcv: no packets\n");
2644#endif
2645 splx(s);
2646}
| 1927 break;
1928 }
1929}
1930
1931void
1932dump_dma(struct fwohci_softc *sc, u_int32_t ch)
1933{
1934 u_int32_t off, cntl, stat, cmd, match;
1935
1936 if(ch == 0){
1937 off = OHCI_ATQOFF;
1938 }else if(ch == 1){
1939 off = OHCI_ATSOFF;
1940 }else if(ch == 2){
1941 off = OHCI_ARQOFF;
1942 }else if(ch == 3){
1943 off = OHCI_ARSOFF;
1944 }else if(ch < IRX_CH){
1945 off = OHCI_ITCTL(ch - ITX_CH);
1946 }else{
1947 off = OHCI_IRCTL(ch - IRX_CH);
1948 }
1949 cntl = stat = OREAD(sc, off);
1950 cmd = OREAD(sc, off + 0xc);
1951 match = OREAD(sc, off + 0x10);
1952
1953 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n",
1954 ch,
1955 cntl,
1956 stat,
1957 cmd,
1958 match);
1959 stat &= 0xffff ;
1960 if(stat & 0xff00){
1961 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
1962 ch,
1963 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
1964 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
1965 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
1966 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
1967 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
1968 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
1969 fwohcicode[stat & 0x1f],
1970 stat & 0x1f
1971 );
1972 }else{
1973 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
1974 }
1975}
1976
1977void
1978dump_db(struct fwohci_softc *sc, u_int32_t ch)
1979{
1980 struct fwohci_dbch *dbch;
1981 struct fwohcidb_tr *cp = NULL, *pp, *np;
1982 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL;
1983 int idb, jdb;
1984 u_int32_t cmd, off;
1985 if(ch == 0){
1986 off = OHCI_ATQOFF;
1987 dbch = &sc->atrq;
1988 }else if(ch == 1){
1989 off = OHCI_ATSOFF;
1990 dbch = &sc->atrs;
1991 }else if(ch == 2){
1992 off = OHCI_ARQOFF;
1993 dbch = &sc->arrq;
1994 }else if(ch == 3){
1995 off = OHCI_ARSOFF;
1996 dbch = &sc->arrs;
1997 }else if(ch < IRX_CH){
1998 off = OHCI_ITCTL(ch - ITX_CH);
1999 dbch = &sc->it[ch - ITX_CH];
2000 }else {
2001 off = OHCI_IRCTL(ch - IRX_CH);
2002 dbch = &sc->ir[ch - IRX_CH];
2003 }
2004 cmd = OREAD(sc, off + 0xc);
2005
2006 if( dbch->ndb == 0 ){
2007 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2008 return;
2009 }
2010 pp = dbch->top;
2011 prev = pp->db;
2012 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2013 if(pp == NULL){
2014 curr = NULL;
2015 goto outdb;
2016 }
2017 cp = STAILQ_NEXT(pp, link);
2018 if(cp == NULL){
2019 curr = NULL;
2020 goto outdb;
2021 }
2022 np = STAILQ_NEXT(cp, link);
2023 if(cp == NULL) break;
2024 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2025 if((cmd & 0xfffffff0)
2026 == vtophys(&(cp->db[jdb]))){
2027 curr = cp->db;
2028 if(np != NULL){
2029 next = np->db;
2030 }else{
2031 next = NULL;
2032 }
2033 goto outdb;
2034 }
2035 }
2036 pp = STAILQ_NEXT(pp, link);
2037 prev = pp->db;
2038 }
2039outdb:
2040 if( curr != NULL){
2041 printf("Prev DB %d\n", ch);
2042 print_db(prev, ch, dbch->ndesc);
2043 printf("Current DB %d\n", ch);
2044 print_db(curr, ch, dbch->ndesc);
2045 printf("Next DB %d\n", ch);
2046 print_db(next, ch, dbch->ndesc);
2047 }else{
2048 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2049 }
2050 return;
2051}
2052
2053void
2054print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max)
2055{
2056 fwohcireg_t stat;
2057 int i, key;
2058
2059 if(db == NULL){
2060 printf("No Descriptor is found\n");
2061 return;
2062 }
2063
2064 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2065 ch,
2066 "Current",
2067 "OP ",
2068 "KEY",
2069 "INT",
2070 "BR ",
2071 "len",
2072 "Addr",
2073 "Depend",
2074 "Stat",
2075 "Cnt");
2076 for( i = 0 ; i <= max ; i ++){
2077 key = db[i].db.desc.cmd & OHCI_KEY_MASK;
2078#if __FreeBSD_version >= 500000
2079 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x",
2080#else
2081 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2082#endif
2083 vtophys(&db[i]),
2084 dbcode[(db[i].db.desc.cmd >> 28) & 0xf],
2085 dbkey[(db[i].db.desc.cmd >> 24) & 0x7],
2086 dbcond[(db[i].db.desc.cmd >> 20) & 0x3],
2087 dbcond[(db[i].db.desc.cmd >> 18) & 0x3],
2088 db[i].db.desc.cmd & 0xffff,
2089 db[i].db.desc.addr,
2090 db[i].db.desc.depend,
2091 db[i].db.desc.status,
2092 db[i].db.desc.count);
2093 stat = db[i].db.desc.status;
2094 if(stat & 0xff00){
2095 printf(" %s%s%s%s%s%s %s(%x)\n",
2096 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2097 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2098 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2099 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2100 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2101 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2102 fwohcicode[stat & 0x1f],
2103 stat & 0x1f
2104 );
2105 }else{
2106 printf(" Nostat\n");
2107 }
2108 if(key == OHCI_KEY_ST2 ){
2109 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2110 db[i+1].db.immed[0],
2111 db[i+1].db.immed[1],
2112 db[i+1].db.immed[2],
2113 db[i+1].db.immed[3]);
2114 }
2115 if(key == OHCI_KEY_DEVICE){
2116 return;
2117 }
2118 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK)
2119 == OHCI_BRANCH_ALWAYS){
2120 return;
2121 }
2122 if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2123 == OHCI_OUTPUT_LAST){
2124 return;
2125 }
2126 if((db[i].db.desc.cmd & OHCI_CMD_MASK)
2127 == OHCI_INPUT_LAST){
2128 return;
2129 }
2130 if(key == OHCI_KEY_ST2 ){
2131 i++;
2132 }
2133 }
2134 return;
2135}
2136
2137void
2138fwohci_ibr(struct firewire_comm *fc)
2139{
2140 struct fwohci_softc *sc;
2141 u_int32_t fun;
2142
2143 sc = (struct fwohci_softc *)fc;
2144
2145 /*
2146 * Set root hold-off bit so that non cyclemaster capable node
2147 * shouldn't became the root node.
2148 */
2149 fun = fwphy_rddata(sc, FW_PHY_RHB_REG);
2150 fun |= FW_PHY_RHB;
2151 fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun);
2152#if 1
2153 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2154 fun |= FW_PHY_IBR;
2155 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2156#else
2157 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2158 fun |= FW_PHY_ISBR;
2159 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2160#endif
2161}
2162
2163void
2164fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2165{
2166 struct fwohcidb_tr *db_tr, *fdb_tr;
2167 struct fwohci_dbch *dbch;
2168 struct fw_pkt *fp;
2169 volatile struct fwohci_txpkthdr *ohcifp;
2170 unsigned short chtag;
2171 int idb;
2172
2173 dbch = &sc->it[dmach];
2174 chtag = sc->it[dmach].xferq.flag & 0xff;
2175
2176 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2177 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2178/*
2179device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db));
2180*/
2181 if(bulkxfer->flag != 0){
2182 return;
2183 }
2184 bulkxfer->flag = 1;
2185 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){
2186 db_tr->db[0].db.desc.cmd
2187 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2188 fp = (struct fw_pkt *)db_tr->buf;
2189 ohcifp = (volatile struct fwohci_txpkthdr *)
2190 db_tr->db[1].db.immed;
2191 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]);
2192 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len);
2193 ohcifp->mode.stream.chtag = chtag;
2194 ohcifp->mode.stream.tcode = 0xa;
2195 ohcifp->mode.stream.spd = 4;
2196 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]);
2197 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]);
2198
2199 db_tr->db[2].db.desc.cmd
2200 = OHCI_OUTPUT_LAST
2201 | OHCI_UPDATE
2202 | OHCI_BRANCH_ALWAYS
2203 | ((ntohs(fp->mode.stream.len) ) & 0xffff);
2204 db_tr->db[2].db.desc.status = 0;
2205 db_tr->db[2].db.desc.count = 0;
2206 if(dbch->xferq.flag & FWXFERQ_DV){
2207 db_tr->db[0].db.desc.depend
2208 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2209 db_tr->db[dbch->ndesc - 1].db.desc.depend
2210 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2211 }else{
2212 db_tr->db[0].db.desc.depend
2213 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2214 db_tr->db[dbch->ndesc - 1].db.desc.depend
2215 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc;
2216 }
2217 bulkxfer->end = (caddr_t)db_tr;
2218 db_tr = STAILQ_NEXT(db_tr, link);
2219 }
2220 db_tr = (struct fwohcidb_tr *)bulkxfer->end;
2221 db_tr->db[0].db.desc.depend &= ~0xf;
2222 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
2223/**/
2224 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS;
2225 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER;
2226/**/
2227 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS;
2228
2229 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2230 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2231/*
2232device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db));
2233*/
2234 return;
2235}
2236
2237static int
2238fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size,
2239 int mode, void *buf)
2240{
2241 volatile struct fwohcidb *db = db_tr->db;
2242 int err = 0;
2243 if(buf == 0){
2244 err = EINVAL;
2245 return err;
2246 }
2247 db_tr->buf = buf;
2248 db_tr->dbcnt = 3;
2249 db_tr->dummy = NULL;
2250
2251 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8;
2252
2253 db[2].db.desc.depend = 0;
2254 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t);
2255 db[2].db.desc.cmd = OHCI_OUTPUT_MORE;
2256
2257 db[0].db.desc.status = 0;
2258 db[0].db.desc.count = 0;
2259
2260 db[2].db.desc.status = 0;
2261 db[2].db.desc.count = 0;
2262 if( mode & FWXFERQ_STREAM ){
2263 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST;
2264 if(mode & FWXFERQ_PACKET ){
2265 db[2].db.desc.cmd
2266 |= OHCI_INTERRUPT_ALWAYS;
2267 }
2268 }
2269 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2270 return 1;
2271}
2272
2273int
2274fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode,
2275 void *buf, void *dummy)
2276{
2277 volatile struct fwohcidb *db = db_tr->db;
2278 int i;
2279 void *dbuf[2];
2280 int dsiz[2];
2281
2282 if(buf == 0){
2283 buf = malloc(size, M_DEVBUF, M_NOWAIT);
2284 if(buf == NULL) return 0;
2285 db_tr->buf = buf;
2286 db_tr->dbcnt = 1;
2287 db_tr->dummy = NULL;
2288 dsiz[0] = size;
2289 dbuf[0] = buf;
2290 }else if(dummy == NULL){
2291 db_tr->buf = buf;
2292 db_tr->dbcnt = 1;
2293 db_tr->dummy = NULL;
2294 dsiz[0] = size;
2295 dbuf[0] = buf;
2296 }else{
2297 db_tr->buf = buf;
2298 db_tr->dbcnt = 2;
2299 db_tr->dummy = dummy;
2300 dsiz[0] = sizeof(u_int32_t);
2301 dsiz[1] = size;
2302 dbuf[0] = dummy;
2303 dbuf[1] = buf;
2304 }
2305 for(i = 0 ; i < db_tr->dbcnt ; i++){
2306 db[i].db.desc.addr = vtophys(dbuf[i]) ;
2307 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i];
2308 if( mode & FWXFERQ_STREAM ){
2309 db[i].db.desc.cmd |= OHCI_UPDATE;
2310 }
2311 db[i].db.desc.status = 0;
2312 db[i].db.desc.count = dsiz[i];
2313 }
2314 if( mode & FWXFERQ_STREAM ){
2315 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST;
2316 if(mode & FWXFERQ_PACKET ){
2317 db[db_tr->dbcnt - 1].db.desc.cmd
2318 |= OHCI_INTERRUPT_ALWAYS;
2319 }
2320 }
2321 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS;
2322 return 1;
2323}
2324
2325static void
2326fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2327{
2328 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr;
2329 struct firewire_comm *fc = (struct firewire_comm *)sc;
2330 int z = 1;
2331 struct fw_pkt *fp;
2332 u_int8_t *ld;
2333 u_int32_t off = NULL;
2334 u_int32_t stat;
2335 u_int32_t *qld;
2336 u_int32_t reg;
2337 u_int spd;
2338 u_int dmach;
2339 int len, i, plen;
2340 caddr_t buf;
2341
2342 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
2343 if( &sc->ir[dmach] == dbch){
2344 off = OHCI_IROFF(dmach);
2345 break;
2346 }
2347 }
2348 if(off == NULL){
2349 return;
2350 }
2351 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){
2352 fwohci_irx_disable(&sc->fc, dmach);
2353 return;
2354 }
2355
2356 odb_tr = NULL;
2357 db_tr = dbch->top;
2358 i = 0;
2359 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) {
2360 if (count >= 0 && count-- == 0)
2361 break;
2362 ld = (u_int8_t *)db_tr->buf;
2363 if (dbch->xferq.flag & FWXFERQ_PACKET) {
2364 /* skip timeStamp */
2365 ld += sizeof(struct fwohci_trailer);
2366 }
2367 qld = (u_int32_t *)ld;
2368 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count);
2369/*
2370{
2371device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len,
2372 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]);
2373}
2374*/
2375 fp=(struct fw_pkt *)ld;
2376 qld[0] = htonl(qld[0]);
2377 plen = sizeof(struct fw_isohdr)
2378 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t);
2379 ld += plen;
2380 len -= plen;
2381 buf = db_tr->buf;
2382 db_tr->buf = NULL;
2383 stat = reg & 0x1f;
2384 spd = reg & 0x3;
2385 switch(stat){
2386 case FWOHCIEV_ACKCOMPL:
2387 case FWOHCIEV_ACKPEND:
2388 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd);
2389 break;
2390 default:
2391 free(buf, M_DEVBUF);
2392 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat);
2393 break;
2394 }
2395 i++;
2396 fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2397 dbch->xferq.flag, 0, NULL);
2398 db_tr->db[0].db.desc.depend &= ~0xf;
2399 if(dbch->pdb_tr != NULL){
2400 dbch->pdb_tr->db[0].db.desc.depend |= z;
2401 } else {
2402 /* XXX should be rewritten in better way */
2403 dbch->bottom->db[0].db.desc.depend |= z;
2404 }
2405 dbch->pdb_tr = db_tr;
2406 db_tr = STAILQ_NEXT(db_tr, link);
2407 }
2408 dbch->top = db_tr;
2409 reg = OREAD(sc, OHCI_DMACTL(off));
2410 if (reg & OHCI_CNTL_DMA_ACTIVE)
2411 return;
2412 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n",
2413 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i);
2414 dbch->top = db_tr;
2415 fwohci_irx_enable(fc, dmach);
2416}
2417
2418#define PLEN(x) (((ntohs(x))+0x3) & ~0x3)
2419static int
2420fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen)
2421{
2422 int i;
2423
2424 for( i = 4; i < hlen ; i+=4){
2425 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]);
2426 }
2427
2428 switch(fp->mode.common.tcode){
2429 case FWTCODE_RREQQ:
2430 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t);
2431 case FWTCODE_WRES:
2432 return sizeof(fp->mode.wres) + sizeof(u_int32_t);
2433 case FWTCODE_WREQQ:
2434 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t);
2435 case FWTCODE_RREQB:
2436 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t);
2437 case FWTCODE_RRESQ:
2438 return sizeof(fp->mode.rresq) + sizeof(u_int32_t);
2439 case FWTCODE_WREQB:
2440 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len)
2441 + sizeof(u_int32_t);
2442 case FWTCODE_LREQ:
2443 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len)
2444 + sizeof(u_int32_t);
2445 case FWTCODE_RRESB:
2446 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len)
2447 + sizeof(u_int32_t);
2448 case FWTCODE_LRES:
2449 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len)
2450 + sizeof(u_int32_t);
2451 case FWOHCITCODE_PHY:
2452 return 16;
2453 }
2454 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2455 return 0;
2456}
2457
2458static void
2459fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2460{
2461 struct fwohcidb_tr *db_tr;
2462 int z = 1;
2463 struct fw_pkt *fp;
2464 u_int8_t *ld;
2465 u_int32_t stat, off;
2466 u_int spd;
2467 int len, plen, hlen, pcnt, poff = 0, rlen;
2468 int s;
2469 caddr_t buf;
2470 int resCount;
2471
2472 if(&sc->arrq == dbch){
2473 off = OHCI_ARQOFF;
2474 }else if(&sc->arrs == dbch){
2475 off = OHCI_ARSOFF;
2476 }else{
2477 return;
2478 }
2479
2480 s = splfw();
2481 db_tr = dbch->top;
2482 pcnt = 0;
2483 /* XXX we cannot handle a packet which lies in more than two buf */
2484 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) {
2485 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset;
2486 resCount = db_tr->db[0].db.desc.count;
2487 len = dbch->xferq.psize - resCount
2488 - dbch->buf_offset;
2489 while (len > 0 ) {
2490 if (count >= 0 && count-- == 0)
2491 goto out;
2492 if(dbch->frag.buf != NULL){
2493 buf = dbch->frag.buf;
2494 if (dbch->frag.plen < 0) {
2495 /* incomplete header */
2496 int hlen;
2497
2498 hlen = - dbch->frag.plen;
2499 rlen = hlen - dbch->frag.len;
2500 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen);
2501 ld += rlen;
2502 len -= rlen;
2503 dbch->frag.len += rlen;
2504#if 0
2505 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2506#endif
2507 fp=(struct fw_pkt *)dbch->frag.buf;
2508 dbch->frag.plen
2509 = fwohci_get_plen(sc, fp, hlen);
2510 if (dbch->frag.plen == 0)
2511 goto out;
2512 }
2513 rlen = dbch->frag.plen - dbch->frag.len;
2514#if 0
2515 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len);
2516#endif
2517 bcopy(ld, dbch->frag.buf + dbch->frag.len,
2518 rlen);
2519 ld += rlen;
2520 len -= rlen;
2521 plen = dbch->frag.plen;
2522 dbch->frag.buf = NULL;
2523 dbch->frag.plen = 0;
2524 dbch->frag.len = 0;
2525 poff = 0;
2526 }else{
2527 fp=(struct fw_pkt *)ld;
2528 fp->mode.ld[0] = htonl(fp->mode.ld[0]);
2529 switch(fp->mode.common.tcode){
2530 case FWTCODE_RREQQ:
2531 case FWTCODE_WRES:
2532 case FWTCODE_WREQQ:
2533 case FWTCODE_RRESQ:
2534 case FWOHCITCODE_PHY:
2535 hlen = 12;
2536 break;
2537 case FWTCODE_RREQB:
2538 case FWTCODE_WREQB:
2539 case FWTCODE_LREQ:
2540 case FWTCODE_RRESB:
2541 case FWTCODE_LRES:
2542 hlen = 16;
2543 break;
2544 default:
2545 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode);
2546 goto out;
2547 }
2548 if (len >= hlen) {
2549 plen = fwohci_get_plen(sc, fp, hlen);
2550 if (plen == 0)
2551 goto out;
2552 plen = (plen + 3) & ~3;
2553 len -= plen;
2554 } else {
2555 plen = -hlen;
2556 len -= hlen;
2557 }
2558 if(resCount > 0 || len > 0){
2559 buf = malloc( dbch->xferq.psize,
2560 M_DEVBUF, M_NOWAIT);
2561 if(buf == NULL){
2562 printf("cannot malloc!\n");
2563 free(db_tr->buf, M_DEVBUF);
2564 goto out;
2565 }
2566 bcopy(ld, buf, plen);
2567 poff = 0;
2568 dbch->frag.buf = NULL;
2569 dbch->frag.plen = 0;
2570 dbch->frag.len = 0;
2571 }else if(len < 0){
2572 dbch->frag.buf = db_tr->buf;
2573 if (plen < 0) {
2574#if 0
2575 printf("plen < 0:"
2576 "hlen: %d len: %d\n",
2577 hlen, len);
2578#endif
2579 dbch->frag.len = hlen + len;
2580 dbch->frag.plen = -hlen;
2581 } else {
2582 dbch->frag.len = plen + len;
2583 dbch->frag.plen = plen;
2584 }
2585 bcopy(ld, db_tr->buf, dbch->frag.len);
2586 buf = NULL;
2587 }else{
2588 buf = db_tr->buf;
2589 poff = ld - (u_int8_t *)buf;
2590 dbch->frag.buf = NULL;
2591 dbch->frag.plen = 0;
2592 dbch->frag.len = 0;
2593 }
2594 ld += plen;
2595 }
2596 if( buf != NULL){
2597/* DMA result-code will be written at the tail of packet */
2598 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2599 spd = (stat >> 5) & 0x3;
2600 stat &= 0x1f;
2601 switch(stat){
2602 case FWOHCIEV_ACKPEND:
2603#if 0
2604 printf("fwohci_arcv: ack pending..\n");
2605#endif
2606 /* fall through */
2607 case FWOHCIEV_ACKCOMPL:
2608 if( poff != 0 )
2609 bcopy(buf+poff, buf, plen - 4);
2610 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd);
2611 break;
2612 case FWOHCIEV_BUSRST:
2613 free(buf, M_DEVBUF);
2614 if (sc->fc.status != FWBUSRESET)
2615 printf("got BUSRST packet!?\n");
2616 break;
2617 default:
2618 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2619#if 0 /* XXX */
2620 goto out;
2621#endif
2622 break;
2623 }
2624 }
2625 pcnt ++;
2626 };
2627out:
2628 if (resCount == 0) {
2629 /* done on this buffer */
2630 fwohci_add_rx_buf(db_tr, dbch->xferq.psize,
2631 dbch->xferq.flag, 0, NULL);
2632 dbch->bottom->db[0].db.desc.depend |= z;
2633 dbch->bottom = db_tr;
2634 db_tr = STAILQ_NEXT(db_tr, link);
2635 dbch->top = db_tr;
2636 dbch->buf_offset = 0;
2637 } else {
2638 dbch->buf_offset = dbch->xferq.psize - resCount;
2639 break;
2640 }
2641 /* XXX make sure DMA is not dead */
2642 }
2643#if 0
2644 if (pcnt < 1)
2645 printf("fwohci_arcv: no packets\n");
2646#endif
2647 splx(s);
2648}
|