1/*
2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 109280 2003-01-15 04:21:16Z simokawa $
34 *
35 */
36
37#define ATRQ_CH 0
38#define ATRS_CH 1
39#define ARRQ_CH 2
40#define ARRS_CH 3
41#define ITX_CH 4

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1161 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb);
1162 /* Attach DB to DMA ch. */
1163 for(idb = 0 ; idb < dbch->ndb ; idb++){
1164 db_tr->dbcnt = 0;
1165 db_tr->db = &db[idb * dbch->ndesc];
1166 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1167 if (!(dbch->xferq.flag & FWXFERQ_PACKET) &&
1168 dbch->xferq.bnpacket != 0) {
1169 /* XXX what those for? */
1170 if (idb % dbch->xferq.bnpacket == 0)
1171 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1172 ].start = (caddr_t)db_tr;
1173 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1174 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1175 ].end = (caddr_t)db_tr;
1176 }
1177 db_tr++;

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1411fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1412{
1413 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1414 int err = 0;
1415 unsigned short tag, ich;
1416 struct fwohci_dbch *dbch;
1417 struct fw_pkt *fp;
1418 struct fwohcidb_tr *db_tr;
1419
1420 tag = (sc->it[dmach].xferq.flag >> 6) & 3;
1421 ich = sc->it[dmach].xferq.flag & 0x3f;
1422 dbch = &sc->it[dmach];
1423 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1424 dbch->xferq.queued = 0;
1425 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk;
1426 dbch->ndesc = 3;
1427 fwohci_db_init(dbch);
1428 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1429 return ENOMEM;
1430 err = fwohci_tx_enable(sc, dbch);
1431 }
1432 if(err)
1433 return err;
1434 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){
1435 if(dbch->xferq.stdma2 != NULL){
1436 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1437 ((struct fwohcidb_tr *)
1438 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1439 |= OHCI_BRANCH_ALWAYS;
1440 ((struct fwohcidb_tr *)
1441 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1442 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1443 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1444 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1445 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1446 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1447 }
1448 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){
1449 if (firewire_debug)
1450 printf("fwohci_itxbuf_enable: kick 0x%08x\n",
1451 OREAD(sc, OHCI_ITCTL(dmach)));
1452 fw_tbuf_update(&sc->fc, dmach, 0);
1453 if(dbch->xferq.stdma == NULL){
1454 return err;
1455 }
1456 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1457 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1458 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1459 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1460 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000);
1461 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma);
1462 if(dbch->xferq.stdma2 != NULL){
1463 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2);
1464 ((struct fwohcidb_tr *)
1465 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd
1466 |= OHCI_BRANCH_ALWAYS;
1467 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend =
1468 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1469 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend =
1470 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc;
1471 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1472 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf;
1473 }else{
1474 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf;
1475 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf;
1476 }
1477 OWRITE(sc, OHCI_ITCMD(dmach),
1478 vtophys(((struct fwohcidb_tr *)
1479 (dbch->xferq.stdma->start))->db) | dbch->ndesc);
1480 if(dbch->xferq.flag & FWXFERQ_DV){
1481 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start;
1482 fp = (struct fw_pkt *)db_tr->buf;
1483 dbch->xferq.dvoffset =
1484 ((fc->cyctimer(fc) >> 12) + 4) & 0xf;
1485#if 0
1486 printf("dvoffset: %d\n", dbch->xferq.dvoffset);
1487#endif
1488 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12);
1489 }
1490
1491 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1492 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1493 }
1494 return err;
1495}
1496
1497static int
1498fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach)
1499{
1500 struct fwohci_softc *sc = (struct fwohci_softc *)fc;

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1928 static int last_timer=0;
1929
1930 timer = (fc->cyctimer(fc) >> 12) & 0xffff;
1931 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start;
1932 fp = (struct fw_pkt *)db_tr->buf;
1933 ciph = (struct ciphdr *) &fp->mode.ld[1];
1934 timestamp = db_tr->db[2].db.desc.count & 0xffff;
1935 cycl = ntohs(ciph->fdf.dv.cyc) >> 12;
1936 diff = cycl - (timestamp & 0xf) - 1;
1937 if (diff < 0)
1938 diff += 16;
1939 if (diff > 8)
1940 diff -= 16;
1941 if (firewire_debug || diff != 0)
1942 printf("dbc: %3d timer: 0x%04x packet: 0x%04x"
1943 " cyc: 0x%x diff: %+1d\n",
1944 ciph->dbc, last_timer, timestamp, cycl, diff);

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