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if_ffecreg.h (256806) if_ffecreg.h (258780)
1/*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * SUCH DAMAGE.
25 *
26 */
27
28#ifndef IF_FFECREG_H
29#define IF_FFECREG_H
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * SUCH DAMAGE.
25 *
26 */
27
28#ifndef IF_FFECREG_H
29#define IF_FFECREG_H
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/ffec/if_ffecreg.h 256806 2013-10-20 21:07:38Z ian $");
32__FBSDID("$FreeBSD: head/sys/dev/ffec/if_ffecreg.h 258780 2013-11-30 22:17:27Z eadler $");
33
34/*
35 * Hardware defines for Freescale Fast Ethernet Controller.
36 */
37
38/*
39 * MAC registers.
40 */
41#define FEC_IER_REG 0x0004
42#define FEC_IEM_REG 0x0008
33
34/*
35 * Hardware defines for Freescale Fast Ethernet Controller.
36 */
37
38/*
39 * MAC registers.
40 */
41#define FEC_IER_REG 0x0004
42#define FEC_IEM_REG 0x0008
43#define FEC_IER_HBERR (1 << 31)
43#define FEC_IER_HBERR (1U << 31)
44#define FEC_IER_BABR (1 << 30)
45#define FEC_IER_BABT (1 << 29)
46#define FEC_IER_GRA (1 << 28)
47#define FEC_IER_TXF (1 << 27)
48#define FEC_IER_TXB (1 << 26)
49#define FEC_IER_RXF (1 << 25)
50#define FEC_IER_RXB (1 << 24)
51#define FEC_IER_MII (1 << 23)

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93#define FEC_MSCR_REG 0x0044
94#define FEC_MSCR_HOLDTIME_SHIFT 8
95#define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT)
96#define FEC_MSCR_DIS_PRE (1 << 7)
97#define FEC_MSCR_MII_SPEED_SHIFT 1
98#define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT)
99
100#define FEC_MIBC_REG 0x0064
44#define FEC_IER_BABR (1 << 30)
45#define FEC_IER_BABT (1 << 29)
46#define FEC_IER_GRA (1 << 28)
47#define FEC_IER_TXF (1 << 27)
48#define FEC_IER_TXB (1 << 26)
49#define FEC_IER_RXF (1 << 25)
50#define FEC_IER_RXB (1 << 24)
51#define FEC_IER_MII (1 << 23)

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93#define FEC_MSCR_REG 0x0044
94#define FEC_MSCR_HOLDTIME_SHIFT 8
95#define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT)
96#define FEC_MSCR_DIS_PRE (1 << 7)
97#define FEC_MSCR_MII_SPEED_SHIFT 1
98#define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT)
99
100#define FEC_MIBC_REG 0x0064
101#define FEC_MIBC_DIS (1 << 31)
101#define FEC_MIBC_DIS (1U << 31)
102#define FEC_MIBC_IDLE (1 << 30)
103#define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */
104
105#define FEC_RCR_REG 0x0084
102#define FEC_MIBC_IDLE (1 << 30)
103#define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */
104
105#define FEC_RCR_REG 0x0084
106#define FEC_RCR_GRS (1 << 31)
106#define FEC_RCR_GRS (1U << 31)
107#define FEC_RCR_NLC (1 << 30)
108#define FEC_RCR_MAX_FL_SHIFT 16
109#define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT)
110#define FEC_RCR_CFEN (1 << 15)
111#define FEC_RCR_CRCFWD (1 << 14)
112#define FEC_RCR_PAUFWD (1 << 13)
113#define FEC_RCR_PADEN (1 << 12)
114#define FEC_RCR_RMII_10T (1 << 9)

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260 * layout, but the bits in the flags field have different meanings.
261 */
262struct ffec_hwdesc
263{
264 uint32_t flags_len;
265 uint32_t buf_paddr;
266};
267
107#define FEC_RCR_NLC (1 << 30)
108#define FEC_RCR_MAX_FL_SHIFT 16
109#define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT)
110#define FEC_RCR_CFEN (1 << 15)
111#define FEC_RCR_CRCFWD (1 << 14)
112#define FEC_RCR_PAUFWD (1 << 13)
113#define FEC_RCR_PADEN (1 << 12)
114#define FEC_RCR_RMII_10T (1 << 9)

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260 * layout, but the bits in the flags field have different meanings.
261 */
262struct ffec_hwdesc
263{
264 uint32_t flags_len;
265 uint32_t buf_paddr;
266};
267
268#define FEC_TXDESC_READY (1 << 31)
268#define FEC_TXDESC_READY (1U << 31)
269#define FEC_TXDESC_T01 (1 << 30)
270#define FEC_TXDESC_WRAP (1 << 29)
271#define FEC_TXDESC_T02 (1 << 28)
272#define FEC_TXDESC_L (1 << 27)
273#define FEC_TXDESC_TC (1 << 26)
274#define FEC_TXDESC_ABC (1 << 25)
275#define FEC_TXDESC_LEN_MASK (0xffff)
276
269#define FEC_TXDESC_T01 (1 << 30)
270#define FEC_TXDESC_WRAP (1 << 29)
271#define FEC_TXDESC_T02 (1 << 28)
272#define FEC_TXDESC_L (1 << 27)
273#define FEC_TXDESC_TC (1 << 26)
274#define FEC_TXDESC_ABC (1 << 25)
275#define FEC_TXDESC_LEN_MASK (0xffff)
276
277#define FEC_RXDESC_EMPTY (1 << 31)
277#define FEC_RXDESC_EMPTY (1U << 31)
278#define FEC_RXDESC_R01 (1 << 30)
279#define FEC_RXDESC_WRAP (1 << 29)
280#define FEC_RXDESC_R02 (1 << 28)
281#define FEC_RXDESC_L (1 << 27)
282#define FEC_RXDESC_M (1 << 24)
283#define FEC_RXDESC_BC (1 << 23)
284#define FEC_RXDESC_MC (1 << 22)
285#define FEC_RXDESC_LG (1 << 21)

--- 18 unchanged lines hidden --- 		278#define FEC_RXDESC_R01 (1 << 30)
279#define FEC_RXDESC_WRAP (1 << 29)
280#define FEC_RXDESC_R02 (1 << 28)
281#define FEC_RXDESC_L (1 << 27)
282#define FEC_RXDESC_M (1 << 24)
283#define FEC_RXDESC_BC (1 << 23)
284#define FEC_RXDESC_MC (1 << 22)
285#define FEC_RXDESC_LG (1 << 21)

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