28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/sockio.h>
43#include <sys/mbuf.h>
44#include <sys/socket.h>
45#include <sys/syslog.h>
46
47#include <sys/module.h>
48#include <sys/bus.h>
49
50#include <machine/bus.h>
51#include <sys/rman.h>
52#include <machine/resource.h>
53
54#include <net/ethernet.h>
55#include <net/if.h>
56#include <net/if_arp.h>
57#include <net/if_dl.h>
58#include <net/if_mib.h>
59
60#include <net/bpf.h>
61#include "opt_bdg.h"
62#ifdef BRIDGE
63#include <net/bridge.h>
64#endif
65
66#include <machine/clock.h>
67#include <machine/md_var.h>
68
69#include <dev/ed/if_edreg.h>
70#include <dev/ed/if_edvar.h>
71
72static void ed_init __P((void *));
73static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
74static void ed_start __P((struct ifnet *));
75static void ed_reset __P((struct ifnet *));
76static void ed_watchdog __P((struct ifnet *));
77
78static void ds_getmcaf __P((struct ed_softc *, u_long *));
79
80static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int));
81
82static __inline void ed_rint __P((struct ed_softc *));
83static __inline void ed_xmit __P((struct ed_softc *));
84static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *,
85 /* u_short */ int));
86static void ed_hpp_set_physical_link __P((struct ed_softc *));
87static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
88 /* u_short */ int));
89static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
90 int));
91
92static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
93 /* u_short */ int));
94static void ed_pio_writemem __P((struct ed_softc *, char *,
95 /* u_short */ int, /* u_short */ int));
96static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
97 int));
98
99static void ed_setrcr __P((struct ed_softc *));
100
101static u_long ds_crc __P((u_char *ep));
102
103/*
104 * Interrupt conversion table for WD/SMC ASIC/83C584
105 */
106static unsigned short ed_intr_val[] = {
107 9,
108 3,
109 5,
110 7,
111 10,
112 11,
113 15,
114 4
115};
116
117/*
118 * Interrupt conversion table for 83C790
119 */
120static unsigned short ed_790_intr_val[] = {
121 0,
122 9,
123 3,
124 5,
125 7,
126 10,
127 11,
128 15
129};
130
131/*
132 * Interrupt conversion table for the HP PC LAN+
133 */
134
135static unsigned short ed_hpp_intr_val[] = {
136 0, /* 0 */
137 0, /* 1 */
138 0, /* 2 */
139 3, /* 3 */
140 4, /* 4 */
141 5, /* 5 */
142 6, /* 6 */
143 7, /* 7 */
144 0, /* 8 */
145 9, /* 9 */
146 10, /* 10 */
147 11, /* 11 */
148 12, /* 12 */
149 0, /* 13 */
150 0, /* 14 */
151 15 /* 15 */
152};
153
154/*
155 * Generic probe routine for testing for the existance of a DS8390.
156 * Must be called after the NIC has just been reset. This routine
157 * works by looking at certain register values that are guaranteed
158 * to be initialized a certain way after power-up or reset. Seems
159 * not to currently work on the 83C690.
160 *
161 * Specifically:
162 *
163 * Register reset bits set bits
164 * Command Register (CR) TXP, STA RD2, STP
165 * Interrupt Status (ISR) RST
166 * Interrupt Mask (IMR) All bits
167 * Data Control (DCR) LAS
168 * Transmit Config. (TCR) LB1, LB0
169 *
170 * We only look at the CR and ISR registers, however, because looking at
171 * the others would require changing register pages (which would be
172 * intrusive if this isn't an 8390).
173 *
174 * Return 1 if 8390 was found, 0 if not.
175 */
176
177int
178ed_probe_generic8390(sc)
179 struct ed_softc *sc;
180{
181 if ((inb(sc->nic_addr + ED_P0_CR) &
182 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
183 (ED_CR_RD2 | ED_CR_STP))
184 return (0);
185 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
186 return (0);
187
188 return (1);
189}
190
191/*
192 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
193 */
194int
195ed_probe_WD80x3(dev)
196 device_t dev;
197{
198 struct ed_softc *sc = device_get_softc(dev);
199 int error;
200 int i;
201 int flags = device_get_flags(dev);
202 u_int memsize, maddr;
203 u_char iptr, isa16bit, sum;
204 u_long conf_maddr, conf_msize, irq, junk;
205
206 error = ed_alloc_port(dev, 0, ED_WD_IO_PORTS);
207 if (error)
208 return (error);
209
210 sc->asic_addr = rman_get_start(sc->port_res);
211 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
212 sc->is790 = 0;
213
214#ifdef TOSH_ETHER
215 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
216 DELAY(10000);
217#endif
218
219 /*
220 * Attempt to do a checksum over the station address PROM. If it
221 * fails, it's probably not a SMC/WD board. There is a problem with
222 * this, though: some clone WD boards don't pass the checksum test.
223 * Danpex boards for one.
224 */
225 for (sum = 0, i = 0; i < 8; ++i)
226 sum += inb(sc->asic_addr + ED_WD_PROM + i);
227
228 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
229
230 /*
231 * Checksum is invalid. This often happens with cheap WD8003E
232 * clones. In this case, the checksum byte (the eighth byte)
233 * seems to always be zero.
234 */
235 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
236 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
237 return (ENXIO);
238 }
239 /* reset card to force it into a known state. */
240#ifdef TOSH_ETHER
241 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
242#else
243 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
244#endif
245 DELAY(100);
246 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
247 /* wait in the case this card is reading its EEROM */
248 DELAY(5000);
249
250 sc->vendor = ED_VENDOR_WD_SMC;
251 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
252
253 /*
254 * Set initial values for width/size.
255 */
256 memsize = 8192;
257 isa16bit = 0;
258 switch (sc->type) {
259 case ED_TYPE_WD8003S:
260 sc->type_str = "WD8003S";
261 break;
262 case ED_TYPE_WD8003E:
263 sc->type_str = "WD8003E";
264 break;
265 case ED_TYPE_WD8003EB:
266 sc->type_str = "WD8003EB";
267 break;
268 case ED_TYPE_WD8003W:
269 sc->type_str = "WD8003W";
270 break;
271 case ED_TYPE_WD8013EBT:
272 sc->type_str = "WD8013EBT";
273 memsize = 16384;
274 isa16bit = 1;
275 break;
276 case ED_TYPE_WD8013W:
277 sc->type_str = "WD8013W";
278 memsize = 16384;
279 isa16bit = 1;
280 break;
281 case ED_TYPE_WD8013EP: /* also WD8003EP */
282 if (inb(sc->asic_addr + ED_WD_ICR)
283 & ED_WD_ICR_16BIT) {
284 isa16bit = 1;
285 memsize = 16384;
286 sc->type_str = "WD8013EP";
287 } else {
288 sc->type_str = "WD8003EP";
289 }
290 break;
291 case ED_TYPE_WD8013WC:
292 sc->type_str = "WD8013WC";
293 memsize = 16384;
294 isa16bit = 1;
295 break;
296 case ED_TYPE_WD8013EBP:
297 sc->type_str = "WD8013EBP";
298 memsize = 16384;
299 isa16bit = 1;
300 break;
301 case ED_TYPE_WD8013EPC:
302 sc->type_str = "WD8013EPC";
303 memsize = 16384;
304 isa16bit = 1;
305 break;
306 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
307 case ED_TYPE_SMC8216T:
308 if (sc->type == ED_TYPE_SMC8216C) {
309 sc->type_str = "SMC8216/SMC8216C";
310 } else {
311 sc->type_str = "SMC8216T";
312 }
313
314 outb(sc->asic_addr + ED_WD790_HWR,
315 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
316 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
317 case ED_WD790_RAR_SZ64:
318 memsize = 65536;
319 break;
320 case ED_WD790_RAR_SZ32:
321 memsize = 32768;
322 break;
323 case ED_WD790_RAR_SZ16:
324 memsize = 16384;
325 break;
326 case ED_WD790_RAR_SZ8:
327 /* 8216 has 16K shared mem -- 8416 has 8K */
328 if (sc->type == ED_TYPE_SMC8216C) {
329 sc->type_str = "SMC8416C/SMC8416BT";
330 } else {
331 sc->type_str = "SMC8416T";
332 }
333 memsize = 8192;
334 break;
335 }
336 outb(sc->asic_addr + ED_WD790_HWR,
337 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
338
339 isa16bit = 1;
340 sc->is790 = 1;
341 break;
342#ifdef TOSH_ETHER
343 case ED_TYPE_TOSHIBA1:
344 sc->type_str = "Toshiba1";
345 memsize = 32768;
346 isa16bit = 1;
347 break;
348 case ED_TYPE_TOSHIBA4:
349 sc->type_str = "Toshiba4";
350 memsize = 32768;
351 isa16bit = 1;
352 break;
353#endif
354 default:
355 sc->type_str = "";
356 break;
357 }
358
359 /*
360 * Make some adjustments to initial values depending on what is found
361 * in the ICR.
362 */
363 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
364#ifdef TOSH_ETHER
365 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
366#endif
367 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
368 isa16bit = 0;
369 memsize = 8192;
370 }
371
372 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
373 &conf_maddr, &conf_msize);
374 if (error)
375 return (error);
376
377#if ED_DEBUG
378 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
379 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
380 for (i = 0; i < 8; i++)
381 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
382#endif
383
384 /*
385 * Allow the user to override the autoconfiguration
386 */
387 if (conf_msize > 1)
388 memsize = conf_msize;
389
390 maddr = conf_maddr;
391 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
392 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
393 maddr, maddr + memsize);
394 return (ENXIO);
395 }
396
397 /*
398 * (note that if the user specifies both of the following flags that
399 * '8bit' mode intentionally has precedence)
400 */
401 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
402 isa16bit = 1;
403 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
404 isa16bit = 0;
405
406 /*
407 * If possible, get the assigned interrupt number from the card and
408 * use it.
409 */
410 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
411
412 /*
413 * Assemble together the encoded interrupt number.
414 */
415 iptr = (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_IR2) |
416 ((inb(sc->asic_addr + ED_WD_IRR) &
417 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
418
419 /*
420 * If no interrupt specified (or "?"), use what the board tells us.
421 */
422 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
423 &irq, &junk);
424 if (error) {
425 bus_set_resource(dev, SYS_RES_IRQ, 0,
426 ed_intr_val[iptr], 1);
427 }
428
429 /*
430 * Enable the interrupt.
431 */
432 outb(sc->asic_addr + ED_WD_IRR,
433 inb(sc->asic_addr + ED_WD_IRR) | ED_WD_IRR_IEN);
434 }
435 if (sc->is790) {
436 outb(sc->asic_addr + ED_WD790_HWR,
437 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
438 iptr = (((inb(sc->asic_addr + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
439 (inb(sc->asic_addr + ED_WD790_GCR) &
440 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
441 outb(sc->asic_addr + ED_WD790_HWR,
442 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
443
444 /*
445 * If no interrupt specified (or "?"), use what the board tells us.
446 */
447 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
448 &irq, &junk);
449 if (error) {
450 bus_set_resource(dev, SYS_RES_IRQ, 0,
451 ed_790_intr_val[iptr], 1);
452 }
453
454 /*
455 * Enable interrupts.
456 */
457 outb(sc->asic_addr + ED_WD790_ICR,
458 inb(sc->asic_addr + ED_WD790_ICR) | ED_WD790_ICR_EIL);
459 }
460 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
461 &irq, &junk);
462 if (error) {
463 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
464 sc->type_str);
465 return (ENXIO);
466 }
467 sc->isa16bit = isa16bit;
468 sc->mem_shared = 1;
469
470 error = ed_alloc_memory(dev, 0, memsize);
471 if (error) {
472 printf("*** ed_alloc_memory() failed! (%d)\n", error);
473 return (error);
474 }
475 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
476
477 /*
478 * allocate one xmit buffer if < 16k, two buffers otherwise
479 */
480 if ((memsize < 16384) ||
481 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
482 sc->txb_cnt = 1;
483 } else {
484 sc->txb_cnt = 2;
485 }
486 sc->tx_page_start = ED_WD_PAGE_OFFSET;
487 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
488 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
489 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
490 sc->mem_size = memsize;
491 sc->mem_end = sc->mem_start + memsize;
492
493 /*
494 * Get station address from on-board ROM
495 */
496 for (i = 0; i < ETHER_ADDR_LEN; ++i)
497 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
498
499 /*
500 * Set upper address bits and 8/16 bit access to shared memory.
501 */
502 if (isa16bit) {
503 if (sc->is790) {
504 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
505 } else {
506 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
507 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
508 }
509 /*
510 * Enable 16bit access
511 */
512 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
513 ED_WD_LAAR_M16EN);
514 } else {
515 if (((sc->type & ED_WD_SOFTCONFIG) ||
516#ifdef TOSH_ETHER
517 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
518#endif
519 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
520 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
521 ED_WD_LAAR_ADDRHI;
522 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
523 }
524 }
525
526 /*
527 * Set address and enable interface shared memory.
528 */
529 if (!sc->is790) {
530#ifdef TOSH_ETHER
531 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
532 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
533 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
534
535#else
536 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
537 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
538#endif
539 sc->cr_proto = ED_CR_RD2;
540 } else {
541 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
542 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
543 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
544 ((kvtop(sc->mem_start) >> 11) & 0x40) |
545 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
546 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
547 sc->cr_proto = 0;
548 }
549
550#if 0
551 printf("starting memory performance test at 0x%x, size %d...\n",
552 sc->mem_start, memsize*16384);
553 for (i = 0; i < 16384; i++)
554 bzero(sc->mem_start, memsize);
555 printf("***DONE***\n");
556#endif
557
558 /*
559 * Now zero memory and verify that it is clear
560 */
561 bzero(sc->mem_start, memsize);
562
563 for (i = 0; i < memsize; ++i) {
564 if (sc->mem_start[i]) {
565 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
566 kvtop(sc->mem_start + i));
567
568 /*
569 * Disable 16 bit access to shared memory
570 */
571 if (isa16bit) {
572 if (sc->is790) {
573 outb(sc->asic_addr + ED_WD_MSR, 0x00);
574 }
575 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
576 ~ED_WD_LAAR_M16EN);
577 }
578 return (ENXIO);
579 }
580 }
581
582 /*
583 * Disable 16bit access to shared memory - we leave it
584 * disabled so that 1) machines reboot properly when the board
585 * is set 16 bit mode and there are conflicting 8bit
586 * devices/ROMS in the same 128k address space as this boards
587 * shared memory. and 2) so that other 8 bit devices with
588 * shared memory can be used in this 128k region, too.
589 */
590 if (isa16bit) {
591 if (sc->is790) {
592 outb(sc->asic_addr + ED_WD_MSR, 0x00);
593 }
594 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
595 ~ED_WD_LAAR_M16EN);
596 }
597 return (0);
598}
599
600/*
601 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
602 */
603int
604ed_probe_3Com(dev)
605 device_t dev;
606{
607 struct ed_softc *sc = device_get_softc(dev);
608 int error;
609 int i;
610 int flags = device_get_flags(dev);
611 u_int memsize;
612 u_char isa16bit;
613 u_long conf_maddr, conf_msize, irq, junk;
614
615 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
616 if (error)
617 return (error);
618
619 sc->asic_addr = rman_get_start(sc->port_res) + ED_3COM_ASIC_OFFSET;
620 sc->nic_addr = rman_get_start(sc->port_res) + ED_3COM_NIC_OFFSET;
621
622 /*
623 * Verify that the kernel configured I/O address matches the board
624 * configured address
625 */
626 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
627 case ED_3COM_BCFR_300:
628 if (rman_get_start(sc->port_res) != 0x300)
629 return (ENXIO);
630 break;
631 case ED_3COM_BCFR_310:
632 if (rman_get_start(sc->port_res) != 0x310)
633 return (ENXIO);
634 break;
635 case ED_3COM_BCFR_330:
636 if (rman_get_start(sc->port_res) != 0x330)
637 return (ENXIO);
638 break;
639 case ED_3COM_BCFR_350:
640 if (rman_get_start(sc->port_res) != 0x350)
641 return (ENXIO);
642 break;
643 case ED_3COM_BCFR_250:
644 if (rman_get_start(sc->port_res) != 0x250)
645 return (ENXIO);
646 break;
647 case ED_3COM_BCFR_280:
648 if (rman_get_start(sc->port_res) != 0x280)
649 return (ENXIO);
650 break;
651 case ED_3COM_BCFR_2A0:
652 if (rman_get_start(sc->port_res) != 0x2a0)
653 return (ENXIO);
654 break;
655 case ED_3COM_BCFR_2E0:
656 if (rman_get_start(sc->port_res) != 0x2e0)
657 return (ENXIO);
658 break;
659 default:
660 return (ENXIO);
661 }
662
663 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
664 &conf_maddr, &conf_msize);
665 if (error)
666 return (error);
667
668 /*
669 * Verify that the kernel shared memory address matches the board
670 * configured address.
671 */
672 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
673 case ED_3COM_PCFR_DC000:
674 if (conf_maddr != 0xdc000)
675 return (ENXIO);
676 break;
677 case ED_3COM_PCFR_D8000:
678 if (conf_maddr != 0xd8000)
679 return (ENXIO);
680 break;
681 case ED_3COM_PCFR_CC000:
682 if (conf_maddr != 0xcc000)
683 return (ENXIO);
684 break;
685 case ED_3COM_PCFR_C8000:
686 if (conf_maddr != 0xc8000)
687 return (ENXIO);
688 break;
689 default:
690 return (ENXIO);
691 }
692
693
694 /*
695 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
696 * sequence because it'll lock up if the cable isn't connected if we
697 * don't.
698 */
699 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
700
701 /*
702 * Wait for a while, then un-reset it
703 */
704 DELAY(50);
705
706 /*
707 * The 3Com ASIC defaults to rather strange settings for the CR after
708 * a reset - it's important to set it again after the following outb
709 * (this is done when we map the PROM below).
710 */
711 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
712
713 /*
714 * Wait a bit for the NIC to recover from the reset
715 */
716 DELAY(5000);
717
718 sc->vendor = ED_VENDOR_3COM;
719 sc->type_str = "3c503";
720 sc->mem_shared = 1;
721 sc->cr_proto = ED_CR_RD2;
722
723 /*
724 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
725 * to it.
726 */
727 memsize = 8192;
728
729 /*
730 * Get station address from on-board ROM
731 */
732
733 /*
734 * First, map ethernet address PROM over the top of where the NIC
735 * registers normally appear.
736 */
737 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
738
739 for (i = 0; i < ETHER_ADDR_LEN; ++i)
740 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
741
742 /*
743 * Unmap PROM - select NIC registers. The proper setting of the
744 * tranceiver is set in ed_init so that the attach code is given a
745 * chance to set the default based on a compile-time config option
746 */
747 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
748
749 /*
750 * Determine if this is an 8bit or 16bit board
751 */
752
753 /*
754 * select page 0 registers
755 */
756 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
757
758 /*
759 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
760 * board.
761 */
762 outb(sc->nic_addr + ED_P0_DCR, 0);
763
764 /*
765 * select page 2 registers
766 */
767 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
768
769 /*
770 * The 3c503 forces the WTS bit to a one if this is a 16bit board
771 */
772 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
773 isa16bit = 1;
774 else
775 isa16bit = 0;
776
777 /*
778 * select page 0 registers
779 */
780 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
781
782 error = ed_alloc_memory(dev, 0, memsize);
783 if (error)
784 return (error);
785
786 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
787 sc->mem_size = memsize;
788 sc->mem_end = sc->mem_start + memsize;
789
790 /*
791 * We have an entire 8k window to put the transmit buffers on the
792 * 16bit boards. But since the 16bit 3c503's shared memory is only
793 * fast enough to overlap the loading of one full-size packet, trying
794 * to load more than 2 buffers can actually leave the transmitter idle
795 * during the load. So 2 seems the best value. (Although a mix of
796 * variable-sized packets might change this assumption. Nonetheless,
797 * we optimize for linear transfers of same-size packets.)
798 */
799 if (isa16bit) {
800 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
801 sc->txb_cnt = 1;
802 else
803 sc->txb_cnt = 2;
804
805 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
806 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
807 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
808 ED_3COM_RX_PAGE_OFFSET_16BIT;
809 sc->mem_ring = sc->mem_start;
810 } else {
811 sc->txb_cnt = 1;
812 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
813 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
814 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
815 ED_3COM_TX_PAGE_OFFSET_8BIT;
816 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
817 }
818
819 sc->isa16bit = isa16bit;
820
821 /*
822 * Initialize GA page start/stop registers. Probably only needed if
823 * doing DMA, but what the hell.
824 */
825 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
826 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
827
828 /*
829 * Set IRQ. 3c503 only allows a choice of irq 2-5.
830 */
831 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
832 &irq, &junk);
833 if (error)
834 return (error);
835
836 switch (irq) {
837 case 2:
838 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
839 break;
840 case 3:
841 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
842 break;
843 case 4:
844 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
845 break;
846 case 5:
847 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
848 break;
849 default:
850 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
851 irq);
852 return (ENXIO);
853 }
854
855 /*
856 * Initialize GA configuration register. Set bank and enable shared
857 * mem.
858 */
859 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
860 ED_3COM_GACFR_MBS0);
861
862 /*
863 * Initialize "Vector Pointer" registers. These gawd-awful things are
864 * compared to 20 bits of the address on ISA, and if they match, the
865 * shared memory is disabled. We set them to 0xffff0...allegedly the
866 * reset vector.
867 */
868 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
869 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
870 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
871
872 /*
873 * Zero memory and verify that it is clear
874 */
875 bzero(sc->mem_start, memsize);
876
877 for (i = 0; i < memsize; ++i)
878 if (sc->mem_start[i]) {
879 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
880 kvtop(sc->mem_start + i));
881 return (ENXIO);
882 }
883 return (0);
884}
885
886/*
887 * Probe the Ethernet MAC addrees for PCMCIA Linksys EtherFast 10/100
888 * and compatible cards (DL10019C Ethernet controller).
889 *
890 * Note: The PAO patches try to use more memory for the card, but that
891 * seems to fail for my card. A future optimization would add this back
892 * conditionally.
893 */
894int
895ed_get_Linksys(sc)
896 struct ed_softc *sc;
897{
898 u_char sum;
899 int i;
900
901 /*
902 * Linksys registers(offset from ASIC base)
903 *
904 * 0x04-0x09 : Physical Address Register 0-5 (PAR0-PAR5)
905 * 0x0A : Card ID Register (CIR)
906 * 0x0B : Check Sum Register (SR)
907 */
908 for (sum = 0, i = 0x04; i < 0x0c; i++)
909 sum += inb(sc->asic_addr + i);
910 if (sum != 0xff)
911 return (0); /* invalid DL10019C */
912 for (i = 0; i < ETHER_ADDR_LEN; i++) {
913 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + 0x04 + i);
914 }
915
916 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
917 sc->isa16bit = 1;
918 sc->type = ED_TYPE_NE2000;
919 sc->type_str = "Linksys";
920 return (1);
921}
922
923/*
924 * Probe and vendor-specific initialization routine for NE1000/2000 boards
925 */
926int
927ed_probe_Novell_generic(dev, port_rid, flags)
928 device_t dev;
929 int port_rid;
930 int flags;
931{
932 struct ed_softc *sc = device_get_softc(dev);
933 u_int memsize, n;
934 u_char romdata[16], tmp;
935 static char test_pattern[32] = "THIS is A memory TEST pattern";
936 char test_buffer[32];
937 int error;
938
939 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
940 if (error)
941 return (error);
942
943 sc->asic_addr = rman_get_start(sc->port_res) + ED_NOVELL_ASIC_OFFSET;
944 sc->nic_addr = rman_get_start(sc->port_res) + ED_NOVELL_NIC_OFFSET;
945
946 /* XXX - do Novell-specific probe here */
947
948 /* Reset the board */
949#ifdef GWETHER
950 outb(sc->asic_addr + ED_NOVELL_RESET, 0);
951 DELAY(200);
952#endif /* GWETHER */
953 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
954
955 /*
956 * I don't know if this is necessary; probably cruft leftover from
957 * Clarkson packet driver code. Doesn't do a thing on the boards I've
958 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
959 * non-invasive...but some boards don't seem to reset and I don't have
960 * complete documentation on what the 'right' thing to do is...so we
961 * do the invasive thing for now. Yuck.]
962 */
963 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
964 DELAY(5000);
965
966 /*
967 * This is needed because some NE clones apparently don't reset the
968 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
969 * - this makes the probe invasive! ...Done against my better
970 * judgement. -DLG
971 */
972 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
973
974 DELAY(5000);
975
976 /* Make sure that we really have an 8390 based board */
977 if (!ed_probe_generic8390(sc))
978 return (ENXIO);
979
980 sc->vendor = ED_VENDOR_NOVELL;
981 sc->mem_shared = 0;
982 sc->cr_proto = ED_CR_RD2;
983
984 /*
985 * Test the ability to read and write to the NIC memory. This has the
986 * side affect of determining if this is an NE1000 or an NE2000.
987 */
988
989 /*
990 * This prevents packets from being stored in the NIC memory when the
991 * readmem routine turns on the start bit in the CR.
992 */
993 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
994
995 /* Temporarily initialize DCR for byte operations */
996 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
997
998 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
999 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1000
1001 sc->isa16bit = 0;
1002
1003 /*
1004 * Write a test pattern in byte mode. If this fails, then there
1005 * probably isn't any memory at 8k - which likely means that the board
1006 * is an NE2000.
1007 */
1008 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1009 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1010
1011 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1012 sc->type = ED_TYPE_NE1000;
1013 sc->type_str = "NE1000";
1014 } else {
1015
1016 /* neither an NE1000 nor a Linksys - try NE2000 */
1017 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1018 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1019 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1020
1021 sc->isa16bit = 1;
1022
1023 /*
1024 * Write a test pattern in word mode. If this also fails, then
1025 * we don't know what this board is.
1026 */
1027 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1028 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1029 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1030 sc->type = ED_TYPE_NE2000;
1031 sc->type_str = "NE2000";
1032 } else {
1033 return (ENXIO);
1034 }
1035 }
1036
1037
1038 /* 8k of memory plus an additional 8k if 16bit */
1039 memsize = 8192 + sc->isa16bit * 8192;
1040
1041#if 0 /* probably not useful - NE boards only come two ways */
1042 /* allow kernel config file overrides */
1043 if (isa_dev->id_msize)
1044 memsize = isa_dev->id_msize;
1045#endif
1046
1047 sc->mem_size = memsize;
1048
1049 /* NIC memory doesn't start at zero on an NE board */
1050 /* The start address is tied to the bus width */
1051 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1052 sc->mem_end = sc->mem_start + memsize;
1053 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1054
1055#ifdef GWETHER
1056 {
1057 int x, i, mstart = 0, msize = 0;
1058 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1059
1060 for (i = 0; i < ED_PAGE_SIZE; i++)
1061 pbuf0[i] = 0;
1062
1063 /* Clear all the memory. */
1064 for (x = 1; x < 256; x++)
1065 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1066
1067 /* Search for the start of RAM. */
1068 for (x = 1; x < 256; x++) {
1069 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1070 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1071 for (i = 0; i < ED_PAGE_SIZE; i++)
1072 pbuf[i] = 255 - x;
1073 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1074 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1075 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1076 mstart = x * ED_PAGE_SIZE;
1077 msize = ED_PAGE_SIZE;
1078 break;
1079 }
1080 }
1081 }
1082
1083 if (mstart == 0) {
1084 device_printf(dev, "Cannot find start of RAM.\n");
1085 return (ENXIO);
1086 }
1087 /* Search for the start of RAM. */
1088 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1089 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1090 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1091 for (i = 0; i < ED_PAGE_SIZE; i++)
1092 pbuf[i] = 255 - x;
1093 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1094 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1095 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1096 msize += ED_PAGE_SIZE;
1097 else {
1098 break;
1099 }
1100 } else {
1101 break;
1102 }
1103 }
1104
1105 if (msize == 0) {
1106 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1107 return (ENXIO);
1108 }
1109 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1110
1111 sc->mem_size = msize;
1112 sc->mem_start = (char *) mstart;
1113 sc->mem_end = (char *) (msize + mstart);
1114 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1115 }
1116#endif /* GWETHER */
1117
1118 /*
1119 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1120 * otherwise).
1121 */
1122 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1123 sc->txb_cnt = 1;
1124 else
1125 sc->txb_cnt = 2;
1126
1127 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1128 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1129
1130 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1131
1132 ed_pio_readmem(sc, 0, romdata, 16);
1133 for (n = 0; n < ETHER_ADDR_LEN; n++)
1134 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1135
1136#ifdef GWETHER
1137 if (sc->arpcom.ac_enaddr[2] == 0x86) {
1138 sc->type_str = "Gateway AT";
1139 }
1140#endif /* GWETHER */
1141
1142 /* clear any pending interrupts that might have occurred above */
1143 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1144
1145 return (0);
1146}
1147
1148int
1149ed_probe_Novell(dev)
1150 device_t dev;
1151{
1152 return ed_probe_Novell_generic(dev, 0, device_get_flags(dev));
1153}
1154
1155#define ED_HPP_TEST_SIZE 16
1156
1157/*
1158 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1159 * (HP Part nos: 27247B and 27252A).
1160 *
1161 * The card has an asic wrapper around a DS8390 core. The asic handles
1162 * host accesses and offers both standard register IO and memory mapped
1163 * IO. Memory mapped I/O allows better performance at the expense of greater
1164 * chance of an incompatibility with existing ISA cards.
1165 *
1166 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1167 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1168 * don't allow 32 bit accesses; these are indicated by a bit in the software
1169 * ID register (see if_edreg.h).
1170 *
1171 * Other caveats are: we should read the MAC address only when the card
1172 * is inactive.
1173 *
1174 * For more information; please consult the CRYNWR packet driver.
1175 *
1176 * The AUI port is turned on using the "link2" option on the ifconfig
1177 * command line.
1178 */
1179int
1180ed_probe_HP_pclanp(dev)
1181 device_t dev;
1182{
1183 struct ed_softc *sc = device_get_softc(dev);
1184 int error;
1185 int n; /* temp var */
1186 int memsize; /* mem on board */
1187 u_char checksum; /* checksum of board address */
1188 u_char irq; /* board configured IRQ */
1189 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1190 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1191 u_long conf_maddr, conf_msize, conf_irq, junk;
1192
1193 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1194 if (error)
1195 return (error);
1196
1197 /* Fill in basic information */
1198 sc->asic_addr = rman_get_start(sc->port_res) + ED_HPP_ASIC_OFFSET;
1199 sc->nic_addr = rman_get_start(sc->port_res) + ED_HPP_NIC_OFFSET;
1200 sc->is790 = 0;
1201 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1202
1203 /*
1204 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1205 */
1206
1207 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) ||
1208 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
1209 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
1210 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
1211 return ENXIO;
1212
1213 /*
1214 * Read the MAC address and verify checksum on the address.
1215 */
1216
1217 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1218 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1219 checksum += (sc->arpcom.ac_enaddr[n] =
1220 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
1221
1222 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1223
1224 if (checksum != 0xFF)
1225 return ENXIO;
1226
1227 /*
1228 * Verify that the software model number is 0.
1229 */
1230
1231 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
1232 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) &
1233 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1234 return ENXIO;
1235
1236 /*
1237 * Read in and save the current options configured on card.
1238 */
1239
1240 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
1241
1242 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1243 ED_HPP_OPTION_CHIP_RESET |
1244 ED_HPP_OPTION_ENABLE_IRQ);
1245
1246 /*
1247 * Reset the chip. This requires writing to the option register
1248 * so take care to preserve the other bits.
1249 */
1250
1251 outw(sc->asic_addr + ED_HPP_OPTION,
1252 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1253 ED_HPP_OPTION_CHIP_RESET)));
1254
1255 DELAY(5000); /* wait for chip reset to complete */
1256
1257 outw(sc->asic_addr + ED_HPP_OPTION,
1258 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1259 ED_HPP_OPTION_CHIP_RESET |
1260 ED_HPP_OPTION_ENABLE_IRQ)));
1261
1262 DELAY(5000);
1263
1264 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
1265 return ENXIO; /* reset did not complete */
1266
1267 /*
1268 * Read out configuration information.
1269 */
1270
1271 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1272
1273 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
1274
1275 /*
1276 * Check for impossible IRQ.
1277 */
1278
1279 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1280 return ENXIO;
1281
1282 /*
1283 * If the kernel IRQ was specified with a '?' use the cards idea
1284 * of the IRQ. If the kernel IRQ was explicitly specified, it
1285 * should match that of the hardware.
1286 */
1287 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1288 &conf_irq, &junk);
1289 if (error) {
1290 bus_set_resource(dev, SYS_RES_IRQ, 0,
1291 ed_hpp_intr_val[irq], 1);
1292 } else {
1293 if (conf_irq != ed_hpp_intr_val[irq])
1294 return (ENXIO);
1295 }
1296
1297 /*
1298 * Fill in softconfig info.
1299 */
1300
1301 sc->vendor = ED_VENDOR_HP;
1302 sc->type = ED_TYPE_HP_PCLANPLUS;
1303 sc->type_str = "HP-PCLAN+";
1304
1305 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1306 sc->mem_start = 0; /* we use offsets inside the card RAM */
1307
1308 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1309
1310 /*
1311 * The board has 32KB of memory. Is there a way to determine
1312 * this programmatically?
1313 */
1314
1315 memsize = 32768;
1316
1317 /*
1318 * Check if memory mapping of the I/O registers possible.
1319 */
1320
1321 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1322 {
1323 u_long mem_addr;
1324
1325 /*
1326 * determine the memory address from the board.
1327 */
1328
1329 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1330 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
1331
1332 /*
1333 * Check that the kernel specified start of memory and
1334 * hardware's idea of it match.
1335 */
1336 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1337 &conf_maddr, &conf_msize);
1338 if (error)
1339 return (error);
1340
1341 if (mem_addr != conf_maddr)
1342 return ENXIO;
1343
1344 error = ed_alloc_memory(dev, 0, memsize);
1345 if (error)
1346 return (error);
1347
1348 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1349 }
1350
1351 /*
1352 * Fill in the rest of the soft config structure.
1353 */
1354
1355 /*
1356 * The transmit page index.
1357 */
1358
1359 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1360
1361 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1362 sc->txb_cnt = 1;
1363 else
1364 sc->txb_cnt = 2;
1365
1366 /*
1367 * Memory description
1368 */
1369
1370 sc->mem_size = memsize;
1371 sc->mem_ring = sc->mem_start +
1372 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1373 sc->mem_end = sc->mem_start + sc->mem_size;
1374
1375 /*
1376 * Receive area starts after the transmit area and
1377 * continues till the end of memory.
1378 */
1379
1380 sc->rec_page_start = sc->tx_page_start +
1381 (sc->txb_cnt * ED_TXBUF_SIZE);
1382 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1383
1384
1385 sc->cr_proto = 0; /* value works */
1386
1387 /*
1388 * Set the wrap registers for string I/O reads.
1389 */
1390
1391 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1392 outw(sc->asic_addr + ED_HPP_HW_WRAP,
1393 ((sc->rec_page_start / ED_PAGE_SIZE) |
1394 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1395
1396 /*
1397 * Reset the register page to normal operation.
1398 */
1399
1400 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1401
1402 /*
1403 * Verify that we can read/write from adapter memory.
1404 * Create test pattern.
1405 */
1406
1407 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1408 {
1409 test_pattern[n] = (n*n) ^ ~n;
1410 }
1411
1412#undef ED_HPP_TEST_SIZE
1413
1414 /*
1415 * Check that the memory is accessible thru the I/O ports.
1416 * Write out the contents of "test_pattern", read back
1417 * into "test_buffer" and compare the two for any
1418 * mismatch.
1419 */
1420
1421 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1422
1423 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1424 sizeof(test_pattern));
1425 ed_pio_readmem(sc, (n * ED_PAGE_SIZE),
1426 test_buffer, sizeof(test_pattern));
1427
1428 if (bcmp(test_pattern, test_buffer,
1429 sizeof(test_pattern)))
1430 return ENXIO;
1431 }
1432
1433 return (ED_HPP_IO_PORTS);
1434
1435}
1436
1437/*
1438 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1439 */
1440
1441void
1442ed_hpp_set_physical_link(struct ed_softc *sc)
1443{
1444 struct ifnet *ifp = &sc->arpcom.ac_if;
1445 int lan_page;
1446
1447 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1448 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
1449
1450 if (ifp->if_flags & IFF_ALTPHYS) {
1451
1452 /*
1453 * Use the AUI port.
1454 */
1455
1456 lan_page |= ED_HPP_LAN_AUI;
1457
1458 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1459 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1460
1461
1462 } else {
1463
1464 /*
1465 * Use the ThinLan interface
1466 */
1467
1468 lan_page &= ~ED_HPP_LAN_AUI;
1469
1470 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1471 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1472
1473 }
1474
1475 /*
1476 * Wait for the lan card to re-initialize itself
1477 */
1478
1479 DELAY(150000); /* wait 150 ms */
1480
1481 /*
1482 * Restore normal pages.
1483 */
1484
1485 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1486
1487}
1488
1489/*
1490 * Allocate a port resource with the given resource id.
1491 */
1492int
1493ed_alloc_port(dev, rid, size)
1494 device_t dev;
1495 int rid;
1496 int size;
1497{
1498 struct ed_softc *sc = device_get_softc(dev);
1499 struct resource *res;
1500
1501 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1502 0ul, ~0ul, size, RF_ACTIVE);
1503 if (res) {
1504 sc->port_rid = rid;
1505 sc->port_res = res;
1506 sc->port_used = size;
1507 return (0);
1508 } else {
1509 return (ENOENT);
1510 }
1511}
1512
1513/*
1514 * Allocate a memory resource with the given resource id.
1515 */
1516int
1517ed_alloc_memory(dev, rid, size)
1518 device_t dev;
1519 int rid;
1520 int size;
1521{
1522 struct ed_softc *sc = device_get_softc(dev);
1523 struct resource *res;
1524
1525 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1526 0ul, ~0ul, size, RF_ACTIVE);
1527 if (res) {
1528 sc->mem_rid = rid;
1529 sc->mem_res = res;
1530 sc->mem_used = size;
1531 return (0);
1532 } else {
1533 return (ENOENT);
1534 }
1535}
1536
1537/*
1538 * Allocate an irq resource with the given resource id.
1539 */
1540int
1541ed_alloc_irq(dev, rid, flags)
1542 device_t dev;
1543 int rid;
1544 int flags;
1545{
1546 struct ed_softc *sc = device_get_softc(dev);
1547 struct resource *res;
1548
1549 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1550 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1551 if (res) {
1552 sc->irq_rid = rid;
1553 sc->irq_res = res;
1554 return (0);
1555 } else {
1556 return (ENOENT);
1557 }
1558}
1559
1560/*
1561 * Release all resources
1562 */
1563void
1564ed_release_resources(dev)
1565 device_t dev;
1566{
1567 struct ed_softc *sc = device_get_softc(dev);
1568
1569 if (sc->port_res) {
1570 bus_release_resource(dev, SYS_RES_IOPORT,
1571 sc->port_rid, sc->port_res);
1572 sc->port_res = 0;
1573 }
1574 if (sc->mem_res) {
1575 bus_release_resource(dev, SYS_RES_MEMORY,
1576 sc->mem_rid, sc->mem_res);
1577 sc->mem_res = 0;
1578 }
1579 if (sc->irq_res) {
1580 bus_release_resource(dev, SYS_RES_IRQ,
1581 sc->irq_rid, sc->irq_res);
1582 sc->irq_res = 0;
1583 }
1584}
1585
1586/*
1587 * Install interface into kernel networking data structures
1588 */
1589int
1590ed_attach(sc, unit, flags)
1591 struct ed_softc *sc;
1592 int unit;
1593 int flags;
1594{
1595 struct ifnet *ifp = &sc->arpcom.ac_if;
1596
1597 /*
1598 * Set interface to stopped condition (reset)
1599 */
1600 ed_stop(sc);
1601
1602 if (!ifp->if_name) {
1603 /*
1604 * Initialize ifnet structure
1605 */
1606 ifp->if_softc = sc;
1607 ifp->if_unit = unit;
1608 ifp->if_name = "ed";
1609 ifp->if_output = ether_output;
1610 ifp->if_start = ed_start;
1611 ifp->if_ioctl = ed_ioctl;
1612 ifp->if_watchdog = ed_watchdog;
1613 ifp->if_init = ed_init;
1614 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1615 ifp->if_linkmib = &sc->mibdata;
1616 ifp->if_linkmiblen = sizeof sc->mibdata;
1617 /*
1618 * XXX - should do a better job.
1619 */
1620 if (sc->is790)
1621 sc->mibdata.dot3StatsEtherChipSet =
1622 DOT3CHIPSET(dot3VendorWesternDigital,
1623 dot3ChipSetWesternDigital83C790);
1624 else
1625 sc->mibdata.dot3StatsEtherChipSet =
1626 DOT3CHIPSET(dot3VendorNational,
1627 dot3ChipSetNational8390);
1628 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1629
1630 /*
1631 * Set default state for ALTPHYS flag (used to disable the
1632 * tranceiver for AUI operation), based on compile-time
1633 * config option.
1634 */
1635 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1636 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1637 IFF_MULTICAST | IFF_ALTPHYS);
1638 else
1639 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1640 IFF_MULTICAST);
1641
1642 /*
1643 * Attach the interface
1644 */
| 28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/sockio.h>
43#include <sys/mbuf.h>
44#include <sys/socket.h>
45#include <sys/syslog.h>
46
47#include <sys/module.h>
48#include <sys/bus.h>
49
50#include <machine/bus.h>
51#include <sys/rman.h>
52#include <machine/resource.h>
53
54#include <net/ethernet.h>
55#include <net/if.h>
56#include <net/if_arp.h>
57#include <net/if_dl.h>
58#include <net/if_mib.h>
59
60#include <net/bpf.h>
61#include "opt_bdg.h"
62#ifdef BRIDGE
63#include <net/bridge.h>
64#endif
65
66#include <machine/clock.h>
67#include <machine/md_var.h>
68
69#include <dev/ed/if_edreg.h>
70#include <dev/ed/if_edvar.h>
71
72static void ed_init __P((void *));
73static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
74static void ed_start __P((struct ifnet *));
75static void ed_reset __P((struct ifnet *));
76static void ed_watchdog __P((struct ifnet *));
77
78static void ds_getmcaf __P((struct ed_softc *, u_long *));
79
80static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int));
81
82static __inline void ed_rint __P((struct ed_softc *));
83static __inline void ed_xmit __P((struct ed_softc *));
84static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *,
85 /* u_short */ int));
86static void ed_hpp_set_physical_link __P((struct ed_softc *));
87static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
88 /* u_short */ int));
89static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
90 int));
91
92static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
93 /* u_short */ int));
94static void ed_pio_writemem __P((struct ed_softc *, char *,
95 /* u_short */ int, /* u_short */ int));
96static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
97 int));
98
99static void ed_setrcr __P((struct ed_softc *));
100
101static u_long ds_crc __P((u_char *ep));
102
103/*
104 * Interrupt conversion table for WD/SMC ASIC/83C584
105 */
106static unsigned short ed_intr_val[] = {
107 9,
108 3,
109 5,
110 7,
111 10,
112 11,
113 15,
114 4
115};
116
117/*
118 * Interrupt conversion table for 83C790
119 */
120static unsigned short ed_790_intr_val[] = {
121 0,
122 9,
123 3,
124 5,
125 7,
126 10,
127 11,
128 15
129};
130
131/*
132 * Interrupt conversion table for the HP PC LAN+
133 */
134
135static unsigned short ed_hpp_intr_val[] = {
136 0, /* 0 */
137 0, /* 1 */
138 0, /* 2 */
139 3, /* 3 */
140 4, /* 4 */
141 5, /* 5 */
142 6, /* 6 */
143 7, /* 7 */
144 0, /* 8 */
145 9, /* 9 */
146 10, /* 10 */
147 11, /* 11 */
148 12, /* 12 */
149 0, /* 13 */
150 0, /* 14 */
151 15 /* 15 */
152};
153
154/*
155 * Generic probe routine for testing for the existance of a DS8390.
156 * Must be called after the NIC has just been reset. This routine
157 * works by looking at certain register values that are guaranteed
158 * to be initialized a certain way after power-up or reset. Seems
159 * not to currently work on the 83C690.
160 *
161 * Specifically:
162 *
163 * Register reset bits set bits
164 * Command Register (CR) TXP, STA RD2, STP
165 * Interrupt Status (ISR) RST
166 * Interrupt Mask (IMR) All bits
167 * Data Control (DCR) LAS
168 * Transmit Config. (TCR) LB1, LB0
169 *
170 * We only look at the CR and ISR registers, however, because looking at
171 * the others would require changing register pages (which would be
172 * intrusive if this isn't an 8390).
173 *
174 * Return 1 if 8390 was found, 0 if not.
175 */
176
177int
178ed_probe_generic8390(sc)
179 struct ed_softc *sc;
180{
181 if ((inb(sc->nic_addr + ED_P0_CR) &
182 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
183 (ED_CR_RD2 | ED_CR_STP))
184 return (0);
185 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
186 return (0);
187
188 return (1);
189}
190
191/*
192 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
193 */
194int
195ed_probe_WD80x3(dev)
196 device_t dev;
197{
198 struct ed_softc *sc = device_get_softc(dev);
199 int error;
200 int i;
201 int flags = device_get_flags(dev);
202 u_int memsize, maddr;
203 u_char iptr, isa16bit, sum;
204 u_long conf_maddr, conf_msize, irq, junk;
205
206 error = ed_alloc_port(dev, 0, ED_WD_IO_PORTS);
207 if (error)
208 return (error);
209
210 sc->asic_addr = rman_get_start(sc->port_res);
211 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
212 sc->is790 = 0;
213
214#ifdef TOSH_ETHER
215 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
216 DELAY(10000);
217#endif
218
219 /*
220 * Attempt to do a checksum over the station address PROM. If it
221 * fails, it's probably not a SMC/WD board. There is a problem with
222 * this, though: some clone WD boards don't pass the checksum test.
223 * Danpex boards for one.
224 */
225 for (sum = 0, i = 0; i < 8; ++i)
226 sum += inb(sc->asic_addr + ED_WD_PROM + i);
227
228 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
229
230 /*
231 * Checksum is invalid. This often happens with cheap WD8003E
232 * clones. In this case, the checksum byte (the eighth byte)
233 * seems to always be zero.
234 */
235 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
236 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
237 return (ENXIO);
238 }
239 /* reset card to force it into a known state. */
240#ifdef TOSH_ETHER
241 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
242#else
243 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
244#endif
245 DELAY(100);
246 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
247 /* wait in the case this card is reading its EEROM */
248 DELAY(5000);
249
250 sc->vendor = ED_VENDOR_WD_SMC;
251 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
252
253 /*
254 * Set initial values for width/size.
255 */
256 memsize = 8192;
257 isa16bit = 0;
258 switch (sc->type) {
259 case ED_TYPE_WD8003S:
260 sc->type_str = "WD8003S";
261 break;
262 case ED_TYPE_WD8003E:
263 sc->type_str = "WD8003E";
264 break;
265 case ED_TYPE_WD8003EB:
266 sc->type_str = "WD8003EB";
267 break;
268 case ED_TYPE_WD8003W:
269 sc->type_str = "WD8003W";
270 break;
271 case ED_TYPE_WD8013EBT:
272 sc->type_str = "WD8013EBT";
273 memsize = 16384;
274 isa16bit = 1;
275 break;
276 case ED_TYPE_WD8013W:
277 sc->type_str = "WD8013W";
278 memsize = 16384;
279 isa16bit = 1;
280 break;
281 case ED_TYPE_WD8013EP: /* also WD8003EP */
282 if (inb(sc->asic_addr + ED_WD_ICR)
283 & ED_WD_ICR_16BIT) {
284 isa16bit = 1;
285 memsize = 16384;
286 sc->type_str = "WD8013EP";
287 } else {
288 sc->type_str = "WD8003EP";
289 }
290 break;
291 case ED_TYPE_WD8013WC:
292 sc->type_str = "WD8013WC";
293 memsize = 16384;
294 isa16bit = 1;
295 break;
296 case ED_TYPE_WD8013EBP:
297 sc->type_str = "WD8013EBP";
298 memsize = 16384;
299 isa16bit = 1;
300 break;
301 case ED_TYPE_WD8013EPC:
302 sc->type_str = "WD8013EPC";
303 memsize = 16384;
304 isa16bit = 1;
305 break;
306 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
307 case ED_TYPE_SMC8216T:
308 if (sc->type == ED_TYPE_SMC8216C) {
309 sc->type_str = "SMC8216/SMC8216C";
310 } else {
311 sc->type_str = "SMC8216T";
312 }
313
314 outb(sc->asic_addr + ED_WD790_HWR,
315 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
316 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
317 case ED_WD790_RAR_SZ64:
318 memsize = 65536;
319 break;
320 case ED_WD790_RAR_SZ32:
321 memsize = 32768;
322 break;
323 case ED_WD790_RAR_SZ16:
324 memsize = 16384;
325 break;
326 case ED_WD790_RAR_SZ8:
327 /* 8216 has 16K shared mem -- 8416 has 8K */
328 if (sc->type == ED_TYPE_SMC8216C) {
329 sc->type_str = "SMC8416C/SMC8416BT";
330 } else {
331 sc->type_str = "SMC8416T";
332 }
333 memsize = 8192;
334 break;
335 }
336 outb(sc->asic_addr + ED_WD790_HWR,
337 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
338
339 isa16bit = 1;
340 sc->is790 = 1;
341 break;
342#ifdef TOSH_ETHER
343 case ED_TYPE_TOSHIBA1:
344 sc->type_str = "Toshiba1";
345 memsize = 32768;
346 isa16bit = 1;
347 break;
348 case ED_TYPE_TOSHIBA4:
349 sc->type_str = "Toshiba4";
350 memsize = 32768;
351 isa16bit = 1;
352 break;
353#endif
354 default:
355 sc->type_str = "";
356 break;
357 }
358
359 /*
360 * Make some adjustments to initial values depending on what is found
361 * in the ICR.
362 */
363 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
364#ifdef TOSH_ETHER
365 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
366#endif
367 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
368 isa16bit = 0;
369 memsize = 8192;
370 }
371
372 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
373 &conf_maddr, &conf_msize);
374 if (error)
375 return (error);
376
377#if ED_DEBUG
378 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
379 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
380 for (i = 0; i < 8; i++)
381 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
382#endif
383
384 /*
385 * Allow the user to override the autoconfiguration
386 */
387 if (conf_msize > 1)
388 memsize = conf_msize;
389
390 maddr = conf_maddr;
391 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
392 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
393 maddr, maddr + memsize);
394 return (ENXIO);
395 }
396
397 /*
398 * (note that if the user specifies both of the following flags that
399 * '8bit' mode intentionally has precedence)
400 */
401 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
402 isa16bit = 1;
403 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
404 isa16bit = 0;
405
406 /*
407 * If possible, get the assigned interrupt number from the card and
408 * use it.
409 */
410 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
411
412 /*
413 * Assemble together the encoded interrupt number.
414 */
415 iptr = (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_IR2) |
416 ((inb(sc->asic_addr + ED_WD_IRR) &
417 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
418
419 /*
420 * If no interrupt specified (or "?"), use what the board tells us.
421 */
422 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
423 &irq, &junk);
424 if (error) {
425 bus_set_resource(dev, SYS_RES_IRQ, 0,
426 ed_intr_val[iptr], 1);
427 }
428
429 /*
430 * Enable the interrupt.
431 */
432 outb(sc->asic_addr + ED_WD_IRR,
433 inb(sc->asic_addr + ED_WD_IRR) | ED_WD_IRR_IEN);
434 }
435 if (sc->is790) {
436 outb(sc->asic_addr + ED_WD790_HWR,
437 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
438 iptr = (((inb(sc->asic_addr + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
439 (inb(sc->asic_addr + ED_WD790_GCR) &
440 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
441 outb(sc->asic_addr + ED_WD790_HWR,
442 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
443
444 /*
445 * If no interrupt specified (or "?"), use what the board tells us.
446 */
447 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
448 &irq, &junk);
449 if (error) {
450 bus_set_resource(dev, SYS_RES_IRQ, 0,
451 ed_790_intr_val[iptr], 1);
452 }
453
454 /*
455 * Enable interrupts.
456 */
457 outb(sc->asic_addr + ED_WD790_ICR,
458 inb(sc->asic_addr + ED_WD790_ICR) | ED_WD790_ICR_EIL);
459 }
460 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
461 &irq, &junk);
462 if (error) {
463 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
464 sc->type_str);
465 return (ENXIO);
466 }
467 sc->isa16bit = isa16bit;
468 sc->mem_shared = 1;
469
470 error = ed_alloc_memory(dev, 0, memsize);
471 if (error) {
472 printf("*** ed_alloc_memory() failed! (%d)\n", error);
473 return (error);
474 }
475 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
476
477 /*
478 * allocate one xmit buffer if < 16k, two buffers otherwise
479 */
480 if ((memsize < 16384) ||
481 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
482 sc->txb_cnt = 1;
483 } else {
484 sc->txb_cnt = 2;
485 }
486 sc->tx_page_start = ED_WD_PAGE_OFFSET;
487 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
488 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
489 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
490 sc->mem_size = memsize;
491 sc->mem_end = sc->mem_start + memsize;
492
493 /*
494 * Get station address from on-board ROM
495 */
496 for (i = 0; i < ETHER_ADDR_LEN; ++i)
497 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
498
499 /*
500 * Set upper address bits and 8/16 bit access to shared memory.
501 */
502 if (isa16bit) {
503 if (sc->is790) {
504 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
505 } else {
506 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
507 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
508 }
509 /*
510 * Enable 16bit access
511 */
512 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
513 ED_WD_LAAR_M16EN);
514 } else {
515 if (((sc->type & ED_WD_SOFTCONFIG) ||
516#ifdef TOSH_ETHER
517 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
518#endif
519 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
520 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
521 ED_WD_LAAR_ADDRHI;
522 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
523 }
524 }
525
526 /*
527 * Set address and enable interface shared memory.
528 */
529 if (!sc->is790) {
530#ifdef TOSH_ETHER
531 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
532 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
533 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
534
535#else
536 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
537 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
538#endif
539 sc->cr_proto = ED_CR_RD2;
540 } else {
541 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
542 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
543 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
544 ((kvtop(sc->mem_start) >> 11) & 0x40) |
545 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
546 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
547 sc->cr_proto = 0;
548 }
549
550#if 0
551 printf("starting memory performance test at 0x%x, size %d...\n",
552 sc->mem_start, memsize*16384);
553 for (i = 0; i < 16384; i++)
554 bzero(sc->mem_start, memsize);
555 printf("***DONE***\n");
556#endif
557
558 /*
559 * Now zero memory and verify that it is clear
560 */
561 bzero(sc->mem_start, memsize);
562
563 for (i = 0; i < memsize; ++i) {
564 if (sc->mem_start[i]) {
565 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
566 kvtop(sc->mem_start + i));
567
568 /*
569 * Disable 16 bit access to shared memory
570 */
571 if (isa16bit) {
572 if (sc->is790) {
573 outb(sc->asic_addr + ED_WD_MSR, 0x00);
574 }
575 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
576 ~ED_WD_LAAR_M16EN);
577 }
578 return (ENXIO);
579 }
580 }
581
582 /*
583 * Disable 16bit access to shared memory - we leave it
584 * disabled so that 1) machines reboot properly when the board
585 * is set 16 bit mode and there are conflicting 8bit
586 * devices/ROMS in the same 128k address space as this boards
587 * shared memory. and 2) so that other 8 bit devices with
588 * shared memory can be used in this 128k region, too.
589 */
590 if (isa16bit) {
591 if (sc->is790) {
592 outb(sc->asic_addr + ED_WD_MSR, 0x00);
593 }
594 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
595 ~ED_WD_LAAR_M16EN);
596 }
597 return (0);
598}
599
600/*
601 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
602 */
603int
604ed_probe_3Com(dev)
605 device_t dev;
606{
607 struct ed_softc *sc = device_get_softc(dev);
608 int error;
609 int i;
610 int flags = device_get_flags(dev);
611 u_int memsize;
612 u_char isa16bit;
613 u_long conf_maddr, conf_msize, irq, junk;
614
615 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
616 if (error)
617 return (error);
618
619 sc->asic_addr = rman_get_start(sc->port_res) + ED_3COM_ASIC_OFFSET;
620 sc->nic_addr = rman_get_start(sc->port_res) + ED_3COM_NIC_OFFSET;
621
622 /*
623 * Verify that the kernel configured I/O address matches the board
624 * configured address
625 */
626 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
627 case ED_3COM_BCFR_300:
628 if (rman_get_start(sc->port_res) != 0x300)
629 return (ENXIO);
630 break;
631 case ED_3COM_BCFR_310:
632 if (rman_get_start(sc->port_res) != 0x310)
633 return (ENXIO);
634 break;
635 case ED_3COM_BCFR_330:
636 if (rman_get_start(sc->port_res) != 0x330)
637 return (ENXIO);
638 break;
639 case ED_3COM_BCFR_350:
640 if (rman_get_start(sc->port_res) != 0x350)
641 return (ENXIO);
642 break;
643 case ED_3COM_BCFR_250:
644 if (rman_get_start(sc->port_res) != 0x250)
645 return (ENXIO);
646 break;
647 case ED_3COM_BCFR_280:
648 if (rman_get_start(sc->port_res) != 0x280)
649 return (ENXIO);
650 break;
651 case ED_3COM_BCFR_2A0:
652 if (rman_get_start(sc->port_res) != 0x2a0)
653 return (ENXIO);
654 break;
655 case ED_3COM_BCFR_2E0:
656 if (rman_get_start(sc->port_res) != 0x2e0)
657 return (ENXIO);
658 break;
659 default:
660 return (ENXIO);
661 }
662
663 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
664 &conf_maddr, &conf_msize);
665 if (error)
666 return (error);
667
668 /*
669 * Verify that the kernel shared memory address matches the board
670 * configured address.
671 */
672 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
673 case ED_3COM_PCFR_DC000:
674 if (conf_maddr != 0xdc000)
675 return (ENXIO);
676 break;
677 case ED_3COM_PCFR_D8000:
678 if (conf_maddr != 0xd8000)
679 return (ENXIO);
680 break;
681 case ED_3COM_PCFR_CC000:
682 if (conf_maddr != 0xcc000)
683 return (ENXIO);
684 break;
685 case ED_3COM_PCFR_C8000:
686 if (conf_maddr != 0xc8000)
687 return (ENXIO);
688 break;
689 default:
690 return (ENXIO);
691 }
692
693
694 /*
695 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
696 * sequence because it'll lock up if the cable isn't connected if we
697 * don't.
698 */
699 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
700
701 /*
702 * Wait for a while, then un-reset it
703 */
704 DELAY(50);
705
706 /*
707 * The 3Com ASIC defaults to rather strange settings for the CR after
708 * a reset - it's important to set it again after the following outb
709 * (this is done when we map the PROM below).
710 */
711 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
712
713 /*
714 * Wait a bit for the NIC to recover from the reset
715 */
716 DELAY(5000);
717
718 sc->vendor = ED_VENDOR_3COM;
719 sc->type_str = "3c503";
720 sc->mem_shared = 1;
721 sc->cr_proto = ED_CR_RD2;
722
723 /*
724 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
725 * to it.
726 */
727 memsize = 8192;
728
729 /*
730 * Get station address from on-board ROM
731 */
732
733 /*
734 * First, map ethernet address PROM over the top of where the NIC
735 * registers normally appear.
736 */
737 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
738
739 for (i = 0; i < ETHER_ADDR_LEN; ++i)
740 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
741
742 /*
743 * Unmap PROM - select NIC registers. The proper setting of the
744 * tranceiver is set in ed_init so that the attach code is given a
745 * chance to set the default based on a compile-time config option
746 */
747 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
748
749 /*
750 * Determine if this is an 8bit or 16bit board
751 */
752
753 /*
754 * select page 0 registers
755 */
756 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
757
758 /*
759 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
760 * board.
761 */
762 outb(sc->nic_addr + ED_P0_DCR, 0);
763
764 /*
765 * select page 2 registers
766 */
767 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
768
769 /*
770 * The 3c503 forces the WTS bit to a one if this is a 16bit board
771 */
772 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
773 isa16bit = 1;
774 else
775 isa16bit = 0;
776
777 /*
778 * select page 0 registers
779 */
780 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
781
782 error = ed_alloc_memory(dev, 0, memsize);
783 if (error)
784 return (error);
785
786 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
787 sc->mem_size = memsize;
788 sc->mem_end = sc->mem_start + memsize;
789
790 /*
791 * We have an entire 8k window to put the transmit buffers on the
792 * 16bit boards. But since the 16bit 3c503's shared memory is only
793 * fast enough to overlap the loading of one full-size packet, trying
794 * to load more than 2 buffers can actually leave the transmitter idle
795 * during the load. So 2 seems the best value. (Although a mix of
796 * variable-sized packets might change this assumption. Nonetheless,
797 * we optimize for linear transfers of same-size packets.)
798 */
799 if (isa16bit) {
800 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
801 sc->txb_cnt = 1;
802 else
803 sc->txb_cnt = 2;
804
805 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
806 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
807 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
808 ED_3COM_RX_PAGE_OFFSET_16BIT;
809 sc->mem_ring = sc->mem_start;
810 } else {
811 sc->txb_cnt = 1;
812 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
813 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
814 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
815 ED_3COM_TX_PAGE_OFFSET_8BIT;
816 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
817 }
818
819 sc->isa16bit = isa16bit;
820
821 /*
822 * Initialize GA page start/stop registers. Probably only needed if
823 * doing DMA, but what the hell.
824 */
825 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
826 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
827
828 /*
829 * Set IRQ. 3c503 only allows a choice of irq 2-5.
830 */
831 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
832 &irq, &junk);
833 if (error)
834 return (error);
835
836 switch (irq) {
837 case 2:
838 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
839 break;
840 case 3:
841 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
842 break;
843 case 4:
844 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
845 break;
846 case 5:
847 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
848 break;
849 default:
850 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
851 irq);
852 return (ENXIO);
853 }
854
855 /*
856 * Initialize GA configuration register. Set bank and enable shared
857 * mem.
858 */
859 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
860 ED_3COM_GACFR_MBS0);
861
862 /*
863 * Initialize "Vector Pointer" registers. These gawd-awful things are
864 * compared to 20 bits of the address on ISA, and if they match, the
865 * shared memory is disabled. We set them to 0xffff0...allegedly the
866 * reset vector.
867 */
868 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
869 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
870 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
871
872 /*
873 * Zero memory and verify that it is clear
874 */
875 bzero(sc->mem_start, memsize);
876
877 for (i = 0; i < memsize; ++i)
878 if (sc->mem_start[i]) {
879 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
880 kvtop(sc->mem_start + i));
881 return (ENXIO);
882 }
883 return (0);
884}
885
886/*
887 * Probe the Ethernet MAC addrees for PCMCIA Linksys EtherFast 10/100
888 * and compatible cards (DL10019C Ethernet controller).
889 *
890 * Note: The PAO patches try to use more memory for the card, but that
891 * seems to fail for my card. A future optimization would add this back
892 * conditionally.
893 */
894int
895ed_get_Linksys(sc)
896 struct ed_softc *sc;
897{
898 u_char sum;
899 int i;
900
901 /*
902 * Linksys registers(offset from ASIC base)
903 *
904 * 0x04-0x09 : Physical Address Register 0-5 (PAR0-PAR5)
905 * 0x0A : Card ID Register (CIR)
906 * 0x0B : Check Sum Register (SR)
907 */
908 for (sum = 0, i = 0x04; i < 0x0c; i++)
909 sum += inb(sc->asic_addr + i);
910 if (sum != 0xff)
911 return (0); /* invalid DL10019C */
912 for (i = 0; i < ETHER_ADDR_LEN; i++) {
913 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + 0x04 + i);
914 }
915
916 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
917 sc->isa16bit = 1;
918 sc->type = ED_TYPE_NE2000;
919 sc->type_str = "Linksys";
920 return (1);
921}
922
923/*
924 * Probe and vendor-specific initialization routine for NE1000/2000 boards
925 */
926int
927ed_probe_Novell_generic(dev, port_rid, flags)
928 device_t dev;
929 int port_rid;
930 int flags;
931{
932 struct ed_softc *sc = device_get_softc(dev);
933 u_int memsize, n;
934 u_char romdata[16], tmp;
935 static char test_pattern[32] = "THIS is A memory TEST pattern";
936 char test_buffer[32];
937 int error;
938
939 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
940 if (error)
941 return (error);
942
943 sc->asic_addr = rman_get_start(sc->port_res) + ED_NOVELL_ASIC_OFFSET;
944 sc->nic_addr = rman_get_start(sc->port_res) + ED_NOVELL_NIC_OFFSET;
945
946 /* XXX - do Novell-specific probe here */
947
948 /* Reset the board */
949#ifdef GWETHER
950 outb(sc->asic_addr + ED_NOVELL_RESET, 0);
951 DELAY(200);
952#endif /* GWETHER */
953 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
954
955 /*
956 * I don't know if this is necessary; probably cruft leftover from
957 * Clarkson packet driver code. Doesn't do a thing on the boards I've
958 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
959 * non-invasive...but some boards don't seem to reset and I don't have
960 * complete documentation on what the 'right' thing to do is...so we
961 * do the invasive thing for now. Yuck.]
962 */
963 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
964 DELAY(5000);
965
966 /*
967 * This is needed because some NE clones apparently don't reset the
968 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
969 * - this makes the probe invasive! ...Done against my better
970 * judgement. -DLG
971 */
972 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
973
974 DELAY(5000);
975
976 /* Make sure that we really have an 8390 based board */
977 if (!ed_probe_generic8390(sc))
978 return (ENXIO);
979
980 sc->vendor = ED_VENDOR_NOVELL;
981 sc->mem_shared = 0;
982 sc->cr_proto = ED_CR_RD2;
983
984 /*
985 * Test the ability to read and write to the NIC memory. This has the
986 * side affect of determining if this is an NE1000 or an NE2000.
987 */
988
989 /*
990 * This prevents packets from being stored in the NIC memory when the
991 * readmem routine turns on the start bit in the CR.
992 */
993 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
994
995 /* Temporarily initialize DCR for byte operations */
996 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
997
998 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
999 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1000
1001 sc->isa16bit = 0;
1002
1003 /*
1004 * Write a test pattern in byte mode. If this fails, then there
1005 * probably isn't any memory at 8k - which likely means that the board
1006 * is an NE2000.
1007 */
1008 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1009 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1010
1011 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1012 sc->type = ED_TYPE_NE1000;
1013 sc->type_str = "NE1000";
1014 } else {
1015
1016 /* neither an NE1000 nor a Linksys - try NE2000 */
1017 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1018 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1019 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1020
1021 sc->isa16bit = 1;
1022
1023 /*
1024 * Write a test pattern in word mode. If this also fails, then
1025 * we don't know what this board is.
1026 */
1027 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1028 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1029 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1030 sc->type = ED_TYPE_NE2000;
1031 sc->type_str = "NE2000";
1032 } else {
1033 return (ENXIO);
1034 }
1035 }
1036
1037
1038 /* 8k of memory plus an additional 8k if 16bit */
1039 memsize = 8192 + sc->isa16bit * 8192;
1040
1041#if 0 /* probably not useful - NE boards only come two ways */
1042 /* allow kernel config file overrides */
1043 if (isa_dev->id_msize)
1044 memsize = isa_dev->id_msize;
1045#endif
1046
1047 sc->mem_size = memsize;
1048
1049 /* NIC memory doesn't start at zero on an NE board */
1050 /* The start address is tied to the bus width */
1051 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1052 sc->mem_end = sc->mem_start + memsize;
1053 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1054
1055#ifdef GWETHER
1056 {
1057 int x, i, mstart = 0, msize = 0;
1058 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1059
1060 for (i = 0; i < ED_PAGE_SIZE; i++)
1061 pbuf0[i] = 0;
1062
1063 /* Clear all the memory. */
1064 for (x = 1; x < 256; x++)
1065 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1066
1067 /* Search for the start of RAM. */
1068 for (x = 1; x < 256; x++) {
1069 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1070 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1071 for (i = 0; i < ED_PAGE_SIZE; i++)
1072 pbuf[i] = 255 - x;
1073 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1074 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1075 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1076 mstart = x * ED_PAGE_SIZE;
1077 msize = ED_PAGE_SIZE;
1078 break;
1079 }
1080 }
1081 }
1082
1083 if (mstart == 0) {
1084 device_printf(dev, "Cannot find start of RAM.\n");
1085 return (ENXIO);
1086 }
1087 /* Search for the start of RAM. */
1088 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1089 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1090 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1091 for (i = 0; i < ED_PAGE_SIZE; i++)
1092 pbuf[i] = 255 - x;
1093 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1094 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1095 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1096 msize += ED_PAGE_SIZE;
1097 else {
1098 break;
1099 }
1100 } else {
1101 break;
1102 }
1103 }
1104
1105 if (msize == 0) {
1106 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1107 return (ENXIO);
1108 }
1109 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1110
1111 sc->mem_size = msize;
1112 sc->mem_start = (char *) mstart;
1113 sc->mem_end = (char *) (msize + mstart);
1114 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1115 }
1116#endif /* GWETHER */
1117
1118 /*
1119 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1120 * otherwise).
1121 */
1122 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1123 sc->txb_cnt = 1;
1124 else
1125 sc->txb_cnt = 2;
1126
1127 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1128 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1129
1130 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1131
1132 ed_pio_readmem(sc, 0, romdata, 16);
1133 for (n = 0; n < ETHER_ADDR_LEN; n++)
1134 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1135
1136#ifdef GWETHER
1137 if (sc->arpcom.ac_enaddr[2] == 0x86) {
1138 sc->type_str = "Gateway AT";
1139 }
1140#endif /* GWETHER */
1141
1142 /* clear any pending interrupts that might have occurred above */
1143 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1144
1145 return (0);
1146}
1147
1148int
1149ed_probe_Novell(dev)
1150 device_t dev;
1151{
1152 return ed_probe_Novell_generic(dev, 0, device_get_flags(dev));
1153}
1154
1155#define ED_HPP_TEST_SIZE 16
1156
1157/*
1158 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1159 * (HP Part nos: 27247B and 27252A).
1160 *
1161 * The card has an asic wrapper around a DS8390 core. The asic handles
1162 * host accesses and offers both standard register IO and memory mapped
1163 * IO. Memory mapped I/O allows better performance at the expense of greater
1164 * chance of an incompatibility with existing ISA cards.
1165 *
1166 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1167 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1168 * don't allow 32 bit accesses; these are indicated by a bit in the software
1169 * ID register (see if_edreg.h).
1170 *
1171 * Other caveats are: we should read the MAC address only when the card
1172 * is inactive.
1173 *
1174 * For more information; please consult the CRYNWR packet driver.
1175 *
1176 * The AUI port is turned on using the "link2" option on the ifconfig
1177 * command line.
1178 */
1179int
1180ed_probe_HP_pclanp(dev)
1181 device_t dev;
1182{
1183 struct ed_softc *sc = device_get_softc(dev);
1184 int error;
1185 int n; /* temp var */
1186 int memsize; /* mem on board */
1187 u_char checksum; /* checksum of board address */
1188 u_char irq; /* board configured IRQ */
1189 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1190 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1191 u_long conf_maddr, conf_msize, conf_irq, junk;
1192
1193 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1194 if (error)
1195 return (error);
1196
1197 /* Fill in basic information */
1198 sc->asic_addr = rman_get_start(sc->port_res) + ED_HPP_ASIC_OFFSET;
1199 sc->nic_addr = rman_get_start(sc->port_res) + ED_HPP_NIC_OFFSET;
1200 sc->is790 = 0;
1201 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1202
1203 /*
1204 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1205 */
1206
1207 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) ||
1208 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
1209 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
1210 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
1211 return ENXIO;
1212
1213 /*
1214 * Read the MAC address and verify checksum on the address.
1215 */
1216
1217 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1218 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1219 checksum += (sc->arpcom.ac_enaddr[n] =
1220 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
1221
1222 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1223
1224 if (checksum != 0xFF)
1225 return ENXIO;
1226
1227 /*
1228 * Verify that the software model number is 0.
1229 */
1230
1231 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
1232 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) &
1233 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1234 return ENXIO;
1235
1236 /*
1237 * Read in and save the current options configured on card.
1238 */
1239
1240 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
1241
1242 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1243 ED_HPP_OPTION_CHIP_RESET |
1244 ED_HPP_OPTION_ENABLE_IRQ);
1245
1246 /*
1247 * Reset the chip. This requires writing to the option register
1248 * so take care to preserve the other bits.
1249 */
1250
1251 outw(sc->asic_addr + ED_HPP_OPTION,
1252 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1253 ED_HPP_OPTION_CHIP_RESET)));
1254
1255 DELAY(5000); /* wait for chip reset to complete */
1256
1257 outw(sc->asic_addr + ED_HPP_OPTION,
1258 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1259 ED_HPP_OPTION_CHIP_RESET |
1260 ED_HPP_OPTION_ENABLE_IRQ)));
1261
1262 DELAY(5000);
1263
1264 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
1265 return ENXIO; /* reset did not complete */
1266
1267 /*
1268 * Read out configuration information.
1269 */
1270
1271 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1272
1273 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
1274
1275 /*
1276 * Check for impossible IRQ.
1277 */
1278
1279 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1280 return ENXIO;
1281
1282 /*
1283 * If the kernel IRQ was specified with a '?' use the cards idea
1284 * of the IRQ. If the kernel IRQ was explicitly specified, it
1285 * should match that of the hardware.
1286 */
1287 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1288 &conf_irq, &junk);
1289 if (error) {
1290 bus_set_resource(dev, SYS_RES_IRQ, 0,
1291 ed_hpp_intr_val[irq], 1);
1292 } else {
1293 if (conf_irq != ed_hpp_intr_val[irq])
1294 return (ENXIO);
1295 }
1296
1297 /*
1298 * Fill in softconfig info.
1299 */
1300
1301 sc->vendor = ED_VENDOR_HP;
1302 sc->type = ED_TYPE_HP_PCLANPLUS;
1303 sc->type_str = "HP-PCLAN+";
1304
1305 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1306 sc->mem_start = 0; /* we use offsets inside the card RAM */
1307
1308 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1309
1310 /*
1311 * The board has 32KB of memory. Is there a way to determine
1312 * this programmatically?
1313 */
1314
1315 memsize = 32768;
1316
1317 /*
1318 * Check if memory mapping of the I/O registers possible.
1319 */
1320
1321 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1322 {
1323 u_long mem_addr;
1324
1325 /*
1326 * determine the memory address from the board.
1327 */
1328
1329 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1330 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
1331
1332 /*
1333 * Check that the kernel specified start of memory and
1334 * hardware's idea of it match.
1335 */
1336 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1337 &conf_maddr, &conf_msize);
1338 if (error)
1339 return (error);
1340
1341 if (mem_addr != conf_maddr)
1342 return ENXIO;
1343
1344 error = ed_alloc_memory(dev, 0, memsize);
1345 if (error)
1346 return (error);
1347
1348 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1349 }
1350
1351 /*
1352 * Fill in the rest of the soft config structure.
1353 */
1354
1355 /*
1356 * The transmit page index.
1357 */
1358
1359 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1360
1361 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1362 sc->txb_cnt = 1;
1363 else
1364 sc->txb_cnt = 2;
1365
1366 /*
1367 * Memory description
1368 */
1369
1370 sc->mem_size = memsize;
1371 sc->mem_ring = sc->mem_start +
1372 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1373 sc->mem_end = sc->mem_start + sc->mem_size;
1374
1375 /*
1376 * Receive area starts after the transmit area and
1377 * continues till the end of memory.
1378 */
1379
1380 sc->rec_page_start = sc->tx_page_start +
1381 (sc->txb_cnt * ED_TXBUF_SIZE);
1382 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1383
1384
1385 sc->cr_proto = 0; /* value works */
1386
1387 /*
1388 * Set the wrap registers for string I/O reads.
1389 */
1390
1391 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1392 outw(sc->asic_addr + ED_HPP_HW_WRAP,
1393 ((sc->rec_page_start / ED_PAGE_SIZE) |
1394 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1395
1396 /*
1397 * Reset the register page to normal operation.
1398 */
1399
1400 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1401
1402 /*
1403 * Verify that we can read/write from adapter memory.
1404 * Create test pattern.
1405 */
1406
1407 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1408 {
1409 test_pattern[n] = (n*n) ^ ~n;
1410 }
1411
1412#undef ED_HPP_TEST_SIZE
1413
1414 /*
1415 * Check that the memory is accessible thru the I/O ports.
1416 * Write out the contents of "test_pattern", read back
1417 * into "test_buffer" and compare the two for any
1418 * mismatch.
1419 */
1420
1421 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1422
1423 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1424 sizeof(test_pattern));
1425 ed_pio_readmem(sc, (n * ED_PAGE_SIZE),
1426 test_buffer, sizeof(test_pattern));
1427
1428 if (bcmp(test_pattern, test_buffer,
1429 sizeof(test_pattern)))
1430 return ENXIO;
1431 }
1432
1433 return (ED_HPP_IO_PORTS);
1434
1435}
1436
1437/*
1438 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1439 */
1440
1441void
1442ed_hpp_set_physical_link(struct ed_softc *sc)
1443{
1444 struct ifnet *ifp = &sc->arpcom.ac_if;
1445 int lan_page;
1446
1447 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1448 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
1449
1450 if (ifp->if_flags & IFF_ALTPHYS) {
1451
1452 /*
1453 * Use the AUI port.
1454 */
1455
1456 lan_page |= ED_HPP_LAN_AUI;
1457
1458 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1459 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1460
1461
1462 } else {
1463
1464 /*
1465 * Use the ThinLan interface
1466 */
1467
1468 lan_page &= ~ED_HPP_LAN_AUI;
1469
1470 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1471 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1472
1473 }
1474
1475 /*
1476 * Wait for the lan card to re-initialize itself
1477 */
1478
1479 DELAY(150000); /* wait 150 ms */
1480
1481 /*
1482 * Restore normal pages.
1483 */
1484
1485 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1486
1487}
1488
1489/*
1490 * Allocate a port resource with the given resource id.
1491 */
1492int
1493ed_alloc_port(dev, rid, size)
1494 device_t dev;
1495 int rid;
1496 int size;
1497{
1498 struct ed_softc *sc = device_get_softc(dev);
1499 struct resource *res;
1500
1501 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1502 0ul, ~0ul, size, RF_ACTIVE);
1503 if (res) {
1504 sc->port_rid = rid;
1505 sc->port_res = res;
1506 sc->port_used = size;
1507 return (0);
1508 } else {
1509 return (ENOENT);
1510 }
1511}
1512
1513/*
1514 * Allocate a memory resource with the given resource id.
1515 */
1516int
1517ed_alloc_memory(dev, rid, size)
1518 device_t dev;
1519 int rid;
1520 int size;
1521{
1522 struct ed_softc *sc = device_get_softc(dev);
1523 struct resource *res;
1524
1525 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1526 0ul, ~0ul, size, RF_ACTIVE);
1527 if (res) {
1528 sc->mem_rid = rid;
1529 sc->mem_res = res;
1530 sc->mem_used = size;
1531 return (0);
1532 } else {
1533 return (ENOENT);
1534 }
1535}
1536
1537/*
1538 * Allocate an irq resource with the given resource id.
1539 */
1540int
1541ed_alloc_irq(dev, rid, flags)
1542 device_t dev;
1543 int rid;
1544 int flags;
1545{
1546 struct ed_softc *sc = device_get_softc(dev);
1547 struct resource *res;
1548
1549 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1550 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1551 if (res) {
1552 sc->irq_rid = rid;
1553 sc->irq_res = res;
1554 return (0);
1555 } else {
1556 return (ENOENT);
1557 }
1558}
1559
1560/*
1561 * Release all resources
1562 */
1563void
1564ed_release_resources(dev)
1565 device_t dev;
1566{
1567 struct ed_softc *sc = device_get_softc(dev);
1568
1569 if (sc->port_res) {
1570 bus_release_resource(dev, SYS_RES_IOPORT,
1571 sc->port_rid, sc->port_res);
1572 sc->port_res = 0;
1573 }
1574 if (sc->mem_res) {
1575 bus_release_resource(dev, SYS_RES_MEMORY,
1576 sc->mem_rid, sc->mem_res);
1577 sc->mem_res = 0;
1578 }
1579 if (sc->irq_res) {
1580 bus_release_resource(dev, SYS_RES_IRQ,
1581 sc->irq_rid, sc->irq_res);
1582 sc->irq_res = 0;
1583 }
1584}
1585
1586/*
1587 * Install interface into kernel networking data structures
1588 */
1589int
1590ed_attach(sc, unit, flags)
1591 struct ed_softc *sc;
1592 int unit;
1593 int flags;
1594{
1595 struct ifnet *ifp = &sc->arpcom.ac_if;
1596
1597 /*
1598 * Set interface to stopped condition (reset)
1599 */
1600 ed_stop(sc);
1601
1602 if (!ifp->if_name) {
1603 /*
1604 * Initialize ifnet structure
1605 */
1606 ifp->if_softc = sc;
1607 ifp->if_unit = unit;
1608 ifp->if_name = "ed";
1609 ifp->if_output = ether_output;
1610 ifp->if_start = ed_start;
1611 ifp->if_ioctl = ed_ioctl;
1612 ifp->if_watchdog = ed_watchdog;
1613 ifp->if_init = ed_init;
1614 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1615 ifp->if_linkmib = &sc->mibdata;
1616 ifp->if_linkmiblen = sizeof sc->mibdata;
1617 /*
1618 * XXX - should do a better job.
1619 */
1620 if (sc->is790)
1621 sc->mibdata.dot3StatsEtherChipSet =
1622 DOT3CHIPSET(dot3VendorWesternDigital,
1623 dot3ChipSetWesternDigital83C790);
1624 else
1625 sc->mibdata.dot3StatsEtherChipSet =
1626 DOT3CHIPSET(dot3VendorNational,
1627 dot3ChipSetNational8390);
1628 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1629
1630 /*
1631 * Set default state for ALTPHYS flag (used to disable the
1632 * tranceiver for AUI operation), based on compile-time
1633 * config option.
1634 */
1635 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1636 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1637 IFF_MULTICAST | IFF_ALTPHYS);
1638 else
1639 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1640 IFF_MULTICAST);
1641
1642 /*
1643 * Attach the interface
1644 */
|
1676 return (0);
1677}
1678
1679/*
1680 * Reset interface.
1681 */
1682static void
1683ed_reset(ifp)
1684 struct ifnet *ifp;
1685{
1686 struct ed_softc *sc = ifp->if_softc;
1687 int s;
1688
1689 if (sc->gone)
1690 return;
1691 s = splimp();
1692
1693 /*
1694 * Stop interface and re-initialize.
1695 */
1696 ed_stop(sc);
1697 ed_init(sc);
1698
1699 (void) splx(s);
1700}
1701
1702/*
1703 * Take interface offline.
1704 */
1705void
1706ed_stop(sc)
1707 struct ed_softc *sc;
1708{
1709 int n = 5000;
1710
1711 if (sc->gone)
1712 return;
1713 /*
1714 * Stop everything on the interface, and select page 0 registers.
1715 */
1716 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1717
1718 /*
1719 * Wait for interface to enter stopped state, but limit # of checks to
1720 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1721 * just in case it's an old one.
1722 */
1723 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1724}
1725
1726/*
1727 * Device timeout/watchdog routine. Entered if the device neglects to
1728 * generate an interrupt after a transmit has been started on it.
1729 */
1730static void
1731ed_watchdog(ifp)
1732 struct ifnet *ifp;
1733{
1734 struct ed_softc *sc = ifp->if_softc;
1735
1736 if (sc->gone)
1737 return;
1738 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1739 ifp->if_oerrors++;
1740
1741 ed_reset(ifp);
1742}
1743
1744/*
1745 * Initialize device.
1746 */
1747static void
1748ed_init(xsc)
1749 void *xsc;
1750{
1751 struct ed_softc *sc = xsc;
1752 struct ifnet *ifp = &sc->arpcom.ac_if;
1753 int i, s;
1754
1755 if (sc->gone)
1756 return;
1757
1758 /* address not known */
1759 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1760 return;
1761
1762 /*
1763 * Initialize the NIC in the exact order outlined in the NS manual.
1764 * This init procedure is "mandatory"...don't change what or when
1765 * things happen.
1766 */
1767 s = splimp();
1768
1769 /* reset transmitter flags */
1770 sc->xmit_busy = 0;
1771 ifp->if_timer = 0;
1772
1773 sc->txb_inuse = 0;
1774 sc->txb_new = 0;
1775 sc->txb_next_tx = 0;
1776
1777 /* This variable is used below - don't move this assignment */
1778 sc->next_packet = sc->rec_page_start + 1;
1779
1780 /*
1781 * Set interface for page 0, Remote DMA complete, Stopped
1782 */
1783 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1784
1785 if (sc->isa16bit) {
1786
1787 /*
1788 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1789 * order=80x86, word-wide DMA xfers,
1790 */
1791 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1792 } else {
1793
1794 /*
1795 * Same as above, but byte-wide DMA xfers
1796 */
1797 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1798 }
1799
1800 /*
1801 * Clear Remote Byte Count Registers
1802 */
1803 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1804 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1805
1806 /*
1807 * For the moment, don't store incoming packets in memory.
1808 */
1809 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1810
1811 /*
1812 * Place NIC in internal loopback mode
1813 */
1814 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1815
1816 /*
1817 * Initialize transmit/receive (ring-buffer) Page Start
1818 */
1819 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1820 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1821 /* Set lower bits of byte addressable framing to 0 */
1822 if (sc->is790)
1823 outb(sc->nic_addr + 0x09, 0);
1824
1825 /*
1826 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1827 */
1828 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1829 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1830
1831 /*
1832 * Clear all interrupts. A '1' in each bit position clears the
1833 * corresponding flag.
1834 */
1835 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1836
1837 /*
1838 * Enable the following interrupts: receive/transmit complete,
1839 * receive/transmit error, and Receiver OverWrite.
1840 *
1841 * Counter overflow and Remote DMA complete are *not* enabled.
1842 */
1843 outb(sc->nic_addr + ED_P0_IMR,
1844 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1845
1846 /*
1847 * Program Command Register for page 1
1848 */
1849 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1850
1851 /*
1852 * Copy out our station address
1853 */
1854 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1855 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1856
1857 /*
1858 * Set Current Page pointer to next_packet (initialized above)
1859 */
1860 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1861
1862 /*
1863 * Program Receiver Configuration Register and multicast filter. CR is
1864 * set to page 0 on return.
1865 */
1866 ed_setrcr(sc);
1867
1868 /*
1869 * Take interface out of loopback
1870 */
1871 outb(sc->nic_addr + ED_P0_TCR, 0);
1872
1873 /*
1874 * If this is a 3Com board, the tranceiver must be software enabled
1875 * (there is no settable hardware default).
1876 */
1877 if (sc->vendor == ED_VENDOR_3COM) {
1878 if (ifp->if_flags & IFF_ALTPHYS) {
1879 outb(sc->asic_addr + ED_3COM_CR, 0);
1880 } else {
1881 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1882 }
1883 }
1884
1885 /*
1886 * Set 'running' flag, and clear output active flag.
1887 */
1888 ifp->if_flags |= IFF_RUNNING;
1889 ifp->if_flags &= ~IFF_OACTIVE;
1890
1891 /*
1892 * ...and attempt to start output
1893 */
1894 ed_start(ifp);
1895
1896 (void) splx(s);
1897}
1898
1899/*
1900 * This routine actually starts the transmission on the interface
1901 */
1902static __inline void
1903ed_xmit(sc)
1904 struct ed_softc *sc;
1905{
1906 struct ifnet *ifp = (struct ifnet *)sc;
1907 unsigned short len;
1908
1909 if (sc->gone)
1910 return;
1911 len = sc->txb_len[sc->txb_next_tx];
1912
1913 /*
1914 * Set NIC for page 0 register access
1915 */
1916 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
1917
1918 /*
1919 * Set TX buffer start page
1920 */
1921 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1922 sc->txb_next_tx * ED_TXBUF_SIZE);
1923
1924 /*
1925 * Set TX length
1926 */
1927 outb(sc->nic_addr + ED_P0_TBCR0, len);
1928 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1929
1930 /*
1931 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1932 */
1933 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1934 sc->xmit_busy = 1;
1935
1936 /*
1937 * Point to next transmit buffer slot and wrap if necessary.
1938 */
1939 sc->txb_next_tx++;
1940 if (sc->txb_next_tx == sc->txb_cnt)
1941 sc->txb_next_tx = 0;
1942
1943 /*
1944 * Set a timer just in case we never hear from the board again
1945 */
1946 ifp->if_timer = 2;
1947}
1948
1949/*
1950 * Start output on interface.
1951 * We make two assumptions here:
1952 * 1) that the current priority is set to splimp _before_ this code
1953 * is called *and* is returned to the appropriate priority after
1954 * return
1955 * 2) that the IFF_OACTIVE flag is checked before this code is called
1956 * (i.e. that the output part of the interface is idle)
1957 */
1958static void
1959ed_start(ifp)
1960 struct ifnet *ifp;
1961{
1962 struct ed_softc *sc = ifp->if_softc;
1963 struct mbuf *m0, *m;
1964 caddr_t buffer;
1965 int len;
1966
1967 if (sc->gone) {
1968 printf("ed_start(%p) GONE\n",ifp);
1969 return;
1970 }
1971outloop:
1972
1973 /*
1974 * First, see if there are buffered packets and an idle transmitter -
1975 * should never happen at this point.
1976 */
1977 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1978 printf("ed: packets buffered, but transmitter idle\n");
1979 ed_xmit(sc);
1980 }
1981
1982 /*
1983 * See if there is room to put another packet in the buffer.
1984 */
1985 if (sc->txb_inuse == sc->txb_cnt) {
1986
1987 /*
1988 * No room. Indicate this to the outside world and exit.
1989 */
1990 ifp->if_flags |= IFF_OACTIVE;
1991 return;
1992 }
1993 IF_DEQUEUE(&ifp->if_snd, m);
1994 if (m == 0) {
1995
1996 /*
1997 * We are using the !OACTIVE flag to indicate to the outside
1998 * world that we can accept an additional packet rather than
1999 * that the transmitter is _actually_ active. Indeed, the
2000 * transmitter may be active, but if we haven't filled all the
2001 * buffers with data then we still want to accept more.
2002 */
2003 ifp->if_flags &= ~IFF_OACTIVE;
2004 return;
2005 }
2006
2007 /*
2008 * Copy the mbuf chain into the transmit buffer
2009 */
2010
2011 m0 = m;
2012
2013 /* txb_new points to next open buffer slot */
2014 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2015
2016 if (sc->mem_shared) {
2017
2018 /*
2019 * Special case setup for 16 bit boards...
2020 */
2021 if (sc->isa16bit) {
2022 switch (sc->vendor) {
2023
2024 /*
2025 * For 16bit 3Com boards (which have 16k of
2026 * memory), we have the xmit buffers in a
2027 * different page of memory ('page 0') - so
2028 * change pages.
2029 */
2030 case ED_VENDOR_3COM:
2031 outb(sc->asic_addr + ED_3COM_GACFR,
2032 ED_3COM_GACFR_RSEL);
2033 break;
2034
2035 /*
2036 * Enable 16bit access to shared memory on
2037 * WD/SMC boards.
2038 */
2039 case ED_VENDOR_WD_SMC:{
2040 outb(sc->asic_addr + ED_WD_LAAR,
2041 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2042 if (sc->is790) {
2043 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
2044 }
2045 break;
2046 }
2047 }
2048 }
2049 for (len = 0; m != 0; m = m->m_next) {
2050 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2051 buffer += m->m_len;
2052 len += m->m_len;
2053 }
2054
2055 /*
2056 * Restore previous shared memory access
2057 */
2058 if (sc->isa16bit) {
2059 switch (sc->vendor) {
2060 case ED_VENDOR_3COM:
2061 outb(sc->asic_addr + ED_3COM_GACFR,
2062 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2063 break;
2064 case ED_VENDOR_WD_SMC:{
2065 if (sc->is790) {
2066 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2067 }
2068 outb(sc->asic_addr + ED_WD_LAAR,
2069 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2070 break;
2071 }
2072 }
2073 }
2074 } else {
2075 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2076 if (len == 0)
2077 goto outloop;
2078 }
2079
2080 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2081
2082 sc->txb_inuse++;
2083
2084 /*
2085 * Point to next buffer slot and wrap if necessary.
2086 */
2087 sc->txb_new++;
2088 if (sc->txb_new == sc->txb_cnt)
2089 sc->txb_new = 0;
2090
2091 if (sc->xmit_busy == 0)
2092 ed_xmit(sc);
2093
2094 /*
2095 * Tap off here if there is a bpf listener.
2096 */
2097 if (ifp->if_bpf) {
2098 bpf_mtap(ifp, m0);
2099 }
2100
2101 m_freem(m0);
2102
2103 /*
2104 * Loop back to the top to possibly buffer more packets
2105 */
2106 goto outloop;
2107}
2108
2109/*
2110 * Ethernet interface receiver interrupt.
2111 */
2112static __inline void
2113ed_rint(sc)
2114 struct ed_softc *sc;
2115{
2116 struct ifnet *ifp = &sc->arpcom.ac_if;
2117 u_char boundry;
2118 u_short len;
2119 struct ed_ring packet_hdr;
2120 char *packet_ptr;
2121
2122 if (sc->gone)
2123 return;
2124
2125 /*
2126 * Set NIC to page 1 registers to get 'current' pointer
2127 */
2128 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2129
2130 /*
2131 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2132 * i.e. it points to where new data has been buffered. The 'CURR'
2133 * (current) register points to the logical end of the ring-buffer -
2134 * i.e. it points to where additional new data will be added. We loop
2135 * here until the logical beginning equals the logical end (or in
2136 * other words, until the ring-buffer is empty).
2137 */
2138 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
2139
2140 /* get pointer to this buffer's header structure */
2141 packet_ptr = sc->mem_ring +
2142 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2143
2144 /*
2145 * The byte count includes a 4 byte header that was added by
2146 * the NIC.
2147 */
2148 if (sc->mem_shared)
2149 packet_hdr = *(struct ed_ring *) packet_ptr;
2150 else
2151 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2152 sizeof(packet_hdr));
2153 len = packet_hdr.count;
2154 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2155 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2156 /*
2157 * Length is a wild value. There's a good chance that
2158 * this was caused by the NIC being old and buggy.
2159 * The bug is that the length low byte is duplicated in
2160 * the high byte. Try to recalculate the length based on
2161 * the pointer to the next packet.
2162 */
2163 /*
2164 * NOTE: sc->next_packet is pointing at the current packet.
2165 */
2166 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2167 if (packet_hdr.next_packet >= sc->next_packet) {
2168 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2169 } else {
2170 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2171 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2172 }
2173 /*
2174 * because buffers are aligned on 256-byte boundary,
2175 * the length computed above is off by 256 in almost
2176 * all cases. Fix it...
2177 */
2178 if (len & 0xff)
2179 len -= 256 ;
2180 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2181 + sizeof(struct ed_ring)))
2182 sc->mibdata.dot3StatsFrameTooLongs++;
2183 }
2184 /*
2185 * Be fairly liberal about what we allow as a "reasonable" length
2186 * so that a [crufty] packet will make it to BPF (and can thus
2187 * be analyzed). Note that all that is really important is that
2188 * we have a length that will fit into one mbuf cluster or less;
2189 * the upper layer protocols can then figure out the length from
2190 * their own length field(s).
2191 */
2192 if ((len > sizeof(struct ed_ring)) &&
2193 (len <= MCLBYTES) &&
2194 (packet_hdr.next_packet >= sc->rec_page_start) &&
2195 (packet_hdr.next_packet < sc->rec_page_stop)) {
2196 /*
2197 * Go get packet.
2198 */
2199 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2200 len - sizeof(struct ed_ring));
2201 ifp->if_ipackets++;
2202 } else {
2203 /*
2204 * Really BAD. The ring pointers are corrupted.
2205 */
2206 log(LOG_ERR,
2207 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2208 ifp->if_unit, len);
2209 ifp->if_ierrors++;
2210 ed_reset(ifp);
2211 return;
2212 }
2213
2214 /*
2215 * Update next packet pointer
2216 */
2217 sc->next_packet = packet_hdr.next_packet;
2218
2219 /*
2220 * Update NIC boundry pointer - being careful to keep it one
2221 * buffer behind. (as recommended by NS databook)
2222 */
2223 boundry = sc->next_packet - 1;
2224 if (boundry < sc->rec_page_start)
2225 boundry = sc->rec_page_stop - 1;
2226
2227 /*
2228 * Set NIC to page 0 registers to update boundry register
2229 */
2230 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2231
2232 outb(sc->nic_addr + ED_P0_BNRY, boundry);
2233
2234 /*
2235 * Set NIC to page 1 registers before looping to top (prepare
2236 * to get 'CURR' current pointer)
2237 */
2238 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2239 }
2240}
2241
2242/*
2243 * Ethernet interface interrupt processor
2244 */
2245void
2246edintr(arg)
2247 void *arg;
2248{
2249 struct ed_softc *sc = (struct ed_softc*) arg;
2250 struct ifnet *ifp = (struct ifnet *)sc;
2251 u_char isr;
2252
2253 if (sc->gone)
2254 return;
2255 /*
2256 * Set NIC to page 0 registers
2257 */
2258 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2259
2260 /*
2261 * loop until there are no more new interrupts
2262 */
2263 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
2264
2265 /*
2266 * reset all the bits that we are 'acknowledging' by writing a
2267 * '1' to each bit position that was set (writing a '1'
2268 * *clears* the bit)
2269 */
2270 outb(sc->nic_addr + ED_P0_ISR, isr);
2271
2272 /*
2273 * Handle transmitter interrupts. Handle these first because
2274 * the receiver will reset the board under some conditions.
2275 */
2276 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2277 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
2278
2279 /*
2280 * Check for transmit error. If a TX completed with an
2281 * error, we end up throwing the packet away. Really
2282 * the only error that is possible is excessive
2283 * collisions, and in this case it is best to allow
2284 * the automatic mechanisms of TCP to backoff the
2285 * flow. Of course, with UDP we're screwed, but this
2286 * is expected when a network is heavily loaded.
2287 */
2288 (void) inb(sc->nic_addr + ED_P0_TSR);
2289 if (isr & ED_ISR_TXE) {
2290 u_char tsr;
2291
2292 /*
2293 * Excessive collisions (16)
2294 */
2295 tsr = inb(sc->nic_addr + ED_P0_TSR);
2296 if ((tsr & ED_TSR_ABT)
2297 && (collisions == 0)) {
2298
2299 /*
2300 * When collisions total 16, the
2301 * P0_NCR will indicate 0, and the
2302 * TSR_ABT is set.
2303 */
2304 collisions = 16;
2305 sc->mibdata.dot3StatsExcessiveCollisions++;
2306 sc->mibdata.dot3StatsCollFrequencies[15]++;
2307 }
2308 if (tsr & ED_TSR_OWC)
2309 sc->mibdata.dot3StatsLateCollisions++;
2310 if (tsr & ED_TSR_CDH)
2311 sc->mibdata.dot3StatsSQETestErrors++;
2312 if (tsr & ED_TSR_CRS)
2313 sc->mibdata.dot3StatsCarrierSenseErrors++;
2314 if (tsr & ED_TSR_FU)
2315 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2316
2317 /*
2318 * update output errors counter
2319 */
2320 ifp->if_oerrors++;
2321 } else {
2322
2323 /*
2324 * Update total number of successfully
2325 * transmitted packets.
2326 */
2327 ifp->if_opackets++;
2328 }
2329
2330 /*
2331 * reset tx busy and output active flags
2332 */
2333 sc->xmit_busy = 0;
2334 ifp->if_flags &= ~IFF_OACTIVE;
2335
2336 /*
2337 * clear watchdog timer
2338 */
2339 ifp->if_timer = 0;
2340
2341 /*
2342 * Add in total number of collisions on last
2343 * transmission.
2344 */
2345 ifp->if_collisions += collisions;
2346 switch(collisions) {
2347 case 0:
2348 case 16:
2349 break;
2350 case 1:
2351 sc->mibdata.dot3StatsSingleCollisionFrames++;
2352 sc->mibdata.dot3StatsCollFrequencies[0]++;
2353 break;
2354 default:
2355 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2356 sc->mibdata.
2357 dot3StatsCollFrequencies[collisions-1]
2358 ++;
2359 break;
2360 }
2361
2362 /*
2363 * Decrement buffer in-use count if not zero (can only
2364 * be zero if a transmitter interrupt occured while
2365 * not actually transmitting). If data is ready to
2366 * transmit, start it transmitting, otherwise defer
2367 * until after handling receiver
2368 */
2369 if (sc->txb_inuse && --sc->txb_inuse)
2370 ed_xmit(sc);
2371 }
2372
2373 /*
2374 * Handle receiver interrupts
2375 */
2376 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2377
2378 /*
2379 * Overwrite warning. In order to make sure that a
2380 * lockup of the local DMA hasn't occurred, we reset
2381 * and re-init the NIC. The NSC manual suggests only a
2382 * partial reset/re-init is necessary - but some chips
2383 * seem to want more. The DMA lockup has been seen
2384 * only with early rev chips - Methinks this bug was
2385 * fixed in later revs. -DG
2386 */
2387 if (isr & ED_ISR_OVW) {
2388 ifp->if_ierrors++;
2389#ifdef DIAGNOSTIC
2390 log(LOG_WARNING,
2391 "ed%d: warning - receiver ring buffer overrun\n",
2392 ifp->if_unit);
2393#endif
2394
2395 /*
2396 * Stop/reset/re-init NIC
2397 */
2398 ed_reset(ifp);
2399 } else {
2400
2401 /*
2402 * Receiver Error. One or more of: CRC error,
2403 * frame alignment error FIFO overrun, or
2404 * missed packet.
2405 */
2406 if (isr & ED_ISR_RXE) {
2407 u_char rsr;
2408 rsr = inb(sc->nic_addr + ED_P0_RSR);
2409 if (rsr & ED_RSR_CRC)
2410 sc->mibdata.dot3StatsFCSErrors++;
2411 if (rsr & ED_RSR_FAE)
2412 sc->mibdata.dot3StatsAlignmentErrors++;
2413 if (rsr & ED_RSR_FO)
2414 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2415 ifp->if_ierrors++;
2416#ifdef ED_DEBUG
2417 printf("ed%d: receive error %x\n", ifp->if_unit,
2418 inb(sc->nic_addr + ED_P0_RSR));
2419#endif
2420 }
2421
2422 /*
2423 * Go get the packet(s) XXX - Doing this on an
2424 * error is dubious because there shouldn't be
2425 * any data to get (we've configured the
2426 * interface to not accept packets with
2427 * errors).
2428 */
2429
2430 /*
2431 * Enable 16bit access to shared memory first
2432 * on WD/SMC boards.
2433 */
2434 if (sc->isa16bit &&
2435 (sc->vendor == ED_VENDOR_WD_SMC)) {
2436
2437 outb(sc->asic_addr + ED_WD_LAAR,
2438 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2439 if (sc->is790) {
2440 outb(sc->asic_addr + ED_WD_MSR,
2441 ED_WD_MSR_MENB);
2442 }
2443 }
2444 ed_rint(sc);
2445
2446 /* disable 16bit access */
2447 if (sc->isa16bit &&
2448 (sc->vendor == ED_VENDOR_WD_SMC)) {
2449
2450 if (sc->is790) {
2451 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2452 }
2453 outb(sc->asic_addr + ED_WD_LAAR,
2454 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2455 }
2456 }
2457 }
2458
2459 /*
2460 * If it looks like the transmitter can take more data,
2461 * attempt to start output on the interface. This is done
2462 * after handling the receiver to give the receiver priority.
2463 */
2464 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2465 ed_start(ifp);
2466
2467 /*
2468 * return NIC CR to standard state: page 0, remote DMA
2469 * complete, start (toggling the TXP bit off, even if was just
2470 * set in the transmit routine, is *okay* - it is 'edge'
2471 * triggered from low to high)
2472 */
2473 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2474
2475 /*
2476 * If the Network Talley Counters overflow, read them to reset
2477 * them. It appears that old 8390's won't clear the ISR flag
2478 * otherwise - resulting in an infinite loop.
2479 */
2480 if (isr & ED_ISR_CNT) {
2481 (void) inb(sc->nic_addr + ED_P0_CNTR0);
2482 (void) inb(sc->nic_addr + ED_P0_CNTR1);
2483 (void) inb(sc->nic_addr + ED_P0_CNTR2);
2484 }
2485 }
2486}
2487
2488/*
2489 * Process an ioctl request. This code needs some work - it looks
2490 * pretty ugly.
2491 */
2492static int
2493ed_ioctl(ifp, command, data)
2494 register struct ifnet *ifp;
2495 u_long command;
2496 caddr_t data;
2497{
2498 struct ed_softc *sc = ifp->if_softc;
2499 int s, error = 0;
2500
2501 if (sc == NULL || sc->gone) {
2502 ifp->if_flags &= ~IFF_RUNNING;
2503 return ENXIO;
2504 }
2505 s = splimp();
2506
2507 switch (command) {
2508
2509 case SIOCSIFADDR:
2510 case SIOCGIFADDR:
2511 case SIOCSIFMTU:
2512 error = ether_ioctl(ifp, command, data);
2513 break;
2514
2515 case SIOCSIFFLAGS:
2516
2517 /*
2518 * If the interface is marked up and stopped, then start it.
2519 * If it is marked down and running, then stop it.
2520 */
2521 if (ifp->if_flags & IFF_UP) {
2522 if ((ifp->if_flags & IFF_RUNNING) == 0)
2523 ed_init(sc);
2524 } else {
2525 if (ifp->if_flags & IFF_RUNNING) {
2526 ed_stop(sc);
2527 ifp->if_flags &= ~IFF_RUNNING;
2528 }
2529 }
2530
2531 /*
2532 * Promiscuous flag may have changed, so reprogram the RCR.
2533 */
2534 ed_setrcr(sc);
2535
2536 /*
2537 * An unfortunate hack to provide the (required) software
2538 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2539 * disables the tranceiver if set.
2540 */
2541 if (sc->vendor == ED_VENDOR_3COM) {
2542 if (ifp->if_flags & IFF_ALTPHYS) {
2543 outb(sc->asic_addr + ED_3COM_CR, 0);
2544 } else {
2545 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2546 }
2547 } else if (sc->vendor == ED_VENDOR_HP)
2548 ed_hpp_set_physical_link(sc);
2549 break;
2550
2551 case SIOCADDMULTI:
2552 case SIOCDELMULTI:
2553 /*
2554 * Multicast list has changed; set the hardware filter
2555 * accordingly.
2556 */
2557 ed_setrcr(sc);
2558 error = 0;
2559 break;
2560
2561 default:
2562 error = EINVAL;
2563 }
2564 (void) splx(s);
2565 return (error);
2566}
2567
2568/*
2569 * Given a source and destination address, copy 'amount' of a packet from
2570 * the ring buffer into a linear destination buffer. Takes into account
2571 * ring-wrap.
2572 */
2573static __inline char *
2574ed_ring_copy(sc, src, dst, amount)
2575 struct ed_softc *sc;
2576 char *src;
2577 char *dst;
2578 u_short amount;
2579{
2580 u_short tmp_amount;
2581
2582 /* does copy wrap to lower addr in ring buffer? */
2583 if (src + amount > sc->mem_end) {
2584 tmp_amount = sc->mem_end - src;
2585
2586 /* copy amount up to end of NIC memory */
2587 if (sc->mem_shared)
2588 bcopy(src, dst, tmp_amount);
2589 else
2590 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2591
2592 amount -= tmp_amount;
2593 src = sc->mem_ring;
2594 dst += tmp_amount;
2595 }
2596 if (sc->mem_shared)
2597 bcopy(src, dst, amount);
2598 else
2599 ed_pio_readmem(sc, (int)src, dst, amount);
2600
2601 return (src + amount);
2602}
2603
2604/*
2605 * Retreive packet from shared memory and send to the next level up via
2606 * ether_input().
2607 */
2608static void
2609ed_get_packet(sc, buf, len)
2610 struct ed_softc *sc;
2611 char *buf;
2612 u_short len;
2613{
2614 struct ether_header *eh;
2615 struct mbuf *m;
2616
2617 /* Allocate a header mbuf */
2618 MGETHDR(m, M_DONTWAIT, MT_DATA);
2619 if (m == NULL)
2620 return;
2621 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2622 m->m_pkthdr.len = m->m_len = len;
2623
2624 /*
2625 * We always put the received packet in a single buffer -
2626 * either with just an mbuf header or in a cluster attached
2627 * to the header. The +2 is to compensate for the alignment
2628 * fixup below.
2629 */
2630 if ((len + 2) > MHLEN) {
2631 /* Attach an mbuf cluster */
2632 MCLGET(m, M_DONTWAIT);
2633
2634 /* Insist on getting a cluster */
2635 if ((m->m_flags & M_EXT) == 0) {
2636 m_freem(m);
2637 return;
2638 }
2639 }
2640
2641 /*
2642 * The +2 is to longword align the start of the real packet.
2643 * This is important for NFS.
2644 */
2645 m->m_data += 2;
2646 eh = mtod(m, struct ether_header *);
2647
2648#ifdef BRIDGE
2649 /*
2650 * Don't read in the entire packet if we know we're going to drop it
2651 */
2652 if (do_bridge) {
2653 struct ifnet *bif;
2654
2655 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2656 if ((bif = bridge_in(&sc->arpcom.ac_if, eh)) == BDG_DROP) {
2657 m_freem(m);
2658 return;
2659 }
2660 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2661 (char *)eh + ETHER_HDR_LEN, len - ETHER_HDR_LEN);
2662 } else
2663#endif
2664 /*
2665 * Get packet, including link layer address, from interface.
2666 */
2667 ed_ring_copy(sc, buf, (char *)eh, len);
2668
2669 /*
2670 * Remove link layer address.
2671 */
2672 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2673 m->m_data += sizeof(struct ether_header);
2674
2675 ether_input(&sc->arpcom.ac_if, eh, m);
2676}
2677
2678/*
2679 * Supporting routines
2680 */
2681
2682/*
2683 * Given a NIC memory source address and a host memory destination
2684 * address, copy 'amount' from NIC to host using Programmed I/O.
2685 * The 'amount' is rounded up to a word - okay as long as mbufs
2686 * are word sized.
2687 * This routine is currently Novell-specific.
2688 */
2689static void
2690ed_pio_readmem(sc, src, dst, amount)
2691 struct ed_softc *sc;
2692 int src;
2693 unsigned char *dst;
2694 unsigned short amount;
2695{
2696 /* HP cards need special handling */
2697 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2698 ed_hpp_readmem(sc, src, dst, amount);
2699 return;
2700 }
2701
2702 /* Regular Novell cards */
2703 /* select page 0 registers */
2704 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2705
2706 /* round up to a word */
2707 if (amount & 1)
2708 ++amount;
2709
2710 /* set up DMA byte count */
2711 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2712 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
2713
2714 /* set up source address in NIC mem */
2715 outb(sc->nic_addr + ED_P0_RSAR0, src);
2716 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
2717
2718 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2719
2720 if (sc->isa16bit) {
2721 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
2722 } else
2723 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2724
2725}
2726
2727/*
2728 * Stripped down routine for writing a linear buffer to NIC memory.
2729 * Only used in the probe routine to test the memory. 'len' must
2730 * be even.
2731 */
2732static void
2733ed_pio_writemem(sc, src, dst, len)
2734 struct ed_softc *sc;
2735 char *src;
2736 unsigned short dst;
2737 unsigned short len;
2738{
2739 int maxwait = 200; /* about 240us */
2740
2741 if (sc->vendor == ED_VENDOR_NOVELL) {
2742
2743 /* select page 0 registers */
2744 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2745
2746 /* reset remote DMA complete flag */
2747 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2748
2749 /* set up DMA byte count */
2750 outb(sc->nic_addr + ED_P0_RBCR0, len);
2751 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
2752
2753 /* set up destination address in NIC mem */
2754 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2755 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2756
2757 /* set remote DMA write */
2758 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2759
2760 if (sc->isa16bit)
2761 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
2762 else
2763 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2764
2765 /*
2766 * Wait for remote DMA complete. This is necessary because on the
2767 * transmit side, data is handled internally by the NIC in bursts and
2768 * we can't start another remote DMA until this one completes. Not
2769 * waiting causes really bad things to happen - like the NIC
2770 * irrecoverably jamming the ISA bus.
2771 */
2772 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2773
2774 } else if ((sc->vendor == ED_VENDOR_HP) &&
2775 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2776
2777 /* HP PCLAN+ */
2778
2779 /* reset remote DMA complete flag */
2780 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2781
2782 /* program the write address in RAM */
2783 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
2784
2785 if (sc->hpp_mem_start) {
2786 u_short *s = (u_short *) src;
2787 volatile u_short *d = (u_short *) sc->hpp_mem_start;
2788 u_short *const fence = s + (len >> 1);
2789
2790 /*
2791 * Enable memory mapped access.
2792 */
2793
2794 outw(sc->asic_addr + ED_HPP_OPTION,
2795 sc->hpp_options &
2796 ~(ED_HPP_OPTION_MEM_DISABLE |
2797 ED_HPP_OPTION_BOOT_ROM_ENB));
2798
2799 /*
2800 * Copy to NIC memory.
2801 */
2802
2803 while (s < fence)
2804 *d = *s++;
2805
2806 /*
2807 * Restore Boot ROM access.
2808 */
2809
2810 outw(sc->asic_addr + ED_HPP_OPTION,
2811 sc->hpp_options);
2812
2813 } else {
2814 /* write data using I/O writes */
2815 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
2816 }
2817
2818 }
2819}
2820
2821/*
2822 * Write an mbuf chain to the destination NIC memory address using
2823 * programmed I/O.
2824 */
2825static u_short
2826ed_pio_write_mbufs(sc, m, dst)
2827 struct ed_softc *sc;
2828 struct mbuf *m;
2829 int dst;
2830{
2831 struct ifnet *ifp = (struct ifnet *)sc;
2832 unsigned short total_len, dma_len;
2833 struct mbuf *mp;
2834 int maxwait = 200; /* about 240us */
2835
2836 /* HP PC Lan+ cards need special handling */
2837 if ((sc->vendor == ED_VENDOR_HP) &&
2838 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2839 return ed_hpp_write_mbufs(sc, m, dst);
2840 }
2841
2842 /* First, count up the total number of bytes to copy */
2843 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2844 total_len += mp->m_len;
2845
2846 dma_len = total_len;
2847 if (sc->isa16bit && (dma_len & 1))
2848 dma_len++;
2849
2850 /* select page 0 registers */
2851 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2852
2853 /* reset remote DMA complete flag */
2854 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2855
2856 /* set up DMA byte count */
2857 outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
2858 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
2859
2860 /* set up destination address in NIC mem */
2861 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2862 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2863
2864 /* set remote DMA write */
2865 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2866
2867 /*
2868 * Transfer the mbuf chain to the NIC memory.
2869 * 16-bit cards require that data be transferred as words, and only words.
2870 * So that case requires some extra code to patch over odd-length mbufs.
2871 */
2872
2873 if (!sc->isa16bit) {
2874 /* NE1000s are easy */
2875 while (m) {
2876 if (m->m_len) {
2877 outsb(sc->asic_addr + ED_NOVELL_DATA,
2878 m->m_data, m->m_len);
2879 }
2880 m = m->m_next;
2881 }
2882 } else {
2883 /* NE2000s are a pain */
2884 unsigned char *data;
2885 int len, wantbyte;
2886 unsigned char savebyte[2];
2887
2888 wantbyte = 0;
2889
2890 while (m) {
2891 len = m->m_len;
2892 if (len) {
2893 data = mtod(m, caddr_t);
2894 /* finish the last word */
2895 if (wantbyte) {
2896 savebyte[1] = *data;
2897 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
2898 data++;
2899 len--;
2900 wantbyte = 0;
2901 }
2902 /* output contiguous words */
2903 if (len > 1) {
2904 outsw(sc->asic_addr + ED_NOVELL_DATA,
2905 data, len >> 1);
2906 data += len & ~1;
2907 len &= 1;
2908 }
2909 /* save last byte, if necessary */
2910 if (len == 1) {
2911 savebyte[0] = *data;
2912 wantbyte = 1;
2913 }
2914 }
2915 m = m->m_next;
2916 }
2917 /* spit last byte */
2918 if (wantbyte) {
2919 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
2920 }
2921 }
2922
2923 /*
2924 * Wait for remote DMA complete. This is necessary because on the
2925 * transmit side, data is handled internally by the NIC in bursts and
2926 * we can't start another remote DMA until this one completes. Not
2927 * waiting causes really bad things to happen - like the NIC
2928 * irrecoverably jamming the ISA bus.
2929 */
2930 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2931
2932 if (!maxwait) {
2933 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2934 ifp->if_unit);
2935 ed_reset(ifp);
2936 return(0);
2937 }
2938 return (total_len);
2939}
2940
2941/*
2942 * Support routines to handle the HP PC Lan+ card.
2943 */
2944
2945/*
2946 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2947 * IO.
2948 */
2949
2950static void
2951ed_hpp_readmem(sc, src, dst, amount)
2952 struct ed_softc *sc;
2953 unsigned short src;
2954 unsigned char *dst;
2955 unsigned short amount;
2956{
2957
2958 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2959
2960
2961 /* Program the source address in RAM */
2962 outw(sc->asic_addr + ED_HPP_PAGE_2, src);
2963
2964 /*
2965 * The HP PC Lan+ card supports word reads as well as
2966 * a memory mapped i/o port that is aliased to every
2967 * even address on the board.
2968 */
2969
2970 if (sc->hpp_mem_start) {
2971
2972 /* Enable memory mapped access. */
2973 outw(sc->asic_addr + ED_HPP_OPTION,
2974 sc->hpp_options &
2975 ~(ED_HPP_OPTION_MEM_DISABLE |
2976 ED_HPP_OPTION_BOOT_ROM_ENB));
2977
2978 if (use_32bit_access && (amount > 3)) {
2979 u_long *dl = (u_long *) dst;
2980 volatile u_long *const sl =
2981 (u_long *) sc->hpp_mem_start;
2982 u_long *const fence = dl + (amount >> 2);
2983
2984 /* Copy out NIC data. We could probably write this
2985 as a `movsl'. The currently generated code is lousy.
2986 */
2987
2988 while (dl < fence)
2989 *dl++ = *sl;
2990
2991 dst += (amount & ~3);
2992 amount &= 3;
2993
2994 }
2995
2996 /* Finish off any words left, as a series of short reads */
2997 if (amount > 1) {
2998 u_short *d = (u_short *) dst;
2999 volatile u_short *const s =
3000 (u_short *) sc->hpp_mem_start;
3001 u_short *const fence = d + (amount >> 1);
3002
3003 /* Copy out NIC data. */
3004
3005 while (d < fence)
3006 *d++ = *s;
3007
3008 dst += (amount & ~1);
3009 amount &= 1;
3010 }
3011
3012 /*
3013 * read in a byte; however we need to always read 16 bits
3014 * at a time or the hardware gets into a funny state
3015 */
3016
3017 if (amount == 1) {
3018 /* need to read in a short and copy LSB */
3019 volatile u_short *const s =
3020 (volatile u_short *) sc->hpp_mem_start;
3021
3022 *dst = (*s) & 0xFF;
3023 }
3024
3025 /* Restore Boot ROM access. */
3026
3027 outw(sc->asic_addr + ED_HPP_OPTION,
3028 sc->hpp_options);
3029
3030
3031 } else {
3032 /* Read in data using the I/O port */
3033 if (use_32bit_access && (amount > 3)) {
3034 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
3035 dst += (amount & ~3);
3036 amount &= 3;
3037 }
3038 if (amount > 1) {
3039 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
3040 dst += (amount & ~1);
3041 amount &= 1;
3042 }
3043 if (amount == 1) { /* read in a short and keep the LSB */
3044 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
3045 }
3046 }
3047}
3048
3049/*
3050 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3051 * outsw() or via the memory mapped interface to the same register.
3052 * Writes have to be in word units; byte accesses won't work and may cause
3053 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3054 * allows it.
3055 */
3056
3057static u_short
3058ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3059{
3060 int len, wantbyte;
3061 unsigned short total_len;
3062 unsigned char savebyte[2];
3063 volatile u_short * const d =
3064 (volatile u_short *) sc->hpp_mem_start;
3065 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3066
3067 /* select page 0 registers */
3068 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3069
3070 /* reset remote DMA complete flag */
3071 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
3072
3073 /* program the write address in RAM */
3074 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
3075
3076 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3077 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options &
3078 ~(ED_HPP_OPTION_MEM_DISABLE |
3079 ED_HPP_OPTION_BOOT_ROM_ENB));
3080
3081 wantbyte = 0;
3082 total_len = 0;
3083
3084 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3085 while (m) {
3086 total_len += (len = m->m_len);
3087 if (len) {
3088 caddr_t data = mtod(m, caddr_t);
3089 /* finish the last word of the previous mbuf */
3090 if (wantbyte) {
3091 savebyte[1] = *data;
3092 *d = *((ushort *) savebyte);
3093 data++; len--; wantbyte = 0;
3094 }
3095 /* output contiguous words */
3096 if ((len > 3) && (use_32bit_accesses)) {
3097 volatile u_long *const dl =
3098 (volatile u_long *) d;
3099 u_long *sl = (u_long *) data;
3100 u_long *fence = sl + (len >> 2);
3101
3102 while (sl < fence)
3103 *dl = *sl++;
3104
3105 data += (len & ~3);
3106 len &= 3;
3107 }
3108 /* finish off remain 16 bit writes */
3109 if (len > 1) {
3110 u_short *s = (u_short *) data;
3111 u_short *fence = s + (len >> 1);
3112
3113 while (s < fence)
3114 *d = *s++;
3115
3116 data += (len & ~1);
3117 len &= 1;
3118 }
3119 /* save last byte if needed */
3120 if ((wantbyte = (len == 1)) != 0)
3121 savebyte[0] = *data;
3122 }
3123 m = m->m_next; /* to next mbuf */
3124 }
3125 if (wantbyte) /* write last byte */
3126 *d = *((u_short *) savebyte);
3127 } else {
3128 /* use programmed I/O */
3129 while (m) {
3130 total_len += (len = m->m_len);
3131 if (len) {
3132 caddr_t data = mtod(m, caddr_t);
3133 /* finish the last word of the previous mbuf */
3134 if (wantbyte) {
3135 savebyte[1] = *data;
3136 outw(sc->asic_addr + ED_HPP_PAGE_4,
3137 *((u_short *)savebyte));
3138 data++;
3139 len--;
3140 wantbyte = 0;
3141 }
3142 /* output contiguous words */
3143 if ((len > 3) && use_32bit_accesses) {
3144 outsl(sc->asic_addr + ED_HPP_PAGE_4,
3145 data, len >> 2);
3146 data += (len & ~3);
3147 len &= 3;
3148 }
3149 /* finish off remaining 16 bit accesses */
3150 if (len > 1) {
3151 outsw(sc->asic_addr + ED_HPP_PAGE_4,
3152 data, len >> 1);
3153 data += (len & ~1);
3154 len &= 1;
3155 }
3156 if ((wantbyte = (len == 1)) != 0)
3157 savebyte[0] = *data;
3158
3159 } /* if len != 0 */
3160 m = m->m_next;
3161 }
3162 if (wantbyte) /* spit last byte */
3163 outw(sc->asic_addr + ED_HPP_PAGE_4,
3164 *(u_short *)savebyte);
3165
3166 }
3167
3168 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3169 outw(sc->asic_addr + ED_HPP_OPTION,
3170 sc->hpp_options);
3171
3172 return (total_len);
3173}
3174
3175static void
3176ed_setrcr(sc)
3177 struct ed_softc *sc;
3178{
3179 struct ifnet *ifp = (struct ifnet *)sc;
3180 int i;
3181
3182 /* set page 1 registers */
3183 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3184
3185 if (ifp->if_flags & IFF_PROMISC) {
3186
3187 /*
3188 * Reconfigure the multicast filter.
3189 */
3190 for (i = 0; i < 8; i++)
3191 outb(sc->nic_addr + ED_P1_MAR(i), 0xff);
3192
3193 /*
3194 * And turn on promiscuous mode. Also enable reception of
3195 * runts and packets with CRC & alignment errors.
3196 */
3197 /* Set page 0 registers */
3198 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3199
3200 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3201 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
3202 } else {
3203 /* set up multicast addresses and filter modes */
3204 if (ifp->if_flags & IFF_MULTICAST) {
3205 u_long mcaf[2];
3206
3207 if (ifp->if_flags & IFF_ALLMULTI) {
3208 mcaf[0] = 0xffffffff;
3209 mcaf[1] = 0xffffffff;
3210 } else
3211 ds_getmcaf(sc, mcaf);
3212
3213 /*
3214 * Set multicast filter on chip.
3215 */
3216 for (i = 0; i < 8; i++)
3217 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3218
3219 /* Set page 0 registers */
3220 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3221
3222 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
3223 } else {
3224
3225 /*
3226 * Initialize multicast address hashing registers to
3227 * not accept multicasts.
3228 */
3229 for (i = 0; i < 8; ++i)
3230 outb(sc->nic_addr + ED_P1_MAR(i), 0x00);
3231
3232 /* Set page 0 registers */
3233 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3234
3235 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
3236 }
3237 }
3238
3239 /*
3240 * Start interface.
3241 */
3242 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3243}
3244
3245/*
3246 * Compute crc for ethernet address
3247 */
3248static u_long
3249ds_crc(ep)
3250 u_char *ep;
3251{
3252#define POLYNOMIAL 0x04c11db6
3253 register u_long crc = 0xffffffffL;
3254 register int carry, i, j;
3255 register u_char b;
3256
3257 for (i = 6; --i >= 0;) {
3258 b = *ep++;
3259 for (j = 8; --j >= 0;) {
3260 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
3261 crc <<= 1;
3262 b >>= 1;
3263 if (carry)
3264 crc = ((crc ^ POLYNOMIAL) | carry);
3265 }
3266 }
3267 return crc;
3268#undef POLYNOMIAL
3269}
3270
3271/*
3272 * Compute the multicast address filter from the
3273 * list of multicast addresses we need to listen to.
3274 */
3275static void
3276ds_getmcaf(sc, mcaf)
3277 struct ed_softc *sc;
3278 u_long *mcaf;
3279{
3280 register u_int index;
3281 register u_char *af = (u_char *) mcaf;
3282 struct ifmultiaddr *ifma;
3283
3284 mcaf[0] = 0;
3285 mcaf[1] = 0;
3286
3287 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3288 ifma = ifma->ifma_link.le_next) {
3289 if (ifma->ifma_addr->sa_family != AF_LINK)
3290 continue;
3291 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3292 >> 26;
3293 af[index >> 3] |= 1 << (index & 7);
3294 }
3295}
| 1671 return (0);
1672}
1673
1674/*
1675 * Reset interface.
1676 */
1677static void
1678ed_reset(ifp)
1679 struct ifnet *ifp;
1680{
1681 struct ed_softc *sc = ifp->if_softc;
1682 int s;
1683
1684 if (sc->gone)
1685 return;
1686 s = splimp();
1687
1688 /*
1689 * Stop interface and re-initialize.
1690 */
1691 ed_stop(sc);
1692 ed_init(sc);
1693
1694 (void) splx(s);
1695}
1696
1697/*
1698 * Take interface offline.
1699 */
1700void
1701ed_stop(sc)
1702 struct ed_softc *sc;
1703{
1704 int n = 5000;
1705
1706 if (sc->gone)
1707 return;
1708 /*
1709 * Stop everything on the interface, and select page 0 registers.
1710 */
1711 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1712
1713 /*
1714 * Wait for interface to enter stopped state, but limit # of checks to
1715 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1716 * just in case it's an old one.
1717 */
1718 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1719}
1720
1721/*
1722 * Device timeout/watchdog routine. Entered if the device neglects to
1723 * generate an interrupt after a transmit has been started on it.
1724 */
1725static void
1726ed_watchdog(ifp)
1727 struct ifnet *ifp;
1728{
1729 struct ed_softc *sc = ifp->if_softc;
1730
1731 if (sc->gone)
1732 return;
1733 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1734 ifp->if_oerrors++;
1735
1736 ed_reset(ifp);
1737}
1738
1739/*
1740 * Initialize device.
1741 */
1742static void
1743ed_init(xsc)
1744 void *xsc;
1745{
1746 struct ed_softc *sc = xsc;
1747 struct ifnet *ifp = &sc->arpcom.ac_if;
1748 int i, s;
1749
1750 if (sc->gone)
1751 return;
1752
1753 /* address not known */
1754 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1755 return;
1756
1757 /*
1758 * Initialize the NIC in the exact order outlined in the NS manual.
1759 * This init procedure is "mandatory"...don't change what or when
1760 * things happen.
1761 */
1762 s = splimp();
1763
1764 /* reset transmitter flags */
1765 sc->xmit_busy = 0;
1766 ifp->if_timer = 0;
1767
1768 sc->txb_inuse = 0;
1769 sc->txb_new = 0;
1770 sc->txb_next_tx = 0;
1771
1772 /* This variable is used below - don't move this assignment */
1773 sc->next_packet = sc->rec_page_start + 1;
1774
1775 /*
1776 * Set interface for page 0, Remote DMA complete, Stopped
1777 */
1778 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1779
1780 if (sc->isa16bit) {
1781
1782 /*
1783 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1784 * order=80x86, word-wide DMA xfers,
1785 */
1786 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1787 } else {
1788
1789 /*
1790 * Same as above, but byte-wide DMA xfers
1791 */
1792 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1793 }
1794
1795 /*
1796 * Clear Remote Byte Count Registers
1797 */
1798 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1799 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1800
1801 /*
1802 * For the moment, don't store incoming packets in memory.
1803 */
1804 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1805
1806 /*
1807 * Place NIC in internal loopback mode
1808 */
1809 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1810
1811 /*
1812 * Initialize transmit/receive (ring-buffer) Page Start
1813 */
1814 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1815 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1816 /* Set lower bits of byte addressable framing to 0 */
1817 if (sc->is790)
1818 outb(sc->nic_addr + 0x09, 0);
1819
1820 /*
1821 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1822 */
1823 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1824 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1825
1826 /*
1827 * Clear all interrupts. A '1' in each bit position clears the
1828 * corresponding flag.
1829 */
1830 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1831
1832 /*
1833 * Enable the following interrupts: receive/transmit complete,
1834 * receive/transmit error, and Receiver OverWrite.
1835 *
1836 * Counter overflow and Remote DMA complete are *not* enabled.
1837 */
1838 outb(sc->nic_addr + ED_P0_IMR,
1839 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1840
1841 /*
1842 * Program Command Register for page 1
1843 */
1844 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1845
1846 /*
1847 * Copy out our station address
1848 */
1849 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1850 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1851
1852 /*
1853 * Set Current Page pointer to next_packet (initialized above)
1854 */
1855 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1856
1857 /*
1858 * Program Receiver Configuration Register and multicast filter. CR is
1859 * set to page 0 on return.
1860 */
1861 ed_setrcr(sc);
1862
1863 /*
1864 * Take interface out of loopback
1865 */
1866 outb(sc->nic_addr + ED_P0_TCR, 0);
1867
1868 /*
1869 * If this is a 3Com board, the tranceiver must be software enabled
1870 * (there is no settable hardware default).
1871 */
1872 if (sc->vendor == ED_VENDOR_3COM) {
1873 if (ifp->if_flags & IFF_ALTPHYS) {
1874 outb(sc->asic_addr + ED_3COM_CR, 0);
1875 } else {
1876 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1877 }
1878 }
1879
1880 /*
1881 * Set 'running' flag, and clear output active flag.
1882 */
1883 ifp->if_flags |= IFF_RUNNING;
1884 ifp->if_flags &= ~IFF_OACTIVE;
1885
1886 /*
1887 * ...and attempt to start output
1888 */
1889 ed_start(ifp);
1890
1891 (void) splx(s);
1892}
1893
1894/*
1895 * This routine actually starts the transmission on the interface
1896 */
1897static __inline void
1898ed_xmit(sc)
1899 struct ed_softc *sc;
1900{
1901 struct ifnet *ifp = (struct ifnet *)sc;
1902 unsigned short len;
1903
1904 if (sc->gone)
1905 return;
1906 len = sc->txb_len[sc->txb_next_tx];
1907
1908 /*
1909 * Set NIC for page 0 register access
1910 */
1911 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
1912
1913 /*
1914 * Set TX buffer start page
1915 */
1916 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1917 sc->txb_next_tx * ED_TXBUF_SIZE);
1918
1919 /*
1920 * Set TX length
1921 */
1922 outb(sc->nic_addr + ED_P0_TBCR0, len);
1923 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1924
1925 /*
1926 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1927 */
1928 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1929 sc->xmit_busy = 1;
1930
1931 /*
1932 * Point to next transmit buffer slot and wrap if necessary.
1933 */
1934 sc->txb_next_tx++;
1935 if (sc->txb_next_tx == sc->txb_cnt)
1936 sc->txb_next_tx = 0;
1937
1938 /*
1939 * Set a timer just in case we never hear from the board again
1940 */
1941 ifp->if_timer = 2;
1942}
1943
1944/*
1945 * Start output on interface.
1946 * We make two assumptions here:
1947 * 1) that the current priority is set to splimp _before_ this code
1948 * is called *and* is returned to the appropriate priority after
1949 * return
1950 * 2) that the IFF_OACTIVE flag is checked before this code is called
1951 * (i.e. that the output part of the interface is idle)
1952 */
1953static void
1954ed_start(ifp)
1955 struct ifnet *ifp;
1956{
1957 struct ed_softc *sc = ifp->if_softc;
1958 struct mbuf *m0, *m;
1959 caddr_t buffer;
1960 int len;
1961
1962 if (sc->gone) {
1963 printf("ed_start(%p) GONE\n",ifp);
1964 return;
1965 }
1966outloop:
1967
1968 /*
1969 * First, see if there are buffered packets and an idle transmitter -
1970 * should never happen at this point.
1971 */
1972 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1973 printf("ed: packets buffered, but transmitter idle\n");
1974 ed_xmit(sc);
1975 }
1976
1977 /*
1978 * See if there is room to put another packet in the buffer.
1979 */
1980 if (sc->txb_inuse == sc->txb_cnt) {
1981
1982 /*
1983 * No room. Indicate this to the outside world and exit.
1984 */
1985 ifp->if_flags |= IFF_OACTIVE;
1986 return;
1987 }
1988 IF_DEQUEUE(&ifp->if_snd, m);
1989 if (m == 0) {
1990
1991 /*
1992 * We are using the !OACTIVE flag to indicate to the outside
1993 * world that we can accept an additional packet rather than
1994 * that the transmitter is _actually_ active. Indeed, the
1995 * transmitter may be active, but if we haven't filled all the
1996 * buffers with data then we still want to accept more.
1997 */
1998 ifp->if_flags &= ~IFF_OACTIVE;
1999 return;
2000 }
2001
2002 /*
2003 * Copy the mbuf chain into the transmit buffer
2004 */
2005
2006 m0 = m;
2007
2008 /* txb_new points to next open buffer slot */
2009 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2010
2011 if (sc->mem_shared) {
2012
2013 /*
2014 * Special case setup for 16 bit boards...
2015 */
2016 if (sc->isa16bit) {
2017 switch (sc->vendor) {
2018
2019 /*
2020 * For 16bit 3Com boards (which have 16k of
2021 * memory), we have the xmit buffers in a
2022 * different page of memory ('page 0') - so
2023 * change pages.
2024 */
2025 case ED_VENDOR_3COM:
2026 outb(sc->asic_addr + ED_3COM_GACFR,
2027 ED_3COM_GACFR_RSEL);
2028 break;
2029
2030 /*
2031 * Enable 16bit access to shared memory on
2032 * WD/SMC boards.
2033 */
2034 case ED_VENDOR_WD_SMC:{
2035 outb(sc->asic_addr + ED_WD_LAAR,
2036 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2037 if (sc->is790) {
2038 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
2039 }
2040 break;
2041 }
2042 }
2043 }
2044 for (len = 0; m != 0; m = m->m_next) {
2045 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2046 buffer += m->m_len;
2047 len += m->m_len;
2048 }
2049
2050 /*
2051 * Restore previous shared memory access
2052 */
2053 if (sc->isa16bit) {
2054 switch (sc->vendor) {
2055 case ED_VENDOR_3COM:
2056 outb(sc->asic_addr + ED_3COM_GACFR,
2057 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2058 break;
2059 case ED_VENDOR_WD_SMC:{
2060 if (sc->is790) {
2061 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2062 }
2063 outb(sc->asic_addr + ED_WD_LAAR,
2064 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2065 break;
2066 }
2067 }
2068 }
2069 } else {
2070 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2071 if (len == 0)
2072 goto outloop;
2073 }
2074
2075 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2076
2077 sc->txb_inuse++;
2078
2079 /*
2080 * Point to next buffer slot and wrap if necessary.
2081 */
2082 sc->txb_new++;
2083 if (sc->txb_new == sc->txb_cnt)
2084 sc->txb_new = 0;
2085
2086 if (sc->xmit_busy == 0)
2087 ed_xmit(sc);
2088
2089 /*
2090 * Tap off here if there is a bpf listener.
2091 */
2092 if (ifp->if_bpf) {
2093 bpf_mtap(ifp, m0);
2094 }
2095
2096 m_freem(m0);
2097
2098 /*
2099 * Loop back to the top to possibly buffer more packets
2100 */
2101 goto outloop;
2102}
2103
2104/*
2105 * Ethernet interface receiver interrupt.
2106 */
2107static __inline void
2108ed_rint(sc)
2109 struct ed_softc *sc;
2110{
2111 struct ifnet *ifp = &sc->arpcom.ac_if;
2112 u_char boundry;
2113 u_short len;
2114 struct ed_ring packet_hdr;
2115 char *packet_ptr;
2116
2117 if (sc->gone)
2118 return;
2119
2120 /*
2121 * Set NIC to page 1 registers to get 'current' pointer
2122 */
2123 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2124
2125 /*
2126 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2127 * i.e. it points to where new data has been buffered. The 'CURR'
2128 * (current) register points to the logical end of the ring-buffer -
2129 * i.e. it points to where additional new data will be added. We loop
2130 * here until the logical beginning equals the logical end (or in
2131 * other words, until the ring-buffer is empty).
2132 */
2133 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
2134
2135 /* get pointer to this buffer's header structure */
2136 packet_ptr = sc->mem_ring +
2137 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2138
2139 /*
2140 * The byte count includes a 4 byte header that was added by
2141 * the NIC.
2142 */
2143 if (sc->mem_shared)
2144 packet_hdr = *(struct ed_ring *) packet_ptr;
2145 else
2146 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2147 sizeof(packet_hdr));
2148 len = packet_hdr.count;
2149 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2150 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2151 /*
2152 * Length is a wild value. There's a good chance that
2153 * this was caused by the NIC being old and buggy.
2154 * The bug is that the length low byte is duplicated in
2155 * the high byte. Try to recalculate the length based on
2156 * the pointer to the next packet.
2157 */
2158 /*
2159 * NOTE: sc->next_packet is pointing at the current packet.
2160 */
2161 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2162 if (packet_hdr.next_packet >= sc->next_packet) {
2163 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2164 } else {
2165 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2166 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2167 }
2168 /*
2169 * because buffers are aligned on 256-byte boundary,
2170 * the length computed above is off by 256 in almost
2171 * all cases. Fix it...
2172 */
2173 if (len & 0xff)
2174 len -= 256 ;
2175 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2176 + sizeof(struct ed_ring)))
2177 sc->mibdata.dot3StatsFrameTooLongs++;
2178 }
2179 /*
2180 * Be fairly liberal about what we allow as a "reasonable" length
2181 * so that a [crufty] packet will make it to BPF (and can thus
2182 * be analyzed). Note that all that is really important is that
2183 * we have a length that will fit into one mbuf cluster or less;
2184 * the upper layer protocols can then figure out the length from
2185 * their own length field(s).
2186 */
2187 if ((len > sizeof(struct ed_ring)) &&
2188 (len <= MCLBYTES) &&
2189 (packet_hdr.next_packet >= sc->rec_page_start) &&
2190 (packet_hdr.next_packet < sc->rec_page_stop)) {
2191 /*
2192 * Go get packet.
2193 */
2194 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2195 len - sizeof(struct ed_ring));
2196 ifp->if_ipackets++;
2197 } else {
2198 /*
2199 * Really BAD. The ring pointers are corrupted.
2200 */
2201 log(LOG_ERR,
2202 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2203 ifp->if_unit, len);
2204 ifp->if_ierrors++;
2205 ed_reset(ifp);
2206 return;
2207 }
2208
2209 /*
2210 * Update next packet pointer
2211 */
2212 sc->next_packet = packet_hdr.next_packet;
2213
2214 /*
2215 * Update NIC boundry pointer - being careful to keep it one
2216 * buffer behind. (as recommended by NS databook)
2217 */
2218 boundry = sc->next_packet - 1;
2219 if (boundry < sc->rec_page_start)
2220 boundry = sc->rec_page_stop - 1;
2221
2222 /*
2223 * Set NIC to page 0 registers to update boundry register
2224 */
2225 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2226
2227 outb(sc->nic_addr + ED_P0_BNRY, boundry);
2228
2229 /*
2230 * Set NIC to page 1 registers before looping to top (prepare
2231 * to get 'CURR' current pointer)
2232 */
2233 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2234 }
2235}
2236
2237/*
2238 * Ethernet interface interrupt processor
2239 */
2240void
2241edintr(arg)
2242 void *arg;
2243{
2244 struct ed_softc *sc = (struct ed_softc*) arg;
2245 struct ifnet *ifp = (struct ifnet *)sc;
2246 u_char isr;
2247
2248 if (sc->gone)
2249 return;
2250 /*
2251 * Set NIC to page 0 registers
2252 */
2253 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2254
2255 /*
2256 * loop until there are no more new interrupts
2257 */
2258 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
2259
2260 /*
2261 * reset all the bits that we are 'acknowledging' by writing a
2262 * '1' to each bit position that was set (writing a '1'
2263 * *clears* the bit)
2264 */
2265 outb(sc->nic_addr + ED_P0_ISR, isr);
2266
2267 /*
2268 * Handle transmitter interrupts. Handle these first because
2269 * the receiver will reset the board under some conditions.
2270 */
2271 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2272 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
2273
2274 /*
2275 * Check for transmit error. If a TX completed with an
2276 * error, we end up throwing the packet away. Really
2277 * the only error that is possible is excessive
2278 * collisions, and in this case it is best to allow
2279 * the automatic mechanisms of TCP to backoff the
2280 * flow. Of course, with UDP we're screwed, but this
2281 * is expected when a network is heavily loaded.
2282 */
2283 (void) inb(sc->nic_addr + ED_P0_TSR);
2284 if (isr & ED_ISR_TXE) {
2285 u_char tsr;
2286
2287 /*
2288 * Excessive collisions (16)
2289 */
2290 tsr = inb(sc->nic_addr + ED_P0_TSR);
2291 if ((tsr & ED_TSR_ABT)
2292 && (collisions == 0)) {
2293
2294 /*
2295 * When collisions total 16, the
2296 * P0_NCR will indicate 0, and the
2297 * TSR_ABT is set.
2298 */
2299 collisions = 16;
2300 sc->mibdata.dot3StatsExcessiveCollisions++;
2301 sc->mibdata.dot3StatsCollFrequencies[15]++;
2302 }
2303 if (tsr & ED_TSR_OWC)
2304 sc->mibdata.dot3StatsLateCollisions++;
2305 if (tsr & ED_TSR_CDH)
2306 sc->mibdata.dot3StatsSQETestErrors++;
2307 if (tsr & ED_TSR_CRS)
2308 sc->mibdata.dot3StatsCarrierSenseErrors++;
2309 if (tsr & ED_TSR_FU)
2310 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2311
2312 /*
2313 * update output errors counter
2314 */
2315 ifp->if_oerrors++;
2316 } else {
2317
2318 /*
2319 * Update total number of successfully
2320 * transmitted packets.
2321 */
2322 ifp->if_opackets++;
2323 }
2324
2325 /*
2326 * reset tx busy and output active flags
2327 */
2328 sc->xmit_busy = 0;
2329 ifp->if_flags &= ~IFF_OACTIVE;
2330
2331 /*
2332 * clear watchdog timer
2333 */
2334 ifp->if_timer = 0;
2335
2336 /*
2337 * Add in total number of collisions on last
2338 * transmission.
2339 */
2340 ifp->if_collisions += collisions;
2341 switch(collisions) {
2342 case 0:
2343 case 16:
2344 break;
2345 case 1:
2346 sc->mibdata.dot3StatsSingleCollisionFrames++;
2347 sc->mibdata.dot3StatsCollFrequencies[0]++;
2348 break;
2349 default:
2350 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2351 sc->mibdata.
2352 dot3StatsCollFrequencies[collisions-1]
2353 ++;
2354 break;
2355 }
2356
2357 /*
2358 * Decrement buffer in-use count if not zero (can only
2359 * be zero if a transmitter interrupt occured while
2360 * not actually transmitting). If data is ready to
2361 * transmit, start it transmitting, otherwise defer
2362 * until after handling receiver
2363 */
2364 if (sc->txb_inuse && --sc->txb_inuse)
2365 ed_xmit(sc);
2366 }
2367
2368 /*
2369 * Handle receiver interrupts
2370 */
2371 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2372
2373 /*
2374 * Overwrite warning. In order to make sure that a
2375 * lockup of the local DMA hasn't occurred, we reset
2376 * and re-init the NIC. The NSC manual suggests only a
2377 * partial reset/re-init is necessary - but some chips
2378 * seem to want more. The DMA lockup has been seen
2379 * only with early rev chips - Methinks this bug was
2380 * fixed in later revs. -DG
2381 */
2382 if (isr & ED_ISR_OVW) {
2383 ifp->if_ierrors++;
2384#ifdef DIAGNOSTIC
2385 log(LOG_WARNING,
2386 "ed%d: warning - receiver ring buffer overrun\n",
2387 ifp->if_unit);
2388#endif
2389
2390 /*
2391 * Stop/reset/re-init NIC
2392 */
2393 ed_reset(ifp);
2394 } else {
2395
2396 /*
2397 * Receiver Error. One or more of: CRC error,
2398 * frame alignment error FIFO overrun, or
2399 * missed packet.
2400 */
2401 if (isr & ED_ISR_RXE) {
2402 u_char rsr;
2403 rsr = inb(sc->nic_addr + ED_P0_RSR);
2404 if (rsr & ED_RSR_CRC)
2405 sc->mibdata.dot3StatsFCSErrors++;
2406 if (rsr & ED_RSR_FAE)
2407 sc->mibdata.dot3StatsAlignmentErrors++;
2408 if (rsr & ED_RSR_FO)
2409 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2410 ifp->if_ierrors++;
2411#ifdef ED_DEBUG
2412 printf("ed%d: receive error %x\n", ifp->if_unit,
2413 inb(sc->nic_addr + ED_P0_RSR));
2414#endif
2415 }
2416
2417 /*
2418 * Go get the packet(s) XXX - Doing this on an
2419 * error is dubious because there shouldn't be
2420 * any data to get (we've configured the
2421 * interface to not accept packets with
2422 * errors).
2423 */
2424
2425 /*
2426 * Enable 16bit access to shared memory first
2427 * on WD/SMC boards.
2428 */
2429 if (sc->isa16bit &&
2430 (sc->vendor == ED_VENDOR_WD_SMC)) {
2431
2432 outb(sc->asic_addr + ED_WD_LAAR,
2433 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2434 if (sc->is790) {
2435 outb(sc->asic_addr + ED_WD_MSR,
2436 ED_WD_MSR_MENB);
2437 }
2438 }
2439 ed_rint(sc);
2440
2441 /* disable 16bit access */
2442 if (sc->isa16bit &&
2443 (sc->vendor == ED_VENDOR_WD_SMC)) {
2444
2445 if (sc->is790) {
2446 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2447 }
2448 outb(sc->asic_addr + ED_WD_LAAR,
2449 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2450 }
2451 }
2452 }
2453
2454 /*
2455 * If it looks like the transmitter can take more data,
2456 * attempt to start output on the interface. This is done
2457 * after handling the receiver to give the receiver priority.
2458 */
2459 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2460 ed_start(ifp);
2461
2462 /*
2463 * return NIC CR to standard state: page 0, remote DMA
2464 * complete, start (toggling the TXP bit off, even if was just
2465 * set in the transmit routine, is *okay* - it is 'edge'
2466 * triggered from low to high)
2467 */
2468 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2469
2470 /*
2471 * If the Network Talley Counters overflow, read them to reset
2472 * them. It appears that old 8390's won't clear the ISR flag
2473 * otherwise - resulting in an infinite loop.
2474 */
2475 if (isr & ED_ISR_CNT) {
2476 (void) inb(sc->nic_addr + ED_P0_CNTR0);
2477 (void) inb(sc->nic_addr + ED_P0_CNTR1);
2478 (void) inb(sc->nic_addr + ED_P0_CNTR2);
2479 }
2480 }
2481}
2482
2483/*
2484 * Process an ioctl request. This code needs some work - it looks
2485 * pretty ugly.
2486 */
2487static int
2488ed_ioctl(ifp, command, data)
2489 register struct ifnet *ifp;
2490 u_long command;
2491 caddr_t data;
2492{
2493 struct ed_softc *sc = ifp->if_softc;
2494 int s, error = 0;
2495
2496 if (sc == NULL || sc->gone) {
2497 ifp->if_flags &= ~IFF_RUNNING;
2498 return ENXIO;
2499 }
2500 s = splimp();
2501
2502 switch (command) {
2503
2504 case SIOCSIFADDR:
2505 case SIOCGIFADDR:
2506 case SIOCSIFMTU:
2507 error = ether_ioctl(ifp, command, data);
2508 break;
2509
2510 case SIOCSIFFLAGS:
2511
2512 /*
2513 * If the interface is marked up and stopped, then start it.
2514 * If it is marked down and running, then stop it.
2515 */
2516 if (ifp->if_flags & IFF_UP) {
2517 if ((ifp->if_flags & IFF_RUNNING) == 0)
2518 ed_init(sc);
2519 } else {
2520 if (ifp->if_flags & IFF_RUNNING) {
2521 ed_stop(sc);
2522 ifp->if_flags &= ~IFF_RUNNING;
2523 }
2524 }
2525
2526 /*
2527 * Promiscuous flag may have changed, so reprogram the RCR.
2528 */
2529 ed_setrcr(sc);
2530
2531 /*
2532 * An unfortunate hack to provide the (required) software
2533 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2534 * disables the tranceiver if set.
2535 */
2536 if (sc->vendor == ED_VENDOR_3COM) {
2537 if (ifp->if_flags & IFF_ALTPHYS) {
2538 outb(sc->asic_addr + ED_3COM_CR, 0);
2539 } else {
2540 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2541 }
2542 } else if (sc->vendor == ED_VENDOR_HP)
2543 ed_hpp_set_physical_link(sc);
2544 break;
2545
2546 case SIOCADDMULTI:
2547 case SIOCDELMULTI:
2548 /*
2549 * Multicast list has changed; set the hardware filter
2550 * accordingly.
2551 */
2552 ed_setrcr(sc);
2553 error = 0;
2554 break;
2555
2556 default:
2557 error = EINVAL;
2558 }
2559 (void) splx(s);
2560 return (error);
2561}
2562
2563/*
2564 * Given a source and destination address, copy 'amount' of a packet from
2565 * the ring buffer into a linear destination buffer. Takes into account
2566 * ring-wrap.
2567 */
2568static __inline char *
2569ed_ring_copy(sc, src, dst, amount)
2570 struct ed_softc *sc;
2571 char *src;
2572 char *dst;
2573 u_short amount;
2574{
2575 u_short tmp_amount;
2576
2577 /* does copy wrap to lower addr in ring buffer? */
2578 if (src + amount > sc->mem_end) {
2579 tmp_amount = sc->mem_end - src;
2580
2581 /* copy amount up to end of NIC memory */
2582 if (sc->mem_shared)
2583 bcopy(src, dst, tmp_amount);
2584 else
2585 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2586
2587 amount -= tmp_amount;
2588 src = sc->mem_ring;
2589 dst += tmp_amount;
2590 }
2591 if (sc->mem_shared)
2592 bcopy(src, dst, amount);
2593 else
2594 ed_pio_readmem(sc, (int)src, dst, amount);
2595
2596 return (src + amount);
2597}
2598
2599/*
2600 * Retreive packet from shared memory and send to the next level up via
2601 * ether_input().
2602 */
2603static void
2604ed_get_packet(sc, buf, len)
2605 struct ed_softc *sc;
2606 char *buf;
2607 u_short len;
2608{
2609 struct ether_header *eh;
2610 struct mbuf *m;
2611
2612 /* Allocate a header mbuf */
2613 MGETHDR(m, M_DONTWAIT, MT_DATA);
2614 if (m == NULL)
2615 return;
2616 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2617 m->m_pkthdr.len = m->m_len = len;
2618
2619 /*
2620 * We always put the received packet in a single buffer -
2621 * either with just an mbuf header or in a cluster attached
2622 * to the header. The +2 is to compensate for the alignment
2623 * fixup below.
2624 */
2625 if ((len + 2) > MHLEN) {
2626 /* Attach an mbuf cluster */
2627 MCLGET(m, M_DONTWAIT);
2628
2629 /* Insist on getting a cluster */
2630 if ((m->m_flags & M_EXT) == 0) {
2631 m_freem(m);
2632 return;
2633 }
2634 }
2635
2636 /*
2637 * The +2 is to longword align the start of the real packet.
2638 * This is important for NFS.
2639 */
2640 m->m_data += 2;
2641 eh = mtod(m, struct ether_header *);
2642
2643#ifdef BRIDGE
2644 /*
2645 * Don't read in the entire packet if we know we're going to drop it
2646 */
2647 if (do_bridge) {
2648 struct ifnet *bif;
2649
2650 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2651 if ((bif = bridge_in(&sc->arpcom.ac_if, eh)) == BDG_DROP) {
2652 m_freem(m);
2653 return;
2654 }
2655 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2656 (char *)eh + ETHER_HDR_LEN, len - ETHER_HDR_LEN);
2657 } else
2658#endif
2659 /*
2660 * Get packet, including link layer address, from interface.
2661 */
2662 ed_ring_copy(sc, buf, (char *)eh, len);
2663
2664 /*
2665 * Remove link layer address.
2666 */
2667 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2668 m->m_data += sizeof(struct ether_header);
2669
2670 ether_input(&sc->arpcom.ac_if, eh, m);
2671}
2672
2673/*
2674 * Supporting routines
2675 */
2676
2677/*
2678 * Given a NIC memory source address and a host memory destination
2679 * address, copy 'amount' from NIC to host using Programmed I/O.
2680 * The 'amount' is rounded up to a word - okay as long as mbufs
2681 * are word sized.
2682 * This routine is currently Novell-specific.
2683 */
2684static void
2685ed_pio_readmem(sc, src, dst, amount)
2686 struct ed_softc *sc;
2687 int src;
2688 unsigned char *dst;
2689 unsigned short amount;
2690{
2691 /* HP cards need special handling */
2692 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2693 ed_hpp_readmem(sc, src, dst, amount);
2694 return;
2695 }
2696
2697 /* Regular Novell cards */
2698 /* select page 0 registers */
2699 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2700
2701 /* round up to a word */
2702 if (amount & 1)
2703 ++amount;
2704
2705 /* set up DMA byte count */
2706 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2707 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
2708
2709 /* set up source address in NIC mem */
2710 outb(sc->nic_addr + ED_P0_RSAR0, src);
2711 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
2712
2713 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2714
2715 if (sc->isa16bit) {
2716 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
2717 } else
2718 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2719
2720}
2721
2722/*
2723 * Stripped down routine for writing a linear buffer to NIC memory.
2724 * Only used in the probe routine to test the memory. 'len' must
2725 * be even.
2726 */
2727static void
2728ed_pio_writemem(sc, src, dst, len)
2729 struct ed_softc *sc;
2730 char *src;
2731 unsigned short dst;
2732 unsigned short len;
2733{
2734 int maxwait = 200; /* about 240us */
2735
2736 if (sc->vendor == ED_VENDOR_NOVELL) {
2737
2738 /* select page 0 registers */
2739 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2740
2741 /* reset remote DMA complete flag */
2742 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2743
2744 /* set up DMA byte count */
2745 outb(sc->nic_addr + ED_P0_RBCR0, len);
2746 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
2747
2748 /* set up destination address in NIC mem */
2749 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2750 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2751
2752 /* set remote DMA write */
2753 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2754
2755 if (sc->isa16bit)
2756 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
2757 else
2758 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2759
2760 /*
2761 * Wait for remote DMA complete. This is necessary because on the
2762 * transmit side, data is handled internally by the NIC in bursts and
2763 * we can't start another remote DMA until this one completes. Not
2764 * waiting causes really bad things to happen - like the NIC
2765 * irrecoverably jamming the ISA bus.
2766 */
2767 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2768
2769 } else if ((sc->vendor == ED_VENDOR_HP) &&
2770 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2771
2772 /* HP PCLAN+ */
2773
2774 /* reset remote DMA complete flag */
2775 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2776
2777 /* program the write address in RAM */
2778 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
2779
2780 if (sc->hpp_mem_start) {
2781 u_short *s = (u_short *) src;
2782 volatile u_short *d = (u_short *) sc->hpp_mem_start;
2783 u_short *const fence = s + (len >> 1);
2784
2785 /*
2786 * Enable memory mapped access.
2787 */
2788
2789 outw(sc->asic_addr + ED_HPP_OPTION,
2790 sc->hpp_options &
2791 ~(ED_HPP_OPTION_MEM_DISABLE |
2792 ED_HPP_OPTION_BOOT_ROM_ENB));
2793
2794 /*
2795 * Copy to NIC memory.
2796 */
2797
2798 while (s < fence)
2799 *d = *s++;
2800
2801 /*
2802 * Restore Boot ROM access.
2803 */
2804
2805 outw(sc->asic_addr + ED_HPP_OPTION,
2806 sc->hpp_options);
2807
2808 } else {
2809 /* write data using I/O writes */
2810 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
2811 }
2812
2813 }
2814}
2815
2816/*
2817 * Write an mbuf chain to the destination NIC memory address using
2818 * programmed I/O.
2819 */
2820static u_short
2821ed_pio_write_mbufs(sc, m, dst)
2822 struct ed_softc *sc;
2823 struct mbuf *m;
2824 int dst;
2825{
2826 struct ifnet *ifp = (struct ifnet *)sc;
2827 unsigned short total_len, dma_len;
2828 struct mbuf *mp;
2829 int maxwait = 200; /* about 240us */
2830
2831 /* HP PC Lan+ cards need special handling */
2832 if ((sc->vendor == ED_VENDOR_HP) &&
2833 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2834 return ed_hpp_write_mbufs(sc, m, dst);
2835 }
2836
2837 /* First, count up the total number of bytes to copy */
2838 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2839 total_len += mp->m_len;
2840
2841 dma_len = total_len;
2842 if (sc->isa16bit && (dma_len & 1))
2843 dma_len++;
2844
2845 /* select page 0 registers */
2846 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2847
2848 /* reset remote DMA complete flag */
2849 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2850
2851 /* set up DMA byte count */
2852 outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
2853 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
2854
2855 /* set up destination address in NIC mem */
2856 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2857 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2858
2859 /* set remote DMA write */
2860 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2861
2862 /*
2863 * Transfer the mbuf chain to the NIC memory.
2864 * 16-bit cards require that data be transferred as words, and only words.
2865 * So that case requires some extra code to patch over odd-length mbufs.
2866 */
2867
2868 if (!sc->isa16bit) {
2869 /* NE1000s are easy */
2870 while (m) {
2871 if (m->m_len) {
2872 outsb(sc->asic_addr + ED_NOVELL_DATA,
2873 m->m_data, m->m_len);
2874 }
2875 m = m->m_next;
2876 }
2877 } else {
2878 /* NE2000s are a pain */
2879 unsigned char *data;
2880 int len, wantbyte;
2881 unsigned char savebyte[2];
2882
2883 wantbyte = 0;
2884
2885 while (m) {
2886 len = m->m_len;
2887 if (len) {
2888 data = mtod(m, caddr_t);
2889 /* finish the last word */
2890 if (wantbyte) {
2891 savebyte[1] = *data;
2892 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
2893 data++;
2894 len--;
2895 wantbyte = 0;
2896 }
2897 /* output contiguous words */
2898 if (len > 1) {
2899 outsw(sc->asic_addr + ED_NOVELL_DATA,
2900 data, len >> 1);
2901 data += len & ~1;
2902 len &= 1;
2903 }
2904 /* save last byte, if necessary */
2905 if (len == 1) {
2906 savebyte[0] = *data;
2907 wantbyte = 1;
2908 }
2909 }
2910 m = m->m_next;
2911 }
2912 /* spit last byte */
2913 if (wantbyte) {
2914 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
2915 }
2916 }
2917
2918 /*
2919 * Wait for remote DMA complete. This is necessary because on the
2920 * transmit side, data is handled internally by the NIC in bursts and
2921 * we can't start another remote DMA until this one completes. Not
2922 * waiting causes really bad things to happen - like the NIC
2923 * irrecoverably jamming the ISA bus.
2924 */
2925 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2926
2927 if (!maxwait) {
2928 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2929 ifp->if_unit);
2930 ed_reset(ifp);
2931 return(0);
2932 }
2933 return (total_len);
2934}
2935
2936/*
2937 * Support routines to handle the HP PC Lan+ card.
2938 */
2939
2940/*
2941 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2942 * IO.
2943 */
2944
2945static void
2946ed_hpp_readmem(sc, src, dst, amount)
2947 struct ed_softc *sc;
2948 unsigned short src;
2949 unsigned char *dst;
2950 unsigned short amount;
2951{
2952
2953 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2954
2955
2956 /* Program the source address in RAM */
2957 outw(sc->asic_addr + ED_HPP_PAGE_2, src);
2958
2959 /*
2960 * The HP PC Lan+ card supports word reads as well as
2961 * a memory mapped i/o port that is aliased to every
2962 * even address on the board.
2963 */
2964
2965 if (sc->hpp_mem_start) {
2966
2967 /* Enable memory mapped access. */
2968 outw(sc->asic_addr + ED_HPP_OPTION,
2969 sc->hpp_options &
2970 ~(ED_HPP_OPTION_MEM_DISABLE |
2971 ED_HPP_OPTION_BOOT_ROM_ENB));
2972
2973 if (use_32bit_access && (amount > 3)) {
2974 u_long *dl = (u_long *) dst;
2975 volatile u_long *const sl =
2976 (u_long *) sc->hpp_mem_start;
2977 u_long *const fence = dl + (amount >> 2);
2978
2979 /* Copy out NIC data. We could probably write this
2980 as a `movsl'. The currently generated code is lousy.
2981 */
2982
2983 while (dl < fence)
2984 *dl++ = *sl;
2985
2986 dst += (amount & ~3);
2987 amount &= 3;
2988
2989 }
2990
2991 /* Finish off any words left, as a series of short reads */
2992 if (amount > 1) {
2993 u_short *d = (u_short *) dst;
2994 volatile u_short *const s =
2995 (u_short *) sc->hpp_mem_start;
2996 u_short *const fence = d + (amount >> 1);
2997
2998 /* Copy out NIC data. */
2999
3000 while (d < fence)
3001 *d++ = *s;
3002
3003 dst += (amount & ~1);
3004 amount &= 1;
3005 }
3006
3007 /*
3008 * read in a byte; however we need to always read 16 bits
3009 * at a time or the hardware gets into a funny state
3010 */
3011
3012 if (amount == 1) {
3013 /* need to read in a short and copy LSB */
3014 volatile u_short *const s =
3015 (volatile u_short *) sc->hpp_mem_start;
3016
3017 *dst = (*s) & 0xFF;
3018 }
3019
3020 /* Restore Boot ROM access. */
3021
3022 outw(sc->asic_addr + ED_HPP_OPTION,
3023 sc->hpp_options);
3024
3025
3026 } else {
3027 /* Read in data using the I/O port */
3028 if (use_32bit_access && (amount > 3)) {
3029 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
3030 dst += (amount & ~3);
3031 amount &= 3;
3032 }
3033 if (amount > 1) {
3034 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
3035 dst += (amount & ~1);
3036 amount &= 1;
3037 }
3038 if (amount == 1) { /* read in a short and keep the LSB */
3039 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
3040 }
3041 }
3042}
3043
3044/*
3045 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3046 * outsw() or via the memory mapped interface to the same register.
3047 * Writes have to be in word units; byte accesses won't work and may cause
3048 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3049 * allows it.
3050 */
3051
3052static u_short
3053ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3054{
3055 int len, wantbyte;
3056 unsigned short total_len;
3057 unsigned char savebyte[2];
3058 volatile u_short * const d =
3059 (volatile u_short *) sc->hpp_mem_start;
3060 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3061
3062 /* select page 0 registers */
3063 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3064
3065 /* reset remote DMA complete flag */
3066 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
3067
3068 /* program the write address in RAM */
3069 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
3070
3071 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3072 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options &
3073 ~(ED_HPP_OPTION_MEM_DISABLE |
3074 ED_HPP_OPTION_BOOT_ROM_ENB));
3075
3076 wantbyte = 0;
3077 total_len = 0;
3078
3079 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3080 while (m) {
3081 total_len += (len = m->m_len);
3082 if (len) {
3083 caddr_t data = mtod(m, caddr_t);
3084 /* finish the last word of the previous mbuf */
3085 if (wantbyte) {
3086 savebyte[1] = *data;
3087 *d = *((ushort *) savebyte);
3088 data++; len--; wantbyte = 0;
3089 }
3090 /* output contiguous words */
3091 if ((len > 3) && (use_32bit_accesses)) {
3092 volatile u_long *const dl =
3093 (volatile u_long *) d;
3094 u_long *sl = (u_long *) data;
3095 u_long *fence = sl + (len >> 2);
3096
3097 while (sl < fence)
3098 *dl = *sl++;
3099
3100 data += (len & ~3);
3101 len &= 3;
3102 }
3103 /* finish off remain 16 bit writes */
3104 if (len > 1) {
3105 u_short *s = (u_short *) data;
3106 u_short *fence = s + (len >> 1);
3107
3108 while (s < fence)
3109 *d = *s++;
3110
3111 data += (len & ~1);
3112 len &= 1;
3113 }
3114 /* save last byte if needed */
3115 if ((wantbyte = (len == 1)) != 0)
3116 savebyte[0] = *data;
3117 }
3118 m = m->m_next; /* to next mbuf */
3119 }
3120 if (wantbyte) /* write last byte */
3121 *d = *((u_short *) savebyte);
3122 } else {
3123 /* use programmed I/O */
3124 while (m) {
3125 total_len += (len = m->m_len);
3126 if (len) {
3127 caddr_t data = mtod(m, caddr_t);
3128 /* finish the last word of the previous mbuf */
3129 if (wantbyte) {
3130 savebyte[1] = *data;
3131 outw(sc->asic_addr + ED_HPP_PAGE_4,
3132 *((u_short *)savebyte));
3133 data++;
3134 len--;
3135 wantbyte = 0;
3136 }
3137 /* output contiguous words */
3138 if ((len > 3) && use_32bit_accesses) {
3139 outsl(sc->asic_addr + ED_HPP_PAGE_4,
3140 data, len >> 2);
3141 data += (len & ~3);
3142 len &= 3;
3143 }
3144 /* finish off remaining 16 bit accesses */
3145 if (len > 1) {
3146 outsw(sc->asic_addr + ED_HPP_PAGE_4,
3147 data, len >> 1);
3148 data += (len & ~1);
3149 len &= 1;
3150 }
3151 if ((wantbyte = (len == 1)) != 0)
3152 savebyte[0] = *data;
3153
3154 } /* if len != 0 */
3155 m = m->m_next;
3156 }
3157 if (wantbyte) /* spit last byte */
3158 outw(sc->asic_addr + ED_HPP_PAGE_4,
3159 *(u_short *)savebyte);
3160
3161 }
3162
3163 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3164 outw(sc->asic_addr + ED_HPP_OPTION,
3165 sc->hpp_options);
3166
3167 return (total_len);
3168}
3169
3170static void
3171ed_setrcr(sc)
3172 struct ed_softc *sc;
3173{
3174 struct ifnet *ifp = (struct ifnet *)sc;
3175 int i;
3176
3177 /* set page 1 registers */
3178 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3179
3180 if (ifp->if_flags & IFF_PROMISC) {
3181
3182 /*
3183 * Reconfigure the multicast filter.
3184 */
3185 for (i = 0; i < 8; i++)
3186 outb(sc->nic_addr + ED_P1_MAR(i), 0xff);
3187
3188 /*
3189 * And turn on promiscuous mode. Also enable reception of
3190 * runts and packets with CRC & alignment errors.
3191 */
3192 /* Set page 0 registers */
3193 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3194
3195 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3196 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
3197 } else {
3198 /* set up multicast addresses and filter modes */
3199 if (ifp->if_flags & IFF_MULTICAST) {
3200 u_long mcaf[2];
3201
3202 if (ifp->if_flags & IFF_ALLMULTI) {
3203 mcaf[0] = 0xffffffff;
3204 mcaf[1] = 0xffffffff;
3205 } else
3206 ds_getmcaf(sc, mcaf);
3207
3208 /*
3209 * Set multicast filter on chip.
3210 */
3211 for (i = 0; i < 8; i++)
3212 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3213
3214 /* Set page 0 registers */
3215 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3216
3217 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
3218 } else {
3219
3220 /*
3221 * Initialize multicast address hashing registers to
3222 * not accept multicasts.
3223 */
3224 for (i = 0; i < 8; ++i)
3225 outb(sc->nic_addr + ED_P1_MAR(i), 0x00);
3226
3227 /* Set page 0 registers */
3228 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3229
3230 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
3231 }
3232 }
3233
3234 /*
3235 * Start interface.
3236 */
3237 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3238}
3239
3240/*
3241 * Compute crc for ethernet address
3242 */
3243static u_long
3244ds_crc(ep)
3245 u_char *ep;
3246{
3247#define POLYNOMIAL 0x04c11db6
3248 register u_long crc = 0xffffffffL;
3249 register int carry, i, j;
3250 register u_char b;
3251
3252 for (i = 6; --i >= 0;) {
3253 b = *ep++;
3254 for (j = 8; --j >= 0;) {
3255 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
3256 crc <<= 1;
3257 b >>= 1;
3258 if (carry)
3259 crc = ((crc ^ POLYNOMIAL) | carry);
3260 }
3261 }
3262 return crc;
3263#undef POLYNOMIAL
3264}
3265
3266/*
3267 * Compute the multicast address filter from the
3268 * list of multicast addresses we need to listen to.
3269 */
3270static void
3271ds_getmcaf(sc, mcaf)
3272 struct ed_softc *sc;
3273 u_long *mcaf;
3274{
3275 register u_int index;
3276 register u_char *af = (u_char *) mcaf;
3277 struct ifmultiaddr *ifma;
3278
3279 mcaf[0] = 0;
3280 mcaf[1] = 0;
3281
3282 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3283 ifma = ifma->ifma_link.le_next) {
3284 if (ifma->ifma_addr->sa_family != AF_LINK)
3285 continue;
3286 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3287 >> 26;
3288 af[index >> 3] |= 1 << (index & 7);
3289 }
3290}
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