1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#include <sys/cdefs.h>
| 1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#include <sys/cdefs.h>
|
27__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/r600_blit_kms.c 254885 2013-08-25 19:37:15Z dumbbell $");
| 27__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/r600_blit_kms.c 258780 2013-11-30 22:17:27Z eadler $");
|
28
29#include <dev/drm2/drmP.h>
30#include <dev/drm2/radeon/radeon_drm.h>
31#include "radeon.h"
32#include "radeon_asic.h"
33
34#include "r600d.h"
35#include "r600_blit_shaders.h"
36#include "radeon_blit_common.h"
37
38/* emits 21 on rv770+, 23 on r600 */
39static void
40set_render_target(struct radeon_device *rdev, int format,
41 int w, int h, u64 gpu_addr)
42{
43 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
44 u32 cb_color_info;
45 int pitch, slice;
46
47 h = roundup2(h, 8);
48 if (h < 8)
49 h = 8;
50
51 cb_color_info = CB_FORMAT(format) |
52 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
53 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
54 pitch = (w / 8) - 1;
55 slice = ((w * h) / 64) - 1;
56
57 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
58 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
59 radeon_ring_write(ring, gpu_addr >> 8);
60
61 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
62 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
63 radeon_ring_write(ring, 2 << 0);
64 }
65
66 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
69
70 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
72 radeon_ring_write(ring, 0);
73
74 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75 radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76 radeon_ring_write(ring, cb_color_info);
77
78 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79 radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80 radeon_ring_write(ring, 0);
81
82 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83 radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84 radeon_ring_write(ring, 0);
85
86 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
87 radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
88 radeon_ring_write(ring, 0);
89}
90
91/* emits 5dw */
92static void
93cp_set_surface_sync(struct radeon_device *rdev,
94 u32 sync_type, u32 size,
95 u64 mc_addr)
96{
97 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
98 u32 cp_coher_size;
99
100 if (size == 0xffffffff)
101 cp_coher_size = 0xffffffff;
102 else
103 cp_coher_size = ((size + 255) >> 8);
104
105 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
106 radeon_ring_write(ring, sync_type);
107 radeon_ring_write(ring, cp_coher_size);
108 radeon_ring_write(ring, mc_addr >> 8);
109 radeon_ring_write(ring, 10); /* poll interval */
110}
111
112/* emits 21dw + 1 surface sync = 26dw */
113static void
114set_shaders(struct radeon_device *rdev)
115{
116 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
117 u64 gpu_addr;
118 u32 sq_pgm_resources;
119
120 /* setup shader regs */
121 sq_pgm_resources = (1 << 0);
122
123 /* VS */
124 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
125 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
126 radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
127 radeon_ring_write(ring, gpu_addr >> 8);
128
129 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
130 radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
131 radeon_ring_write(ring, sq_pgm_resources);
132
133 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
134 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
135 radeon_ring_write(ring, 0);
136
137 /* PS */
138 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
139 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
140 radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
141 radeon_ring_write(ring, gpu_addr >> 8);
142
143 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
144 radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
145 radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
146
147 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
148 radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
149 radeon_ring_write(ring, 2);
150
151 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
152 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
153 radeon_ring_write(ring, 0);
154
155 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
156 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
157}
158
159/* emits 9 + 1 sync (5) = 14*/
160static void
161set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
162{
163 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
164 u32 sq_vtx_constant_word2;
165
166 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
167 SQ_VTXC_STRIDE(16);
168#ifdef __BIG_ENDIAN
169 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
170#endif
171
172 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
173 radeon_ring_write(ring, 0x460);
174 radeon_ring_write(ring, gpu_addr & 0xffffffff);
175 radeon_ring_write(ring, 48 - 1);
176 radeon_ring_write(ring, sq_vtx_constant_word2);
177 radeon_ring_write(ring, 1 << 0);
178 radeon_ring_write(ring, 0);
179 radeon_ring_write(ring, 0);
180 radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
181
182 if ((rdev->family == CHIP_RV610) ||
183 (rdev->family == CHIP_RV620) ||
184 (rdev->family == CHIP_RS780) ||
185 (rdev->family == CHIP_RS880) ||
186 (rdev->family == CHIP_RV710))
187 cp_set_surface_sync(rdev,
188 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
189 else
190 cp_set_surface_sync(rdev,
191 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
192}
193
194/* emits 9 */
195static void
196set_tex_resource(struct radeon_device *rdev,
197 int format, int w, int h, int pitch,
198 u64 gpu_addr, u32 size)
199{
200 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
201 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
202
203 if (h < 1)
204 h = 1;
205
206 sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
207 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
208 sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
209 S_038000_TEX_WIDTH(w - 1);
210
211 sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
212 sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
213
214 sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
215 S_038010_DST_SEL_X(SQ_SEL_X) |
216 S_038010_DST_SEL_Y(SQ_SEL_Y) |
217 S_038010_DST_SEL_Z(SQ_SEL_Z) |
218 S_038010_DST_SEL_W(SQ_SEL_W);
219
220 cp_set_surface_sync(rdev,
221 PACKET3_TC_ACTION_ENA, size, gpu_addr);
222
223 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
224 radeon_ring_write(ring, 0);
225 radeon_ring_write(ring, sq_tex_resource_word0);
226 radeon_ring_write(ring, sq_tex_resource_word1);
227 radeon_ring_write(ring, gpu_addr >> 8);
228 radeon_ring_write(ring, gpu_addr >> 8);
229 radeon_ring_write(ring, sq_tex_resource_word4);
230 radeon_ring_write(ring, 0);
231 radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
232}
233
234/* emits 12 */
235static void
236set_scissors(struct radeon_device *rdev, int x1, int y1,
237 int x2, int y2)
238{
239 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
240 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
241 radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
242 radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
243 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
244
245 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
246 radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
| 28
29#include <dev/drm2/drmP.h>
30#include <dev/drm2/radeon/radeon_drm.h>
31#include "radeon.h"
32#include "radeon_asic.h"
33
34#include "r600d.h"
35#include "r600_blit_shaders.h"
36#include "radeon_blit_common.h"
37
38/* emits 21 on rv770+, 23 on r600 */
39static void
40set_render_target(struct radeon_device *rdev, int format,
41 int w, int h, u64 gpu_addr)
42{
43 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
44 u32 cb_color_info;
45 int pitch, slice;
46
47 h = roundup2(h, 8);
48 if (h < 8)
49 h = 8;
50
51 cb_color_info = CB_FORMAT(format) |
52 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
53 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
54 pitch = (w / 8) - 1;
55 slice = ((w * h) / 64) - 1;
56
57 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
58 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
59 radeon_ring_write(ring, gpu_addr >> 8);
60
61 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
62 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
63 radeon_ring_write(ring, 2 << 0);
64 }
65
66 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
69
70 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
72 radeon_ring_write(ring, 0);
73
74 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75 radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76 radeon_ring_write(ring, cb_color_info);
77
78 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79 radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80 radeon_ring_write(ring, 0);
81
82 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83 radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84 radeon_ring_write(ring, 0);
85
86 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
87 radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
88 radeon_ring_write(ring, 0);
89}
90
91/* emits 5dw */
92static void
93cp_set_surface_sync(struct radeon_device *rdev,
94 u32 sync_type, u32 size,
95 u64 mc_addr)
96{
97 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
98 u32 cp_coher_size;
99
100 if (size == 0xffffffff)
101 cp_coher_size = 0xffffffff;
102 else
103 cp_coher_size = ((size + 255) >> 8);
104
105 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
106 radeon_ring_write(ring, sync_type);
107 radeon_ring_write(ring, cp_coher_size);
108 radeon_ring_write(ring, mc_addr >> 8);
109 radeon_ring_write(ring, 10); /* poll interval */
110}
111
112/* emits 21dw + 1 surface sync = 26dw */
113static void
114set_shaders(struct radeon_device *rdev)
115{
116 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
117 u64 gpu_addr;
118 u32 sq_pgm_resources;
119
120 /* setup shader regs */
121 sq_pgm_resources = (1 << 0);
122
123 /* VS */
124 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
125 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
126 radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
127 radeon_ring_write(ring, gpu_addr >> 8);
128
129 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
130 radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
131 radeon_ring_write(ring, sq_pgm_resources);
132
133 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
134 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
135 radeon_ring_write(ring, 0);
136
137 /* PS */
138 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
139 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
140 radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
141 radeon_ring_write(ring, gpu_addr >> 8);
142
143 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
144 radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
145 radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
146
147 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
148 radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
149 radeon_ring_write(ring, 2);
150
151 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
152 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
153 radeon_ring_write(ring, 0);
154
155 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
156 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
157}
158
159/* emits 9 + 1 sync (5) = 14*/
160static void
161set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
162{
163 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
164 u32 sq_vtx_constant_word2;
165
166 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
167 SQ_VTXC_STRIDE(16);
168#ifdef __BIG_ENDIAN
169 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
170#endif
171
172 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
173 radeon_ring_write(ring, 0x460);
174 radeon_ring_write(ring, gpu_addr & 0xffffffff);
175 radeon_ring_write(ring, 48 - 1);
176 radeon_ring_write(ring, sq_vtx_constant_word2);
177 radeon_ring_write(ring, 1 << 0);
178 radeon_ring_write(ring, 0);
179 radeon_ring_write(ring, 0);
180 radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
181
182 if ((rdev->family == CHIP_RV610) ||
183 (rdev->family == CHIP_RV620) ||
184 (rdev->family == CHIP_RS780) ||
185 (rdev->family == CHIP_RS880) ||
186 (rdev->family == CHIP_RV710))
187 cp_set_surface_sync(rdev,
188 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
189 else
190 cp_set_surface_sync(rdev,
191 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
192}
193
194/* emits 9 */
195static void
196set_tex_resource(struct radeon_device *rdev,
197 int format, int w, int h, int pitch,
198 u64 gpu_addr, u32 size)
199{
200 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
201 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
202
203 if (h < 1)
204 h = 1;
205
206 sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
207 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
208 sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
209 S_038000_TEX_WIDTH(w - 1);
210
211 sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
212 sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
213
214 sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
215 S_038010_DST_SEL_X(SQ_SEL_X) |
216 S_038010_DST_SEL_Y(SQ_SEL_Y) |
217 S_038010_DST_SEL_Z(SQ_SEL_Z) |
218 S_038010_DST_SEL_W(SQ_SEL_W);
219
220 cp_set_surface_sync(rdev,
221 PACKET3_TC_ACTION_ENA, size, gpu_addr);
222
223 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
224 radeon_ring_write(ring, 0);
225 radeon_ring_write(ring, sq_tex_resource_word0);
226 radeon_ring_write(ring, sq_tex_resource_word1);
227 radeon_ring_write(ring, gpu_addr >> 8);
228 radeon_ring_write(ring, gpu_addr >> 8);
229 radeon_ring_write(ring, sq_tex_resource_word4);
230 radeon_ring_write(ring, 0);
231 radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
232}
233
234/* emits 12 */
235static void
236set_scissors(struct radeon_device *rdev, int x1, int y1,
237 int x2, int y2)
238{
239 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
240 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
241 radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
242 radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
243 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
244
245 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
246 radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
247 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
| 247 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
|
248 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
249
250 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
251 radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
| 248 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
249
250 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
251 radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
|
252 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
| 252 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
|
253 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
254}
255
256/* emits 10 */
257static void
258draw_auto(struct radeon_device *rdev)
259{
260 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
261 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
262 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
263 radeon_ring_write(ring, DI_PT_RECTLIST);
264
265 radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
266 radeon_ring_write(ring,
267#ifdef __BIG_ENDIAN
268 (2 << 2) |
269#endif
270 DI_INDEX_SIZE_16_BIT);
271
272 radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
273 radeon_ring_write(ring, 1);
274
275 radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
276 radeon_ring_write(ring, 3);
277 radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
278
279}
280
281/* emits 14 */
282static void
283set_default_state(struct radeon_device *rdev)
284{
285 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
286 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
287 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
288 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
289 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
290 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
291 u64 gpu_addr;
292 int dwords;
293
294 switch (rdev->family) {
295 case CHIP_R600:
296 num_ps_gprs = 192;
297 num_vs_gprs = 56;
298 num_temp_gprs = 4;
299 num_gs_gprs = 0;
300 num_es_gprs = 0;
301 num_ps_threads = 136;
302 num_vs_threads = 48;
303 num_gs_threads = 4;
304 num_es_threads = 4;
305 num_ps_stack_entries = 128;
306 num_vs_stack_entries = 128;
307 num_gs_stack_entries = 0;
308 num_es_stack_entries = 0;
309 break;
310 case CHIP_RV630:
311 case CHIP_RV635:
312 num_ps_gprs = 84;
313 num_vs_gprs = 36;
314 num_temp_gprs = 4;
315 num_gs_gprs = 0;
316 num_es_gprs = 0;
317 num_ps_threads = 144;
318 num_vs_threads = 40;
319 num_gs_threads = 4;
320 num_es_threads = 4;
321 num_ps_stack_entries = 40;
322 num_vs_stack_entries = 40;
323 num_gs_stack_entries = 32;
324 num_es_stack_entries = 16;
325 break;
326 case CHIP_RV610:
327 case CHIP_RV620:
328 case CHIP_RS780:
329 case CHIP_RS880:
330 default:
331 num_ps_gprs = 84;
332 num_vs_gprs = 36;
333 num_temp_gprs = 4;
334 num_gs_gprs = 0;
335 num_es_gprs = 0;
336 num_ps_threads = 136;
337 num_vs_threads = 48;
338 num_gs_threads = 4;
339 num_es_threads = 4;
340 num_ps_stack_entries = 40;
341 num_vs_stack_entries = 40;
342 num_gs_stack_entries = 32;
343 num_es_stack_entries = 16;
344 break;
345 case CHIP_RV670:
346 num_ps_gprs = 144;
347 num_vs_gprs = 40;
348 num_temp_gprs = 4;
349 num_gs_gprs = 0;
350 num_es_gprs = 0;
351 num_ps_threads = 136;
352 num_vs_threads = 48;
353 num_gs_threads = 4;
354 num_es_threads = 4;
355 num_ps_stack_entries = 40;
356 num_vs_stack_entries = 40;
357 num_gs_stack_entries = 32;
358 num_es_stack_entries = 16;
359 break;
360 case CHIP_RV770:
361 num_ps_gprs = 192;
362 num_vs_gprs = 56;
363 num_temp_gprs = 4;
364 num_gs_gprs = 0;
365 num_es_gprs = 0;
366 num_ps_threads = 188;
367 num_vs_threads = 60;
368 num_gs_threads = 0;
369 num_es_threads = 0;
370 num_ps_stack_entries = 256;
371 num_vs_stack_entries = 256;
372 num_gs_stack_entries = 0;
373 num_es_stack_entries = 0;
374 break;
375 case CHIP_RV730:
376 case CHIP_RV740:
377 num_ps_gprs = 84;
378 num_vs_gprs = 36;
379 num_temp_gprs = 4;
380 num_gs_gprs = 0;
381 num_es_gprs = 0;
382 num_ps_threads = 188;
383 num_vs_threads = 60;
384 num_gs_threads = 0;
385 num_es_threads = 0;
386 num_ps_stack_entries = 128;
387 num_vs_stack_entries = 128;
388 num_gs_stack_entries = 0;
389 num_es_stack_entries = 0;
390 break;
391 case CHIP_RV710:
392 num_ps_gprs = 192;
393 num_vs_gprs = 56;
394 num_temp_gprs = 4;
395 num_gs_gprs = 0;
396 num_es_gprs = 0;
397 num_ps_threads = 144;
398 num_vs_threads = 48;
399 num_gs_threads = 0;
400 num_es_threads = 0;
401 num_ps_stack_entries = 128;
402 num_vs_stack_entries = 128;
403 num_gs_stack_entries = 0;
404 num_es_stack_entries = 0;
405 break;
406 }
407
408 if ((rdev->family == CHIP_RV610) ||
409 (rdev->family == CHIP_RV620) ||
410 (rdev->family == CHIP_RS780) ||
411 (rdev->family == CHIP_RS880) ||
412 (rdev->family == CHIP_RV710))
413 sq_config = 0;
414 else
415 sq_config = VC_ENABLE;
416
417 sq_config |= (DX9_CONSTS |
418 ALU_INST_PREFER_VECTOR |
419 PS_PRIO(0) |
420 VS_PRIO(1) |
421 GS_PRIO(2) |
422 ES_PRIO(3));
423
424 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
425 NUM_VS_GPRS(num_vs_gprs) |
426 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
427 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
428 NUM_ES_GPRS(num_es_gprs));
429 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
430 NUM_VS_THREADS(num_vs_threads) |
431 NUM_GS_THREADS(num_gs_threads) |
432 NUM_ES_THREADS(num_es_threads));
433 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
434 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
435 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
436 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
437
438 /* emit an IB pointing at default state */
439 dwords = roundup2(rdev->r600_blit.state_len, 0x10);
440 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
441 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
442 radeon_ring_write(ring,
443#ifdef __BIG_ENDIAN
444 (2 << 0) |
445#endif
446 (gpu_addr & 0xFFFFFFFC));
447 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
448 radeon_ring_write(ring, dwords);
449
450 /* SQ config */
451 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
452 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
453 radeon_ring_write(ring, sq_config);
454 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
455 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
456 radeon_ring_write(ring, sq_thread_resource_mgmt);
457 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
458 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
459}
460
461int r600_blit_init(struct radeon_device *rdev)
462{
463 u32 obj_size;
464 int i, r, dwords;
465 void *ptr;
466 u32 packet2s[16];
467 int num_packet2s = 0;
468
469 rdev->r600_blit.primitives.set_render_target = set_render_target;
470 rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
471 rdev->r600_blit.primitives.set_shaders = set_shaders;
472 rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
473 rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
474 rdev->r600_blit.primitives.set_scissors = set_scissors;
475 rdev->r600_blit.primitives.draw_auto = draw_auto;
476 rdev->r600_blit.primitives.set_default_state = set_default_state;
477
478 rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
479 rdev->r600_blit.ring_size_common += 40; /* shaders + def state */
480 rdev->r600_blit.ring_size_common += 5; /* done copy */
481 rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
482
483 rdev->r600_blit.ring_size_per_loop = 76;
484 /* set_render_target emits 2 extra dwords on rv6xx */
485 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
486 rdev->r600_blit.ring_size_per_loop += 2;
487
488 rdev->r600_blit.max_dim = 8192;
489
490 rdev->r600_blit.state_offset = 0;
491
492 if (rdev->family >= CHIP_RV770)
493 rdev->r600_blit.state_len = r7xx_default_size;
494 else
495 rdev->r600_blit.state_len = r6xx_default_size;
496
497 dwords = rdev->r600_blit.state_len;
498 while (dwords & 0xf) {
499 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
500 dwords++;
501 }
502
503 obj_size = dwords * 4;
504 obj_size = roundup2(obj_size, 256);
505
506 rdev->r600_blit.vs_offset = obj_size;
507 obj_size += r6xx_vs_size * 4;
508 obj_size = roundup2(obj_size, 256);
509
510 rdev->r600_blit.ps_offset = obj_size;
511 obj_size += r6xx_ps_size * 4;
512 obj_size = roundup2(obj_size, 256);
513
514 /* pin copy shader into vram if not already initialized */
515 if (rdev->r600_blit.shader_obj == NULL) {
516 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
517 RADEON_GEM_DOMAIN_VRAM,
518 NULL, &rdev->r600_blit.shader_obj);
519 if (r) {
520 DRM_ERROR("r600 failed to allocate shader\n");
521 return r;
522 }
523
524 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
525 if (unlikely(r != 0))
526 return r;
527 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
528 &rdev->r600_blit.shader_gpu_addr);
529 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
530 if (r) {
531 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
532 return r;
533 }
534 }
535
536 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
537 obj_size,
538 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
539
540 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
541 if (unlikely(r != 0))
542 return r;
543 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
544 if (r) {
545 DRM_ERROR("failed to map blit object %d\n", r);
546 return r;
547 }
548 if (rdev->family >= CHIP_RV770)
549 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
550 r7xx_default_state, rdev->r600_blit.state_len * 4);
551 else
552 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
553 r6xx_default_state, rdev->r600_blit.state_len * 4);
554 if (num_packet2s)
555 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
556 packet2s, num_packet2s * 4);
557 for (i = 0; i < r6xx_vs_size; i++)
558 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
559 for (i = 0; i < r6xx_ps_size; i++)
560 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
561 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
562 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
563
564 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
565 return 0;
566}
567
568void r600_blit_fini(struct radeon_device *rdev)
569{
570 int r;
571
572 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
573 if (rdev->r600_blit.shader_obj == NULL)
574 return;
575 /* If we can't reserve the bo, unref should be enough to destroy
576 * it when it becomes idle.
577 */
578 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
579 if (!r) {
580 radeon_bo_unpin(rdev->r600_blit.shader_obj);
581 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
582 }
583 radeon_bo_unref(&rdev->r600_blit.shader_obj);
584}
585
586static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
587 int *width, int *height, int max_dim)
588{
589 unsigned max_pages;
590 unsigned pages = num_gpu_pages;
591 int w, h;
592
593 if (num_gpu_pages == 0) {
594 /* not supposed to be called with no pages, but just in case */
595 h = 0;
596 w = 0;
597 pages = 0;
598 DRM_ERROR("%s: called with no pages", __func__);
599 } else {
600 int rect_order = 2;
601 h = RECT_UNIT_H;
602 while (num_gpu_pages / rect_order) {
603 h *= 2;
604 rect_order *= 4;
605 if (h >= max_dim) {
606 h = max_dim;
607 break;
608 }
609 }
610 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
611 if (pages > max_pages)
612 pages = max_pages;
613 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
614 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
615 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
616 KASSERT(pages != 0, ("r600_blit_create_rect: pages == 0"));
617 }
618
619
620 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
621
622 /* return width and height only of the caller wants it */
623 if (height)
624 *height = h;
625 if (width)
626 *width = w;
627
628 return pages;
629}
630
631
632int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
633 struct radeon_fence **fence, struct radeon_sa_bo **vb,
634 struct radeon_semaphore **sem)
635{
636 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
637 int r;
638 int ring_size;
639 int num_loops = 0;
640 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
641
642 /* num loops */
643 while (num_gpu_pages) {
644 num_gpu_pages -=
645 r600_blit_create_rect(num_gpu_pages, NULL, NULL,
646 rdev->r600_blit.max_dim);
647 num_loops++;
648 }
649
650 /* 48 bytes for vertex per loop */
651 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
652 (num_loops*48)+256, 256, true);
653 if (r) {
654 return r;
655 }
656
657 r = radeon_semaphore_create(rdev, sem);
658 if (r) {
659 radeon_sa_bo_free(rdev, vb, NULL);
660 return r;
661 }
662
663 /* calculate number of loops correctly */
664 ring_size = num_loops * dwords_per_loop;
665 ring_size += rdev->r600_blit.ring_size_common;
666 r = radeon_ring_lock(rdev, ring, ring_size);
667 if (r) {
668 radeon_sa_bo_free(rdev, vb, NULL);
669 radeon_semaphore_free(rdev, sem, NULL);
670 return r;
671 }
672
673 if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) {
674 radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
675 RADEON_RING_TYPE_GFX_INDEX);
676 radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX);
677 } else {
678 radeon_semaphore_free(rdev, sem, NULL);
679 }
680
681 rdev->r600_blit.primitives.set_default_state(rdev);
682 rdev->r600_blit.primitives.set_shaders(rdev);
683 return 0;
684}
685
686void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
687 struct radeon_sa_bo *vb, struct radeon_semaphore *sem)
688{
689 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
690 int r;
691
692 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
693 if (r) {
694 radeon_ring_unlock_undo(rdev, ring);
695 return;
696 }
697
698 radeon_ring_unlock_commit(rdev, ring);
699 radeon_sa_bo_free(rdev, &vb, *fence);
700 radeon_semaphore_free(rdev, &sem, *fence);
701}
702
703void r600_kms_blit_copy(struct radeon_device *rdev,
704 u64 src_gpu_addr, u64 dst_gpu_addr,
705 unsigned num_gpu_pages,
706 struct radeon_sa_bo *vb)
707{
708 u64 vb_gpu_addr;
709 u32 *vb_cpu_addr;
710
711 DRM_DEBUG("emitting copy %16jx %16jx %d\n",
712 (uintmax_t)src_gpu_addr, (uintmax_t)dst_gpu_addr, num_gpu_pages);
713 vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
714 vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
715
716 while (num_gpu_pages) {
717 int w, h;
718 unsigned size_in_bytes;
719 unsigned pages_per_loop =
720 r600_blit_create_rect(num_gpu_pages, &w, &h,
721 rdev->r600_blit.max_dim);
722
723 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
724 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
725
726 vb_cpu_addr[0] = 0;
727 vb_cpu_addr[1] = 0;
728 vb_cpu_addr[2] = 0;
729 vb_cpu_addr[3] = 0;
730
731 vb_cpu_addr[4] = 0;
732 vb_cpu_addr[5] = int2float(h);
733 vb_cpu_addr[6] = 0;
734 vb_cpu_addr[7] = int2float(h);
735
736 vb_cpu_addr[8] = int2float(w);
737 vb_cpu_addr[9] = int2float(h);
738 vb_cpu_addr[10] = int2float(w);
739 vb_cpu_addr[11] = int2float(h);
740
741 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
742 w, h, w, src_gpu_addr, size_in_bytes);
743 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
744 w, h, dst_gpu_addr);
745 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
746 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
747 rdev->r600_blit.primitives.draw_auto(rdev);
748 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
749 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
750 size_in_bytes, dst_gpu_addr);
751
752 vb_cpu_addr += 12;
753 vb_gpu_addr += 4*12;
754 src_gpu_addr += size_in_bytes;
755 dst_gpu_addr += size_in_bytes;
756 num_gpu_pages -= pages_per_loop;
757 }
758}
| 253 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
254}
255
256/* emits 10 */
257static void
258draw_auto(struct radeon_device *rdev)
259{
260 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
261 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
262 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
263 radeon_ring_write(ring, DI_PT_RECTLIST);
264
265 radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
266 radeon_ring_write(ring,
267#ifdef __BIG_ENDIAN
268 (2 << 2) |
269#endif
270 DI_INDEX_SIZE_16_BIT);
271
272 radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
273 radeon_ring_write(ring, 1);
274
275 radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
276 radeon_ring_write(ring, 3);
277 radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
278
279}
280
281/* emits 14 */
282static void
283set_default_state(struct radeon_device *rdev)
284{
285 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
286 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
287 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
288 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
289 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
290 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
291 u64 gpu_addr;
292 int dwords;
293
294 switch (rdev->family) {
295 case CHIP_R600:
296 num_ps_gprs = 192;
297 num_vs_gprs = 56;
298 num_temp_gprs = 4;
299 num_gs_gprs = 0;
300 num_es_gprs = 0;
301 num_ps_threads = 136;
302 num_vs_threads = 48;
303 num_gs_threads = 4;
304 num_es_threads = 4;
305 num_ps_stack_entries = 128;
306 num_vs_stack_entries = 128;
307 num_gs_stack_entries = 0;
308 num_es_stack_entries = 0;
309 break;
310 case CHIP_RV630:
311 case CHIP_RV635:
312 num_ps_gprs = 84;
313 num_vs_gprs = 36;
314 num_temp_gprs = 4;
315 num_gs_gprs = 0;
316 num_es_gprs = 0;
317 num_ps_threads = 144;
318 num_vs_threads = 40;
319 num_gs_threads = 4;
320 num_es_threads = 4;
321 num_ps_stack_entries = 40;
322 num_vs_stack_entries = 40;
323 num_gs_stack_entries = 32;
324 num_es_stack_entries = 16;
325 break;
326 case CHIP_RV610:
327 case CHIP_RV620:
328 case CHIP_RS780:
329 case CHIP_RS880:
330 default:
331 num_ps_gprs = 84;
332 num_vs_gprs = 36;
333 num_temp_gprs = 4;
334 num_gs_gprs = 0;
335 num_es_gprs = 0;
336 num_ps_threads = 136;
337 num_vs_threads = 48;
338 num_gs_threads = 4;
339 num_es_threads = 4;
340 num_ps_stack_entries = 40;
341 num_vs_stack_entries = 40;
342 num_gs_stack_entries = 32;
343 num_es_stack_entries = 16;
344 break;
345 case CHIP_RV670:
346 num_ps_gprs = 144;
347 num_vs_gprs = 40;
348 num_temp_gprs = 4;
349 num_gs_gprs = 0;
350 num_es_gprs = 0;
351 num_ps_threads = 136;
352 num_vs_threads = 48;
353 num_gs_threads = 4;
354 num_es_threads = 4;
355 num_ps_stack_entries = 40;
356 num_vs_stack_entries = 40;
357 num_gs_stack_entries = 32;
358 num_es_stack_entries = 16;
359 break;
360 case CHIP_RV770:
361 num_ps_gprs = 192;
362 num_vs_gprs = 56;
363 num_temp_gprs = 4;
364 num_gs_gprs = 0;
365 num_es_gprs = 0;
366 num_ps_threads = 188;
367 num_vs_threads = 60;
368 num_gs_threads = 0;
369 num_es_threads = 0;
370 num_ps_stack_entries = 256;
371 num_vs_stack_entries = 256;
372 num_gs_stack_entries = 0;
373 num_es_stack_entries = 0;
374 break;
375 case CHIP_RV730:
376 case CHIP_RV740:
377 num_ps_gprs = 84;
378 num_vs_gprs = 36;
379 num_temp_gprs = 4;
380 num_gs_gprs = 0;
381 num_es_gprs = 0;
382 num_ps_threads = 188;
383 num_vs_threads = 60;
384 num_gs_threads = 0;
385 num_es_threads = 0;
386 num_ps_stack_entries = 128;
387 num_vs_stack_entries = 128;
388 num_gs_stack_entries = 0;
389 num_es_stack_entries = 0;
390 break;
391 case CHIP_RV710:
392 num_ps_gprs = 192;
393 num_vs_gprs = 56;
394 num_temp_gprs = 4;
395 num_gs_gprs = 0;
396 num_es_gprs = 0;
397 num_ps_threads = 144;
398 num_vs_threads = 48;
399 num_gs_threads = 0;
400 num_es_threads = 0;
401 num_ps_stack_entries = 128;
402 num_vs_stack_entries = 128;
403 num_gs_stack_entries = 0;
404 num_es_stack_entries = 0;
405 break;
406 }
407
408 if ((rdev->family == CHIP_RV610) ||
409 (rdev->family == CHIP_RV620) ||
410 (rdev->family == CHIP_RS780) ||
411 (rdev->family == CHIP_RS880) ||
412 (rdev->family == CHIP_RV710))
413 sq_config = 0;
414 else
415 sq_config = VC_ENABLE;
416
417 sq_config |= (DX9_CONSTS |
418 ALU_INST_PREFER_VECTOR |
419 PS_PRIO(0) |
420 VS_PRIO(1) |
421 GS_PRIO(2) |
422 ES_PRIO(3));
423
424 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
425 NUM_VS_GPRS(num_vs_gprs) |
426 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
427 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
428 NUM_ES_GPRS(num_es_gprs));
429 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
430 NUM_VS_THREADS(num_vs_threads) |
431 NUM_GS_THREADS(num_gs_threads) |
432 NUM_ES_THREADS(num_es_threads));
433 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
434 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
435 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
436 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
437
438 /* emit an IB pointing at default state */
439 dwords = roundup2(rdev->r600_blit.state_len, 0x10);
440 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
441 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
442 radeon_ring_write(ring,
443#ifdef __BIG_ENDIAN
444 (2 << 0) |
445#endif
446 (gpu_addr & 0xFFFFFFFC));
447 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
448 radeon_ring_write(ring, dwords);
449
450 /* SQ config */
451 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
452 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
453 radeon_ring_write(ring, sq_config);
454 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
455 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
456 radeon_ring_write(ring, sq_thread_resource_mgmt);
457 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
458 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
459}
460
461int r600_blit_init(struct radeon_device *rdev)
462{
463 u32 obj_size;
464 int i, r, dwords;
465 void *ptr;
466 u32 packet2s[16];
467 int num_packet2s = 0;
468
469 rdev->r600_blit.primitives.set_render_target = set_render_target;
470 rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
471 rdev->r600_blit.primitives.set_shaders = set_shaders;
472 rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
473 rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
474 rdev->r600_blit.primitives.set_scissors = set_scissors;
475 rdev->r600_blit.primitives.draw_auto = draw_auto;
476 rdev->r600_blit.primitives.set_default_state = set_default_state;
477
478 rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
479 rdev->r600_blit.ring_size_common += 40; /* shaders + def state */
480 rdev->r600_blit.ring_size_common += 5; /* done copy */
481 rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
482
483 rdev->r600_blit.ring_size_per_loop = 76;
484 /* set_render_target emits 2 extra dwords on rv6xx */
485 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
486 rdev->r600_blit.ring_size_per_loop += 2;
487
488 rdev->r600_blit.max_dim = 8192;
489
490 rdev->r600_blit.state_offset = 0;
491
492 if (rdev->family >= CHIP_RV770)
493 rdev->r600_blit.state_len = r7xx_default_size;
494 else
495 rdev->r600_blit.state_len = r6xx_default_size;
496
497 dwords = rdev->r600_blit.state_len;
498 while (dwords & 0xf) {
499 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
500 dwords++;
501 }
502
503 obj_size = dwords * 4;
504 obj_size = roundup2(obj_size, 256);
505
506 rdev->r600_blit.vs_offset = obj_size;
507 obj_size += r6xx_vs_size * 4;
508 obj_size = roundup2(obj_size, 256);
509
510 rdev->r600_blit.ps_offset = obj_size;
511 obj_size += r6xx_ps_size * 4;
512 obj_size = roundup2(obj_size, 256);
513
514 /* pin copy shader into vram if not already initialized */
515 if (rdev->r600_blit.shader_obj == NULL) {
516 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
517 RADEON_GEM_DOMAIN_VRAM,
518 NULL, &rdev->r600_blit.shader_obj);
519 if (r) {
520 DRM_ERROR("r600 failed to allocate shader\n");
521 return r;
522 }
523
524 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
525 if (unlikely(r != 0))
526 return r;
527 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
528 &rdev->r600_blit.shader_gpu_addr);
529 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
530 if (r) {
531 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
532 return r;
533 }
534 }
535
536 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
537 obj_size,
538 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
539
540 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
541 if (unlikely(r != 0))
542 return r;
543 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
544 if (r) {
545 DRM_ERROR("failed to map blit object %d\n", r);
546 return r;
547 }
548 if (rdev->family >= CHIP_RV770)
549 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
550 r7xx_default_state, rdev->r600_blit.state_len * 4);
551 else
552 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
553 r6xx_default_state, rdev->r600_blit.state_len * 4);
554 if (num_packet2s)
555 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
556 packet2s, num_packet2s * 4);
557 for (i = 0; i < r6xx_vs_size; i++)
558 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
559 for (i = 0; i < r6xx_ps_size; i++)
560 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
561 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
562 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
563
564 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
565 return 0;
566}
567
568void r600_blit_fini(struct radeon_device *rdev)
569{
570 int r;
571
572 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
573 if (rdev->r600_blit.shader_obj == NULL)
574 return;
575 /* If we can't reserve the bo, unref should be enough to destroy
576 * it when it becomes idle.
577 */
578 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
579 if (!r) {
580 radeon_bo_unpin(rdev->r600_blit.shader_obj);
581 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
582 }
583 radeon_bo_unref(&rdev->r600_blit.shader_obj);
584}
585
586static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
587 int *width, int *height, int max_dim)
588{
589 unsigned max_pages;
590 unsigned pages = num_gpu_pages;
591 int w, h;
592
593 if (num_gpu_pages == 0) {
594 /* not supposed to be called with no pages, but just in case */
595 h = 0;
596 w = 0;
597 pages = 0;
598 DRM_ERROR("%s: called with no pages", __func__);
599 } else {
600 int rect_order = 2;
601 h = RECT_UNIT_H;
602 while (num_gpu_pages / rect_order) {
603 h *= 2;
604 rect_order *= 4;
605 if (h >= max_dim) {
606 h = max_dim;
607 break;
608 }
609 }
610 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
611 if (pages > max_pages)
612 pages = max_pages;
613 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
614 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
615 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
616 KASSERT(pages != 0, ("r600_blit_create_rect: pages == 0"));
617 }
618
619
620 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
621
622 /* return width and height only of the caller wants it */
623 if (height)
624 *height = h;
625 if (width)
626 *width = w;
627
628 return pages;
629}
630
631
632int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
633 struct radeon_fence **fence, struct radeon_sa_bo **vb,
634 struct radeon_semaphore **sem)
635{
636 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
637 int r;
638 int ring_size;
639 int num_loops = 0;
640 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
641
642 /* num loops */
643 while (num_gpu_pages) {
644 num_gpu_pages -=
645 r600_blit_create_rect(num_gpu_pages, NULL, NULL,
646 rdev->r600_blit.max_dim);
647 num_loops++;
648 }
649
650 /* 48 bytes for vertex per loop */
651 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
652 (num_loops*48)+256, 256, true);
653 if (r) {
654 return r;
655 }
656
657 r = radeon_semaphore_create(rdev, sem);
658 if (r) {
659 radeon_sa_bo_free(rdev, vb, NULL);
660 return r;
661 }
662
663 /* calculate number of loops correctly */
664 ring_size = num_loops * dwords_per_loop;
665 ring_size += rdev->r600_blit.ring_size_common;
666 r = radeon_ring_lock(rdev, ring, ring_size);
667 if (r) {
668 radeon_sa_bo_free(rdev, vb, NULL);
669 radeon_semaphore_free(rdev, sem, NULL);
670 return r;
671 }
672
673 if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) {
674 radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
675 RADEON_RING_TYPE_GFX_INDEX);
676 radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX);
677 } else {
678 radeon_semaphore_free(rdev, sem, NULL);
679 }
680
681 rdev->r600_blit.primitives.set_default_state(rdev);
682 rdev->r600_blit.primitives.set_shaders(rdev);
683 return 0;
684}
685
686void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
687 struct radeon_sa_bo *vb, struct radeon_semaphore *sem)
688{
689 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
690 int r;
691
692 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
693 if (r) {
694 radeon_ring_unlock_undo(rdev, ring);
695 return;
696 }
697
698 radeon_ring_unlock_commit(rdev, ring);
699 radeon_sa_bo_free(rdev, &vb, *fence);
700 radeon_semaphore_free(rdev, &sem, *fence);
701}
702
703void r600_kms_blit_copy(struct radeon_device *rdev,
704 u64 src_gpu_addr, u64 dst_gpu_addr,
705 unsigned num_gpu_pages,
706 struct radeon_sa_bo *vb)
707{
708 u64 vb_gpu_addr;
709 u32 *vb_cpu_addr;
710
711 DRM_DEBUG("emitting copy %16jx %16jx %d\n",
712 (uintmax_t)src_gpu_addr, (uintmax_t)dst_gpu_addr, num_gpu_pages);
713 vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
714 vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
715
716 while (num_gpu_pages) {
717 int w, h;
718 unsigned size_in_bytes;
719 unsigned pages_per_loop =
720 r600_blit_create_rect(num_gpu_pages, &w, &h,
721 rdev->r600_blit.max_dim);
722
723 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
724 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
725
726 vb_cpu_addr[0] = 0;
727 vb_cpu_addr[1] = 0;
728 vb_cpu_addr[2] = 0;
729 vb_cpu_addr[3] = 0;
730
731 vb_cpu_addr[4] = 0;
732 vb_cpu_addr[5] = int2float(h);
733 vb_cpu_addr[6] = 0;
734 vb_cpu_addr[7] = int2float(h);
735
736 vb_cpu_addr[8] = int2float(w);
737 vb_cpu_addr[9] = int2float(h);
738 vb_cpu_addr[10] = int2float(w);
739 vb_cpu_addr[11] = int2float(h);
740
741 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
742 w, h, w, src_gpu_addr, size_in_bytes);
743 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
744 w, h, dst_gpu_addr);
745 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
746 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
747 rdev->r600_blit.primitives.draw_auto(rdev);
748 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
749 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
750 size_in_bytes, dst_gpu_addr);
751
752 vb_cpu_addr += 12;
753 vb_gpu_addr += 4*12;
754 src_gpu_addr += size_in_bytes;
755 dst_gpu_addr += size_in_bytes;
756 num_gpu_pages -= pages_per_loop;
757 }
758}
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