Deleted Added
sdiff udiff text old ( 254885 ) new ( 280183 )
full compact
evergreen.c (254885) evergreen.c (280183)
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 9 unchanged lines hidden (view full) ---

18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <sys/cdefs.h>
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 9 unchanged lines hidden (view full) ---

18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <sys/cdefs.h>
26__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/evergreen.c 254885 2013-08-25 19:37:15Z dumbbell $");
26__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/evergreen.c 280183 2015-03-17 18:50:33Z dumbbell $");
27
28#include <dev/drm2/drmP.h>
29#include "radeon.h"
30#include "radeon_asic.h"
31#include <dev/drm2/radeon/radeon_drm.h>
32#include "evergreend.h"
33#include "atom.h"
34#include "avivod.h"

--- 9 unchanged lines hidden (view full) ---

44 EVERGREEN_CRTC1_REGISTER_OFFSET,
45 EVERGREEN_CRTC2_REGISTER_OFFSET,
46 EVERGREEN_CRTC3_REGISTER_OFFSET,
47 EVERGREEN_CRTC4_REGISTER_OFFSET,
48 EVERGREEN_CRTC5_REGISTER_OFFSET
49};
50
51static void evergreen_gpu_init(struct radeon_device *rdev);
27
28#include <dev/drm2/drmP.h>
29#include "radeon.h"
30#include "radeon_asic.h"
31#include <dev/drm2/radeon/radeon_drm.h>
32#include "evergreend.h"
33#include "atom.h"
34#include "avivod.h"

--- 9 unchanged lines hidden (view full) ---

44 EVERGREEN_CRTC1_REGISTER_OFFSET,
45 EVERGREEN_CRTC2_REGISTER_OFFSET,
46 EVERGREEN_CRTC3_REGISTER_OFFSET,
47 EVERGREEN_CRTC4_REGISTER_OFFSET,
48 EVERGREEN_CRTC5_REGISTER_OFFSET
49};
50
51static void evergreen_gpu_init(struct radeon_device *rdev);
52#ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
53void evergreen_fini(struct radeon_device *rdev);
54#endif
52void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
55void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
56#ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
57extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
58 int ring, u32 cp_int_cntl);
59#endif
53
54void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
55 unsigned *bankh, unsigned *mtaspect,
56 unsigned *tile_split)
57{
58 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
59 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
60 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;

--- 41 unchanged lines hidden (view full) ---

102 */
103 if ((v == 0) || (v == 6) || (v == 7)) {
104 ctl &= ~PCIEM_CTL_MAX_READ_REQUEST;
105 ctl |= (2 << 12);
106 pci_write_config(rdev->dev, cap, ctl, 2);
107 }
108}
109
60
61void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
62 unsigned *bankh, unsigned *mtaspect,
63 unsigned *tile_split)
64{
65 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
66 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
67 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;

--- 41 unchanged lines hidden (view full) ---

109 */
110 if ((v == 0) || (v == 6) || (v == 7)) {
111 ctl &= ~PCIEM_CTL_MAX_READ_REQUEST;
112 ctl |= (2 << 12);
113 pci_write_config(rdev->dev, cap, ctl, 2);
114 }
115}
116
117static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
118{
119 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
120 return true;
121 else
122 return false;
123}
124
125static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
126{
127 u32 pos1, pos2;
128
129 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
130 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
131
132 if (pos1 != pos2)
133 return true;
134 else
135 return false;
136}
137
110/**
111 * dce4_wait_for_vblank - vblank wait asic callback.
112 *
113 * @rdev: radeon_device pointer
114 * @crtc: crtc to wait for vblank on
115 *
116 * Wait for vblank on the requested crtc (evergreen+).
117 */
118void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
119{
138/**
139 * dce4_wait_for_vblank - vblank wait asic callback.
140 *
141 * @rdev: radeon_device pointer
142 * @crtc: crtc to wait for vblank on
143 *
144 * Wait for vblank on the requested crtc (evergreen+).
145 */
146void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
147{
120 int i;
148 unsigned i = 0;
121
122 if (crtc >= rdev->num_crtc)
123 return;
124
149
150 if (crtc >= rdev->num_crtc)
151 return;
152
125 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
126 for (i = 0; i < rdev->usec_timeout; i++) {
127 if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
153 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
154 return;
155
156 /* depending on when we hit vblank, we may be close to active; if so,
157 * wait for another frame.
158 */
159 while (dce4_is_in_vblank(rdev, crtc)) {
160 if (i++ % 100 == 0) {
161 if (!dce4_is_counter_moving(rdev, crtc))
128 break;
162 break;
129 DRM_UDELAY(1);
130 }
163 }
131 for (i = 0; i < rdev->usec_timeout; i++) {
132 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
164 }
165
166 while (!dce4_is_in_vblank(rdev, crtc)) {
167 if (i++ % 100 == 0) {
168 if (!dce4_is_counter_moving(rdev, crtc))
133 break;
169 break;
134 DRM_UDELAY(1);
135 }
136 }
137}
138
139/**
140 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
141 *
142 * @rdev: radeon_device pointer

--- 56 unchanged lines hidden (view full) ---

199 upper_32_bits(crtc_base));
200 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
201 (u32)crtc_base);
202
203 /* Wait for update_pending to go high. */
204 for (i = 0; i < rdev->usec_timeout; i++) {
205 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
206 break;
170 }
171 }
172}
173
174/**
175 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
176 *
177 * @rdev: radeon_device pointer

--- 56 unchanged lines hidden (view full) ---

234 upper_32_bits(crtc_base));
235 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
236 (u32)crtc_base);
237
238 /* Wait for update_pending to go high. */
239 for (i = 0; i < rdev->usec_timeout; i++) {
240 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
241 break;
207 DRM_UDELAY(1);
242 udelay(1);
208 }
209 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
210
211 /* Unlock the lock, so double-buffering can take place inside vblank */
212 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
213 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
214
215 /* Return current update_pending status: */

--- 184 unchanged lines hidden (view full) ---

400 /* 0xff01 is a flag rather then an actual voltage */
401 if (voltage->voltage == 0xff01)
402 return;
403 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
404 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
405 rdev->pm.current_vddc = voltage->voltage;
406 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
407 }
243 }
244 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
245
246 /* Unlock the lock, so double-buffering can take place inside vblank */
247 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
248 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
249
250 /* Return current update_pending status: */

--- 184 unchanged lines hidden (view full) ---

435 /* 0xff01 is a flag rather then an actual voltage */
436 if (voltage->voltage == 0xff01)
437 return;
438 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
439 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
440 rdev->pm.current_vddc = voltage->voltage;
441 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
442 }
443
444 /* starting with BTC, there is one state that is used for both
445 * MH and SH. Difference is that we always use the high clock index for
446 * mclk and vddci.
447 */
448 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
449 (rdev->family >= CHIP_BARTS) &&
450 rdev->pm.active_crtc_count &&
451 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
452 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
453 voltage = &rdev->pm.power_state[req_ps_idx].
454 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
455
408 /* 0xff01 is a flag rather then an actual voltage */
409 if (voltage->vddci == 0xff01)
410 return;
411 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
412 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
413 rdev->pm.current_vddci = voltage->vddci;
414 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
415 }

--- 176 unchanged lines hidden (view full) ---

592 struct drm_device *dev = rdev->ddev;
593 struct drm_connector *connector;
594 unsigned enabled = 0;
595 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
596 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
597
598 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
599 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
456 /* 0xff01 is a flag rather then an actual voltage */
457 if (voltage->vddci == 0xff01)
458 return;
459 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
460 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
461 rdev->pm.current_vddci = voltage->vddci;
462 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
463 }

--- 176 unchanged lines hidden (view full) ---

640 struct drm_device *dev = rdev->ddev;
641 struct drm_connector *connector;
642 unsigned enabled = 0;
643 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
644 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
645
646 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
647 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
648
649 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
650 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
651 /* don't try to enable hpd on eDP or LVDS avoid breaking the
652 * aux dp channel on imac and help (but not completely fix)
653 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
654 * also avoid interrupt storms during dpms.
655 */
656 continue;
657 }
600 switch (radeon_connector->hpd.hpd) {
601 case RADEON_HPD_1:
602 WREG32(DC_HPD1_CONTROL, tmp);
603 break;
604 case RADEON_HPD_2:
605 WREG32(DC_HPD2_CONTROL, tmp);
606 break;
607 case RADEON_HPD_3:

--- 533 unchanged lines hidden (view full) ---

1141 unsigned i;
1142 u32 tmp;
1143
1144 for (i = 0; i < rdev->usec_timeout; i++) {
1145 /* read MC_STATUS */
1146 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1147 if (!tmp)
1148 return 0;
658 switch (radeon_connector->hpd.hpd) {
659 case RADEON_HPD_1:
660 WREG32(DC_HPD1_CONTROL, tmp);
661 break;
662 case RADEON_HPD_2:
663 WREG32(DC_HPD2_CONTROL, tmp);
664 break;
665 case RADEON_HPD_3:

--- 533 unchanged lines hidden (view full) ---

1199 unsigned i;
1200 u32 tmp;
1201
1202 for (i = 0; i < rdev->usec_timeout; i++) {
1203 /* read MC_STATUS */
1204 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1205 if (!tmp)
1206 return 0;
1149 DRM_UDELAY(1);
1207 udelay(1);
1150 }
1151 return -1;
1152}
1153
1154/*
1155 * GART
1156 */
1157void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)

--- 10 unchanged lines hidden (view full) ---

1168 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1169 if (tmp == 2) {
1170 DRM_ERROR("[drm] r600 flush TLB failed\n");
1171 return;
1172 }
1173 if (tmp) {
1174 return;
1175 }
1208 }
1209 return -1;
1210}
1211
1212/*
1213 * GART
1214 */
1215void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)

--- 10 unchanged lines hidden (view full) ---

1226 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1227 if (tmp == 2) {
1228 DRM_ERROR("[drm] r600 flush TLB failed\n");
1229 return;
1230 }
1231 if (tmp) {
1232 return;
1233 }
1176 DRM_UDELAY(1);
1234 udelay(1);
1177 }
1178}
1179
1180static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1181{
1182 u32 tmp;
1183 int r;
1184

--- 124 unchanged lines hidden (view full) ---

1309 for (i = 0; i < rdev->num_crtc; i++) {
1310 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1311 if (crtc_enabled) {
1312 save->crtc_enabled[i] = true;
1313 if (ASIC_IS_DCE6(rdev)) {
1314 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1315 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1316 radeon_wait_for_vblank(rdev, i);
1235 }
1236}
1237
1238static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1239{
1240 u32 tmp;
1241 int r;
1242

--- 124 unchanged lines hidden (view full) ---

1367 for (i = 0; i < rdev->num_crtc; i++) {
1368 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1369 if (crtc_enabled) {
1370 save->crtc_enabled[i] = true;
1371 if (ASIC_IS_DCE6(rdev)) {
1372 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1373 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1374 radeon_wait_for_vblank(rdev, i);
1317 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1318 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1375 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1376 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1319 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1377 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1320 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1321 }
1322 } else {
1323 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1324 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1325 radeon_wait_for_vblank(rdev, i);
1378 }
1379 } else {
1380 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1381 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1382 radeon_wait_for_vblank(rdev, i);
1326 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1327 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1383 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1384 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1328 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1329 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1330 }
1331 }
1332 /* wait for the next frame */
1333 frame_count = radeon_get_vblank_counter(rdev, i);
1334 for (j = 0; j < rdev->usec_timeout; j++) {
1335 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1336 break;
1385 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1386 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1387 }
1388 }
1389 /* wait for the next frame */
1390 frame_count = radeon_get_vblank_counter(rdev, i);
1391 for (j = 0; j < rdev->usec_timeout; j++) {
1392 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1393 break;
1337 DRM_UDELAY(1);
1394 udelay(1);
1338 }
1395 }
1396
1397 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
1398 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1399 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1400 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
1401 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1402 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1403 save->crtc_enabled[i] = false;
1404 /* ***** */
1339 } else {
1340 save->crtc_enabled[i] = false;
1341 }
1342 }
1343
1344 radeon_mc_wait_for_idle(rdev);
1345
1346 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1347 if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1348 /* Block CPU access */
1349 WREG32(BIF_FB_EN, 0);
1350 /* blackout the MC */
1351 blackout &= ~BLACKOUT_MODE_MASK;
1352 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1353 }
1354 /* wait for the MC to settle */
1405 } else {
1406 save->crtc_enabled[i] = false;
1407 }
1408 }
1409
1410 radeon_mc_wait_for_idle(rdev);
1411
1412 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1413 if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1414 /* Block CPU access */
1415 WREG32(BIF_FB_EN, 0);
1416 /* blackout the MC */
1417 blackout &= ~BLACKOUT_MODE_MASK;
1418 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1419 }
1420 /* wait for the MC to settle */
1355 DRM_UDELAY(100);
1421 udelay(100);
1422
1423 /* lock double buffered regs */
1424 for (i = 0; i < rdev->num_crtc; i++) {
1425 if (save->crtc_enabled[i]) {
1426 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1427 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
1428 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
1429 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
1430 }
1431 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
1432 if (!(tmp & 1)) {
1433 tmp |= 1;
1434 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
1435 }
1436 }
1437 }
1356}
1357
1358void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1359{
1360 u32 tmp, frame_count;
1361 int i, j;
1362
1363 /* update crtc base addresses */

--- 5 unchanged lines hidden (view full) ---

1369 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1370 (u32)rdev->mc.vram_start);
1371 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1372 (u32)rdev->mc.vram_start);
1373 }
1374 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1375 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1376
1438}
1439
1440void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1441{
1442 u32 tmp, frame_count;
1443 int i, j;
1444
1445 /* update crtc base addresses */

--- 5 unchanged lines hidden (view full) ---

1451 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1452 (u32)rdev->mc.vram_start);
1453 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1454 (u32)rdev->mc.vram_start);
1455 }
1456 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1457 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1458
1459 /* unlock regs and wait for update */
1460 for (i = 0; i < rdev->num_crtc; i++) {
1461 if (save->crtc_enabled[i]) {
1462 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
1463 if ((tmp & 0x3) != 0) {
1464 tmp &= ~0x3;
1465 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
1466 }
1467 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1468 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
1469 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
1470 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
1471 }
1472 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
1473 if (tmp & 1) {
1474 tmp &= ~1;
1475 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
1476 }
1477 for (j = 0; j < rdev->usec_timeout; j++) {
1478 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
1479 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
1480 break;
1481 udelay(1);
1482 }
1483 }
1484 }
1485
1377 /* unblackout the MC */
1378 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1379 tmp &= ~BLACKOUT_MODE_MASK;
1380 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1381 /* allow CPU access */
1382 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1383
1384 for (i = 0; i < rdev->num_crtc; i++) {

--- 11 unchanged lines hidden (view full) ---

1396 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1397 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1398 }
1399 /* wait for the next frame */
1400 frame_count = radeon_get_vblank_counter(rdev, i);
1401 for (j = 0; j < rdev->usec_timeout; j++) {
1402 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1403 break;
1486 /* unblackout the MC */
1487 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1488 tmp &= ~BLACKOUT_MODE_MASK;
1489 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1490 /* allow CPU access */
1491 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1492
1493 for (i = 0; i < rdev->num_crtc; i++) {

--- 11 unchanged lines hidden (view full) ---

1505 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1506 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1507 }
1508 /* wait for the next frame */
1509 frame_count = radeon_get_vblank_counter(rdev, i);
1510 for (j = 0; j < rdev->usec_timeout; j++) {
1511 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1512 break;
1404 DRM_UDELAY(1);
1513 udelay(1);
1405 }
1406 }
1407 }
1408 /* Unlock vga access */
1409 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1514 }
1515 }
1516 }
1517 /* Unlock vga access */
1518 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1410 DRM_MDELAY(1);
1519 mdelay(1);
1411 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1412}
1413
1414void evergreen_mc_program(struct radeon_device *rdev)
1415{
1416 struct evergreen_mc_save save;
1417 u32 tmp;
1418 int i, j;

--- 215 unchanged lines hidden (view full) ---

1634 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1635 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1636 SOFT_RESET_PA |
1637 SOFT_RESET_SH |
1638 SOFT_RESET_VGT |
1639 SOFT_RESET_SPI |
1640 SOFT_RESET_SX));
1641 RREG32(GRBM_SOFT_RESET);
1520 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1521}
1522
1523void evergreen_mc_program(struct radeon_device *rdev)
1524{
1525 struct evergreen_mc_save save;
1526 u32 tmp;
1527 int i, j;

--- 215 unchanged lines hidden (view full) ---

1743 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1744 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1745 SOFT_RESET_PA |
1746 SOFT_RESET_SH |
1747 SOFT_RESET_VGT |
1748 SOFT_RESET_SPI |
1749 SOFT_RESET_SX));
1750 RREG32(GRBM_SOFT_RESET);
1642 DRM_MDELAY(15);
1751 mdelay(15);
1643 WREG32(GRBM_SOFT_RESET, 0);
1644 RREG32(GRBM_SOFT_RESET);
1645
1646 /* Set ring buffer size */
1647 rb_bufsz = drm_order(ring->ring_size / 8);
1648 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1649#ifdef __BIG_ENDIAN
1650 tmp |= BUF_SWAP_32BIT;

--- 19 unchanged lines hidden (view full) ---

1670
1671 if (rdev->wb.enabled)
1672 WREG32(SCRATCH_UMSK, 0xff);
1673 else {
1674 tmp |= RB_NO_UPDATE;
1675 WREG32(SCRATCH_UMSK, 0);
1676 }
1677
1752 WREG32(GRBM_SOFT_RESET, 0);
1753 RREG32(GRBM_SOFT_RESET);
1754
1755 /* Set ring buffer size */
1756 rb_bufsz = drm_order(ring->ring_size / 8);
1757 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1758#ifdef __BIG_ENDIAN
1759 tmp |= BUF_SWAP_32BIT;

--- 19 unchanged lines hidden (view full) ---

1779
1780 if (rdev->wb.enabled)
1781 WREG32(SCRATCH_UMSK, 0xff);
1782 else {
1783 tmp |= RB_NO_UPDATE;
1784 WREG32(SCRATCH_UMSK, 0);
1785 }
1786
1678 DRM_MDELAY(1);
1787 mdelay(1);
1679 WREG32(CP_RB_CNTL, tmp);
1680
1681 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1682 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1683
1684 ring->rptr = RREG32(CP_RB_RPTR);
1685
1686 evergreen_cp_start(rdev);

--- 555 unchanged lines hidden (view full) ---

2242 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2243 WREG32(HDP_MISC_CNTL, tmp);
2244
2245 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2246 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2247
2248 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2249
1788 WREG32(CP_RB_CNTL, tmp);
1789
1790 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1791 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1792
1793 ring->rptr = RREG32(CP_RB_RPTR);
1794
1795 evergreen_cp_start(rdev);

--- 555 unchanged lines hidden (view full) ---

2351 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2352 WREG32(HDP_MISC_CNTL, tmp);
2353
2354 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2355 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2356
2357 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2358
2250 DRM_UDELAY(50);
2359 udelay(50);
2251
2252}
2253
2254int evergreen_mc_init(struct radeon_device *rdev)
2255{
2256 u32 tmp;
2257 int chansize, numchan;
2258

--- 109 unchanged lines hidden (view full) ---

2368 SOFT_RESET_TC |
2369 SOFT_RESET_TA |
2370 SOFT_RESET_VC |
2371 SOFT_RESET_VGT);
2372
2373 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2374 WREG32(GRBM_SOFT_RESET, grbm_reset);
2375 (void)RREG32(GRBM_SOFT_RESET);
2360
2361}
2362
2363int evergreen_mc_init(struct radeon_device *rdev)
2364{
2365 u32 tmp;
2366 int chansize, numchan;
2367

--- 109 unchanged lines hidden (view full) ---

2477 SOFT_RESET_TC |
2478 SOFT_RESET_TA |
2479 SOFT_RESET_VC |
2480 SOFT_RESET_VGT);
2481
2482 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2483 WREG32(GRBM_SOFT_RESET, grbm_reset);
2484 (void)RREG32(GRBM_SOFT_RESET);
2376 DRM_UDELAY(50);
2485 udelay(50);
2377 WREG32(GRBM_SOFT_RESET, 0);
2378 (void)RREG32(GRBM_SOFT_RESET);
2379
2380 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
2381 RREG32(GRBM_STATUS));
2382 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
2383 RREG32(GRBM_STATUS_SE0));
2384 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",

--- 23 unchanged lines hidden (view full) ---

2408 /* Disable DMA */
2409 tmp = RREG32(DMA_RB_CNTL);
2410 tmp &= ~DMA_RB_ENABLE;
2411 WREG32(DMA_RB_CNTL, tmp);
2412
2413 /* Reset dma */
2414 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2415 RREG32(SRBM_SOFT_RESET);
2486 WREG32(GRBM_SOFT_RESET, 0);
2487 (void)RREG32(GRBM_SOFT_RESET);
2488
2489 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
2490 RREG32(GRBM_STATUS));
2491 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
2492 RREG32(GRBM_STATUS_SE0));
2493 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",

--- 23 unchanged lines hidden (view full) ---

2517 /* Disable DMA */
2518 tmp = RREG32(DMA_RB_CNTL);
2519 tmp &= ~DMA_RB_ENABLE;
2520 WREG32(DMA_RB_CNTL, tmp);
2521
2522 /* Reset dma */
2523 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2524 RREG32(SRBM_SOFT_RESET);
2416 DRM_UDELAY(50);
2525 udelay(50);
2417 WREG32(SRBM_SOFT_RESET, 0);
2418
2419 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2420 RREG32(DMA_STATUS_REG));
2421}
2422
2423static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2424{

--- 17 unchanged lines hidden (view full) ---

2442
2443 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2444 evergreen_gpu_soft_reset_gfx(rdev);
2445
2446 if (reset_mask & RADEON_RESET_DMA)
2447 evergreen_gpu_soft_reset_dma(rdev);
2448
2449 /* Wait a little for things to settle down */
2526 WREG32(SRBM_SOFT_RESET, 0);
2527
2528 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2529 RREG32(DMA_STATUS_REG));
2530}
2531
2532static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2533{

--- 17 unchanged lines hidden (view full) ---

2551
2552 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2553 evergreen_gpu_soft_reset_gfx(rdev);
2554
2555 if (reset_mask & RADEON_RESET_DMA)
2556 evergreen_gpu_soft_reset_dma(rdev);
2557
2558 /* Wait a little for things to settle down */
2450 DRM_UDELAY(50);
2559 udelay(50);
2451
2452 evergreen_mc_resume(rdev, &save);
2453 return 0;
2454}
2455
2456int evergreen_asic_reset(struct radeon_device *rdev)
2457{
2458 return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

--- 407 unchanged lines hidden (view full) ---

2866 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2867 }
2868}
2869
2870static void evergreen_irq_disable(struct radeon_device *rdev)
2871{
2872 r600_disable_interrupts(rdev);
2873 /* Wait and acknowledge irq */
2560
2561 evergreen_mc_resume(rdev, &save);
2562 return 0;
2563}
2564
2565int evergreen_asic_reset(struct radeon_device *rdev)
2566{
2567 return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

--- 407 unchanged lines hidden (view full) ---

2975 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2976 }
2977}
2978
2979static void evergreen_irq_disable(struct radeon_device *rdev)
2980{
2981 r600_disable_interrupts(rdev);
2982 /* Wait and acknowledge irq */
2874 DRM_MDELAY(1);
2983 mdelay(1);
2875 evergreen_irq_ack(rdev);
2876 evergreen_disable_interrupt_state(rdev);
2877}
2878
2879void evergreen_irq_suspend(struct radeon_device *rdev)
2880{
2881 evergreen_irq_disable(rdev);
2882 r600_rlc_stop(rdev);

--- 877 unchanged lines hidden --- 		2984 evergreen_irq_ack(rdev);
2985 evergreen_disable_interrupt_state(rdev);
2986}
2987
2988void evergreen_irq_suspend(struct radeon_device *rdev)
2989{
2990 evergreen_irq_disable(rdev);
2991 r600_rlc_stop(rdev);

--- 877 unchanged lines hidden ---