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i915_gem.c (293837) i915_gem.c (296548)
1/*
2 * Copyright �� 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 38 unchanged lines hidden (view full) ---

47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * SUCH DAMAGE.
52 */
53
54#include <sys/cdefs.h>
1/*
2 * Copyright �� 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 38 unchanged lines hidden (view full) ---

47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * SUCH DAMAGE.
52 */
53
54#include <sys/cdefs.h>
55__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 293837 2016-01-13 19:52:25Z dumbbell $");
55__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 296548 2016-03-08 20:33:02Z dumbbell $");
56
57#include <dev/drm2/drmP.h>
56
57#include <dev/drm2/drmP.h>
58#include <dev/drm2/drm.h>
59#include <dev/drm2/i915/i915_drm.h>
60#include <dev/drm2/i915/i915_drv.h>
61#include <dev/drm2/i915/intel_drv.h>
58#include <dev/drm2/i915/i915_drm.h>
59#include <dev/drm2/i915/i915_drv.h>
60#include <dev/drm2/i915/intel_drv.h>
62#include <dev/drm2/i915/intel_ringbuffer.h>
63
64#include <sys/resourcevar.h>
65#include <sys/sched.h>
66#include <sys/sf_buf.h>
67
68#include <vm/vm.h>
69#include <vm/vm_pageout.h>
70
71#include <machine/md_var.h>
72
61
62#include <sys/resourcevar.h>
63#include <sys/sched.h>
64#include <sys/sf_buf.h>
65
66#include <vm/vm.h>
67#include <vm/vm_pageout.h>
68
69#include <machine/md_var.h>
70
73#define __user
74#define __force
75#define __iomem
76#define __must_check
77#define to_user_ptr(x) ((void *)(uintptr_t)(x))
78#define offset_in_page(x) ((x) & PAGE_MASK)
79#define page_to_phys(x) VM_PAGE_TO_PHYS(x)
80
81static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
82static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
83static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
84 unsigned alignment,
71static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
72static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
73static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
74 unsigned alignment,
85 bool map_and_fenceable);
75 bool map_and_fenceable,
76 bool nonblocking);
86static int i915_gem_phys_pwrite(struct drm_device *dev,
87 struct drm_i915_gem_object *obj,
88 struct drm_i915_gem_pwrite *args,
89 struct drm_file *file);
90
91static void i915_gem_write_fence(struct drm_device *dev, int reg,
92 struct drm_i915_gem_object *obj);
93static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
94 struct drm_i915_fence_reg *fence,
95 bool enable);
96
77static int i915_gem_phys_pwrite(struct drm_device *dev,
78 struct drm_i915_gem_object *obj,
79 struct drm_i915_gem_pwrite *args,
80 struct drm_file *file);
81
82static void i915_gem_write_fence(struct drm_device *dev, int reg,
83 struct drm_i915_gem_object *obj);
84static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
85 struct drm_i915_fence_reg *fence,
86 bool enable);
87
97static void i915_gem_lowmem(void *arg);
88static void i915_gem_inactive_shrink(void *);
89static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
90static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
98static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
99
100static int i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
101 off_t start, off_t end);
91static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
92
93static int i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
94 off_t start, off_t end);
102static void i915_gem_object_put_pages_range(struct drm_i915_gem_object *obj,
103 off_t start, off_t end);
104
105static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex,
106 bool *fresh);
107
108MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
109long i915_gem_wired_pages_cnt;
110
95
96static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex,
97 bool *fresh);
98
99MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
100long i915_gem_wired_pages_cnt;
101
111static bool cpu_cache_is_coherent(struct drm_device *dev,
112 enum i915_cache_level level)
113{
114 return HAS_LLC(dev) || level != I915_CACHE_NONE;
115}
116
117static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
118{
119 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
120 return true;
121
122 return obj->pin_display;
123}
124
125static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
126{
127 if (obj->tiling_mode)
128 i915_gem_release_mmap(obj);
129
130 /* As we do not have an associated fence register, we will force
131 * a tiling change if we ever need to acquire one.
132 */

--- 15 unchanged lines hidden (view full) ---

148 dev_priv->mm.object_count--;
149 dev_priv->mm.object_memory -= size;
150}
151
152static int
153i915_gem_wait_for_error(struct drm_device *dev)
154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
102static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
103{
104 if (obj->tiling_mode)
105 i915_gem_release_mmap(obj);
106
107 /* As we do not have an associated fence register, we will force
108 * a tiling change if we ever need to acquire one.
109 */

--- 15 unchanged lines hidden (view full) ---

125 dev_priv->mm.object_count--;
126 dev_priv->mm.object_memory -= size;
127}
128
129static int
130i915_gem_wait_for_error(struct drm_device *dev)
131{
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct completion *x = &dev_priv->error_completion;
156 int ret;
157
134 int ret;
135
158 if (!atomic_load_acq_int(&dev_priv->mm.wedged))
136 if (!atomic_read(&dev_priv->mm.wedged))
159 return 0;
160
137 return 0;
138
161 mtx_lock(&dev_priv->error_completion_lock);
162 while (dev_priv->error_completion == 0) {
163 ret = -msleep(&dev_priv->error_completion,
164 &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
165 if (ret == -ERESTART)
166 ret = -ERESTARTSYS;
167 if (ret != 0) {
168 mtx_unlock(&dev_priv->error_completion_lock);
169 return ret;
170 }
139 /*
140 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
141 * userspace. If it takes that long something really bad is going on and
142 * we should simply try to bail out and fail as gracefully as possible.
143 */
144 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
145 if (ret == 0) {
146 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
147 return -EIO;
148 } else if (ret < 0) {
149 return ret;
171 }
150 }
172 mtx_unlock(&dev_priv->error_completion_lock);
173
151
174 if (atomic_load_acq_int(&dev_priv->mm.wedged)) {
152 if (atomic_read(&dev_priv->mm.wedged)) {
175 /* GPU is hung, bump the completion count to account for
176 * the token we just consumed so that we never hit zero and
177 * end up waiting upon a subsequent completion event that
178 * will never happen.
179 */
153 /* GPU is hung, bump the completion count to account for
154 * the token we just consumed so that we never hit zero and
155 * end up waiting upon a subsequent completion event that
156 * will never happen.
157 */
180 mtx_lock(&dev_priv->error_completion_lock);
181 dev_priv->error_completion++;
182 mtx_unlock(&dev_priv->error_completion_lock);
158 mtx_lock(&x->lock);
159 x->done++;
160 mtx_unlock(&x->lock);
183 }
184 return 0;
185}
186
187int i915_mutex_lock_interruptible(struct drm_device *dev)
188{
189 int ret;
190
191 ret = i915_gem_wait_for_error(dev);
192 if (ret)
193 return ret;
194
195 /*
196 * interruptible shall it be. might indeed be if dev_lock is
197 * changed to sx
198 */
161 }
162 return 0;
163}
164
165int i915_mutex_lock_interruptible(struct drm_device *dev)
166{
167 int ret;
168
169 ret = i915_gem_wait_for_error(dev);
170 if (ret)
171 return ret;
172
173 /*
174 * interruptible shall it be. might indeed be if dev_lock is
175 * changed to sx
176 */
199 ret = -sx_xlock_sig(&dev->dev_struct_lock);
177 ret = sx_xlock_sig(&dev->dev_struct_lock);
200 if (ret)
178 if (ret)
201 return ret;
179 return -EINTR;
202
180
181 WARN_ON(i915_verify_lists(dev));
203 return 0;
204}
205
206static inline bool
207i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
208{
182 return 0;
183}
184
185static inline bool
186i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
187{
209 return !obj->active;
188 return obj->gtt_space && !obj->active;
210}
211
212int
213i915_gem_init_ioctl(struct drm_device *dev, void *data,
214 struct drm_file *file)
215{
216 struct drm_i915_gem_init *args = data;
189}
190
191int
192i915_gem_init_ioctl(struct drm_device *dev, void *data,
193 struct drm_file *file)
194{
195 struct drm_i915_gem_init *args = data;
217 drm_i915_private_t *dev_priv = dev->dev_private;
218 int ret;
219
220 if (drm_core_check_feature(dev, DRIVER_MODESET))
221 return -ENODEV;
222
223 if (args->gtt_start >= args->gtt_end ||
224 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
225 return -EINVAL;
226
196
197 if (drm_core_check_feature(dev, DRIVER_MODESET))
198 return -ENODEV;
199
200 if (args->gtt_start >= args->gtt_end ||
201 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
202 return -EINVAL;
203
227 if (mtx_initialized(&dev_priv->mm.gtt_space.unused_lock))
228 return -EBUSY;
229
230 /* GEM with user mode setting was never supported on ilk and later. */
231 if (INTEL_INFO(dev)->gen >= 5)
232 return -ENODEV;
233
234 /*
235 * XXXKIB. The second-time initialization should be guarded
236 * against.
237 */
238 DRM_LOCK(dev);
204 /* GEM with user mode setting was never supported on ilk and later. */
205 if (INTEL_INFO(dev)->gen >= 5)
206 return -ENODEV;
207
208 /*
209 * XXXKIB. The second-time initialization should be guarded
210 * against.
211 */
212 DRM_LOCK(dev);
239 ret = i915_gem_init_global_gtt(dev, args->gtt_start,
213 i915_gem_init_global_gtt(dev, args->gtt_start,
240 args->gtt_end, args->gtt_end);
241 DRM_UNLOCK(dev);
242
214 args->gtt_end, args->gtt_end);
215 DRM_UNLOCK(dev);
216
243 return ret;
217 return 0;
244}
245
246int
247i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
248 struct drm_file *file)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 struct drm_i915_gem_get_aperture *args = data;
252 struct drm_i915_gem_object *obj;
253 size_t pinned;
254
255 pinned = 0;
256 DRM_LOCK(dev);
218}
219
220int
221i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
222 struct drm_file *file)
223{
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 struct drm_i915_gem_get_aperture *args = data;
226 struct drm_i915_gem_object *obj;
227 size_t pinned;
228
229 pinned = 0;
230 DRM_LOCK(dev);
257 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
231 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
258 if (obj->pin_count)
259 pinned += obj->gtt_space->size;
260 DRM_UNLOCK(dev);
261
262 args->aper_size = dev_priv->mm.gtt_total;
263 args->aper_available_size = args->aper_size - pinned;
264
265 return 0;

--- 70 unchanged lines hidden (view full) ---

336{
337 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
338
339 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
340 obj->tiling_mode != I915_TILING_NONE;
341}
342
343static inline int
232 if (obj->pin_count)
233 pinned += obj->gtt_space->size;
234 DRM_UNLOCK(dev);
235
236 args->aper_size = dev_priv->mm.gtt_total;
237 args->aper_available_size = args->aper_size - pinned;
238
239 return 0;

--- 70 unchanged lines hidden (view full) ---

310{
311 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
312
313 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
314 obj->tiling_mode != I915_TILING_NONE;
315}
316
317static inline int
344__copy_to_user_inatomic(void __user *to, const void *from, unsigned n)
345{
346 return (copyout_nofault(from, to, n) != 0 ? n : 0);
347}
348static inline unsigned long
349__copy_from_user_inatomic_nocache(void *to, const void __user *from,
350 unsigned long n)
351{
352
353 /*
354 * XXXKIB. Equivalent Linux function is implemented using
355 * MOVNTI for aligned moves. For unaligned head and tail,
356 * normal move is performed. As such, it is not incorrect, if
357 * only somewhat slower, to use normal copyin. All uses
358 * except shmem_pwrite_fast() have the destination mapped WC.
359 */
360 return ((copyin_nofault(__DECONST(void *, from), to, n) != 0 ? n : 0));
361}
362static inline int
363fault_in_multipages_readable(const char __user *uaddr, int size)
364{
365 char c;
366 int ret = 0;
367 const char __user *end = uaddr + size - 1;
368
369 if (unlikely(size == 0))
370 return ret;
371
372 while (uaddr <= end) {
373 ret = -copyin(uaddr, &c, 1);
374 if (ret != 0)
375 return -EFAULT;
376 uaddr += PAGE_SIZE;
377 }
378
379 /* Check whether the range spilled into the next page. */
380 if (((unsigned long)uaddr & ~PAGE_MASK) ==
381 ((unsigned long)end & ~PAGE_MASK)) {
382 ret = -copyin(end, &c, 1);
383 }
384
385 return ret;
386}
387
388static inline int
389fault_in_multipages_writeable(char __user *uaddr, int size)
390{
391 int ret = 0;
392 char __user *end = uaddr + size - 1;
393
394 if (unlikely(size == 0))
395 return ret;
396
397 /*
398 * Writing zeroes into userspace here is OK, because we know that if
399 * the zero gets there, we'll be overwriting it.
400 */
401 while (uaddr <= end) {
402 ret = subyte(uaddr, 0);
403 if (ret != 0)
404 return -EFAULT;
405 uaddr += PAGE_SIZE;
406 }
407
408 /* Check whether the range spilled into the next page. */
409 if (((unsigned long)uaddr & ~PAGE_MASK) ==
410 ((unsigned long)end & ~PAGE_MASK))
411 ret = subyte(end, 0);
412
413 return ret;
414}
415
416static inline int
417__copy_to_user_swizzled(char __user *cpu_vaddr,
418 const char *gpu_vaddr, int gpu_offset,
419 int length)
420{
421 int ret, cpu_offset = 0;
422
423 while (length > 0) {
424 int cacheline_end = roundup2(gpu_offset + 1, 64);

--- 81 unchanged lines hidden (view full) ---

506 if (unlikely(swizzled)) {
507 unsigned long start = (unsigned long) addr;
508 unsigned long end = (unsigned long) addr + length;
509
510 /* For swizzling simply ensure that we always flush both
511 * channels. Lame, but simple and it works. Swizzled
512 * pwrite/pread is far from a hotpath - current userspace
513 * doesn't use it at all. */
318__copy_to_user_swizzled(char __user *cpu_vaddr,
319 const char *gpu_vaddr, int gpu_offset,
320 int length)
321{
322 int ret, cpu_offset = 0;
323
324 while (length > 0) {
325 int cacheline_end = roundup2(gpu_offset + 1, 64);

--- 81 unchanged lines hidden (view full) ---

407 if (unlikely(swizzled)) {
408 unsigned long start = (unsigned long) addr;
409 unsigned long end = (unsigned long) addr + length;
410
411 /* For swizzling simply ensure that we always flush both
412 * channels. Lame, but simple and it works. Swizzled
413 * pwrite/pread is far from a hotpath - current userspace
414 * doesn't use it at all. */
514 start = rounddown2(start, 128);
515 end = roundup2(end, 128);
415 start = round_down(start, 128);
416 end = round_up(end, 128);
516
517 drm_clflush_virt_range((void *)start, end - start);
518 } else {
519 drm_clflush_virt_range(addr, length);
520 }
521
522}
523

--- 30 unchanged lines hidden (view full) ---

554
555static int
556i915_gem_shmem_pread(struct drm_device *dev,
557 struct drm_i915_gem_object *obj,
558 struct drm_i915_gem_pread *args,
559 struct drm_file *file)
560{
561 char __user *user_data;
417
418 drm_clflush_virt_range((void *)start, end - start);
419 } else {
420 drm_clflush_virt_range(addr, length);
421 }
422
423}
424

--- 30 unchanged lines hidden (view full) ---

455
456static int
457i915_gem_shmem_pread(struct drm_device *dev,
458 struct drm_i915_gem_object *obj,
459 struct drm_i915_gem_pread *args,
460 struct drm_file *file)
461{
462 char __user *user_data;
562 ssize_t remain, sremain;
563 off_t offset, soffset;
463 ssize_t remain;
464 off_t offset;
564 int shmem_page_offset, page_length, ret = 0;
565 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
465 int shmem_page_offset, page_length, ret = 0;
466 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
467 int hit_slowpath = 0;
566 int prefaulted = 0;
567 int needs_clflush = 0;
568
569 user_data = to_user_ptr(args->data_ptr);
468 int prefaulted = 0;
469 int needs_clflush = 0;
470
471 user_data = to_user_ptr(args->data_ptr);
570 sremain = remain = args->size;
472 remain = args->size;
571
572 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
573
574 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
575 /* If we're not in the cpu read domain, set ourself into the gtt
576 * read domain and manually flush cachelines (if required). This
577 * optimizes for the case when the gpu will dirty the data
578 * anyway again before the next pread happens. */
473
474 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
475
476 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
477 /* If we're not in the cpu read domain, set ourself into the gtt
478 * read domain and manually flush cachelines (if required). This
479 * optimizes for the case when the gpu will dirty the data
480 * anyway again before the next pread happens. */
579 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
580 ret = i915_gem_object_set_to_gtt_domain(obj, false);
581 if (ret)
582 return ret;
481 if (obj->cache_level == I915_CACHE_NONE)
482 needs_clflush = 1;
483 if (obj->gtt_space) {
484 ret = i915_gem_object_set_to_gtt_domain(obj, false);
485 if (ret)
486 return ret;
487 }
583 }
584
488 }
489
585 soffset = offset = args->offset;
586 ret = i915_gem_object_get_pages_range(obj, soffset, soffset + sremain);
490 ret = i915_gem_object_get_pages(obj);
587 if (ret)
588 return ret;
589
590 i915_gem_object_pin_pages(obj);
591
491 if (ret)
492 return ret;
493
494 i915_gem_object_pin_pages(obj);
495
496 offset = args->offset;
497
592 VM_OBJECT_WLOCK(obj->base.vm_obj);
593 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
594 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
595 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
596
597 if (remain <= 0)
598 break;
599

--- 11 unchanged lines hidden (view full) ---

611 (page_to_phys(page) & (1 << 17)) != 0;
612
613 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
614 user_data, page_do_bit17_swizzling,
615 needs_clflush);
616 if (ret == 0)
617 goto next_page;
618
498 VM_OBJECT_WLOCK(obj->base.vm_obj);
499 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
500 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
501 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
502
503 if (remain <= 0)
504 break;
505

--- 11 unchanged lines hidden (view full) ---

517 (page_to_phys(page) & (1 << 17)) != 0;
518
519 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
520 user_data, page_do_bit17_swizzling,
521 needs_clflush);
522 if (ret == 0)
523 goto next_page;
524
525 hit_slowpath = 1;
619 DRM_UNLOCK(dev);
620
526 DRM_UNLOCK(dev);
527
621 if (likely(!i915_prefault_disable) && !prefaulted) {
528 if (!prefaulted) {
622 ret = fault_in_multipages_writeable(user_data, remain);
623 /* Userspace is tricking us, but we've already clobbered
624 * its pages with the prefault and promised to write the
625 * data up to the first fault. Hence ignore any errors
626 * and just continue. */
627 (void)ret;
628 prefaulted = 1;
629 }

--- 13 unchanged lines hidden (view full) ---

643 remain -= page_length;
644 user_data += page_length;
645 offset += page_length;
646 VM_OBJECT_WLOCK(obj->base.vm_obj);
647 }
648
649out:
650 i915_gem_object_unpin_pages(obj);
529 ret = fault_in_multipages_writeable(user_data, remain);
530 /* Userspace is tricking us, but we've already clobbered
531 * its pages with the prefault and promised to write the
532 * data up to the first fault. Hence ignore any errors
533 * and just continue. */
534 (void)ret;
535 prefaulted = 1;
536 }

--- 13 unchanged lines hidden (view full) ---

550 remain -= page_length;
551 user_data += page_length;
552 offset += page_length;
553 VM_OBJECT_WLOCK(obj->base.vm_obj);
554 }
555
556out:
557 i915_gem_object_unpin_pages(obj);
651 i915_gem_object_put_pages_range(obj, soffset, soffset + sremain);
652
558
559 if (hit_slowpath) {
560 /* Fixup: Kill any reinstated backing storage pages */
561 if (obj->madv == __I915_MADV_PURGED)
562 i915_gem_object_truncate(obj);
563 }
564
653 return ret;
654}
655
656/**
657 * Reads data from the object referenced by handle.
658 *
659 * On error, the contents of *data are undefined.
660 */

--- 23 unchanged lines hidden (view full) ---

684
685 /* Bounds check source. */
686 if (args->offset > obj->base.size ||
687 args->size > obj->base.size - args->offset) {
688 ret = -EINVAL;
689 goto out;
690 }
691
565 return ret;
566}
567
568/**
569 * Reads data from the object referenced by handle.
570 *
571 * On error, the contents of *data are undefined.
572 */

--- 23 unchanged lines hidden (view full) ---

596
597 /* Bounds check source. */
598 if (args->offset > obj->base.size ||
599 args->size > obj->base.size - args->offset) {
600 ret = -EINVAL;
601 goto out;
602 }
603
692#if 1
693 KIB_NOTYET();
694#else
604#ifdef FREEBSD_WIP
695 /* prime objects have no backing filp to GEM pread/pwrite
696 * pages from.
697 */
698 if (!obj->base.filp) {
699 ret = -EINVAL;
700 goto out;
701 }
605 /* prime objects have no backing filp to GEM pread/pwrite
606 * pages from.
607 */
608 if (!obj->base.filp) {
609 ret = -EINVAL;
610 goto out;
611 }
702#endif
612#endif /* FREEBSD_WIP */
703
704 CTR3(KTR_DRM, "pread %p %jx %jx", obj, args->offset, args->size);
705
706 ret = i915_gem_shmem_pread(dev, obj, args, file);
707
708out:
709 drm_gem_object_unreference(&obj->base);
710unlock:
711 DRM_UNLOCK(dev);
712 return ret;
713}
714
715/* This is the fast write path which cannot handle
716 * page faults in the source data
717 */
718
719static inline int
613
614 CTR3(KTR_DRM, "pread %p %jx %jx", obj, args->offset, args->size);
615
616 ret = i915_gem_shmem_pread(dev, obj, args, file);
617
618out:
619 drm_gem_object_unreference(&obj->base);
620unlock:
621 DRM_UNLOCK(dev);
622 return ret;
623}
624
625/* This is the fast write path which cannot handle
626 * page faults in the source data
627 */
628
629static inline int
720fast_user_write(struct drm_device *dev,
630fast_user_write(vm_paddr_t mapping_addr,
721 off_t page_base, int page_offset,
722 char __user *user_data,
723 int length)
724{
725 void __iomem *vaddr_atomic;
726 void *vaddr;
727 unsigned long unwritten;
728
631 off_t page_base, int page_offset,
632 char __user *user_data,
633 int length)
634{
635 void __iomem *vaddr_atomic;
636 void *vaddr;
637 unsigned long unwritten;
638
729 vaddr_atomic = pmap_mapdev_attr(dev->agp->base + page_base,
639 vaddr_atomic = pmap_mapdev_attr(mapping_addr + page_base,
730 length, PAT_WRITE_COMBINING);
731 /* We can use the cpu mem copy function because this is X86. */
732 vaddr = (char __force*)vaddr_atomic + page_offset;
733 unwritten = __copy_from_user_inatomic_nocache(vaddr,
734 user_data, length);
735 pmap_unmapdev((vm_offset_t)vaddr_atomic, length);
736 return unwritten;
737}
738
739/**
740 * This is the fast pwrite path, where we copy the data directly from the
741 * user into the GTT, uncached.
742 */
743static int
744i915_gem_gtt_pwrite_fast(struct drm_device *dev,
745 struct drm_i915_gem_object *obj,
746 struct drm_i915_gem_pwrite *args,
747 struct drm_file *file)
748{
640 length, PAT_WRITE_COMBINING);
641 /* We can use the cpu mem copy function because this is X86. */
642 vaddr = (char __force*)vaddr_atomic + page_offset;
643 unwritten = __copy_from_user_inatomic_nocache(vaddr,
644 user_data, length);
645 pmap_unmapdev((vm_offset_t)vaddr_atomic, length);
646 return unwritten;
647}
648
649/**
650 * This is the fast pwrite path, where we copy the data directly from the
651 * user into the GTT, uncached.
652 */
653static int
654i915_gem_gtt_pwrite_fast(struct drm_device *dev,
655 struct drm_i915_gem_object *obj,
656 struct drm_i915_gem_pwrite *args,
657 struct drm_file *file)
658{
659 drm_i915_private_t *dev_priv = dev->dev_private;
749 ssize_t remain;
750 off_t offset, page_base;
751 char __user *user_data;
752 int page_offset, page_length, ret;
753
660 ssize_t remain;
661 off_t offset, page_base;
662 char __user *user_data;
663 int page_offset, page_length, ret;
664
754 ret = i915_gem_object_pin(obj, 0, true);
755 /* XXXKIB ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); */
665 ret = i915_gem_object_pin(obj, 0, true, true);
756 if (ret)
757 goto out;
758
759 ret = i915_gem_object_set_to_gtt_domain(obj, true);
760 if (ret)
761 goto out_unpin;
762
763 ret = i915_gem_object_put_fence(obj);

--- 17 unchanged lines hidden (view full) ---

781 page_length = remain;
782 if ((page_offset + remain) > PAGE_SIZE)
783 page_length = PAGE_SIZE - page_offset;
784
785 /* If we get a fault while copying data, then (presumably) our
786 * source page isn't available. Return the error and we'll
787 * retry in the slow path.
788 */
666 if (ret)
667 goto out;
668
669 ret = i915_gem_object_set_to_gtt_domain(obj, true);
670 if (ret)
671 goto out_unpin;
672
673 ret = i915_gem_object_put_fence(obj);

--- 17 unchanged lines hidden (view full) ---

691 page_length = remain;
692 if ((page_offset + remain) > PAGE_SIZE)
693 page_length = PAGE_SIZE - page_offset;
694
695 /* If we get a fault while copying data, then (presumably) our
696 * source page isn't available. Return the error and we'll
697 * retry in the slow path.
698 */
789 if (fast_user_write(dev, page_base,
699 if (fast_user_write(dev_priv->mm.gtt_base_addr, page_base,
790 page_offset, user_data, page_length)) {
791 ret = -EFAULT;
792 goto out_unpin;
793 }
794
795 remain -= page_length;
796 user_data += page_length;
797 offset += page_length;

--- 82 unchanged lines hidden (view full) ---

880}
881
882static int
883i915_gem_shmem_pwrite(struct drm_device *dev,
884 struct drm_i915_gem_object *obj,
885 struct drm_i915_gem_pwrite *args,
886 struct drm_file *file)
887{
700 page_offset, user_data, page_length)) {
701 ret = -EFAULT;
702 goto out_unpin;
703 }
704
705 remain -= page_length;
706 user_data += page_length;
707 offset += page_length;

--- 82 unchanged lines hidden (view full) ---

790}
791
792static int
793i915_gem_shmem_pwrite(struct drm_device *dev,
794 struct drm_i915_gem_object *obj,
795 struct drm_i915_gem_pwrite *args,
796 struct drm_file *file)
797{
888 ssize_t remain, sremain;
889 off_t offset, soffset;
798 ssize_t remain;
799 off_t offset;
890 char __user *user_data;
891 int shmem_page_offset, page_length, ret = 0;
892 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
893 int hit_slowpath = 0;
894 int needs_clflush_after = 0;
895 int needs_clflush_before = 0;
896
897 user_data = to_user_ptr(args->data_ptr);
800 char __user *user_data;
801 int shmem_page_offset, page_length, ret = 0;
802 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
803 int hit_slowpath = 0;
804 int needs_clflush_after = 0;
805 int needs_clflush_before = 0;
806
807 user_data = to_user_ptr(args->data_ptr);
898 sremain = remain = args->size;
808 remain = args->size;
899
900 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
901
902 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
903 /* If we're not in the cpu write domain, set ourself into the gtt
904 * write domain and manually flush cachelines (if required). This
905 * optimizes for the case when the gpu will use the data
906 * right away and we therefore have to clflush anyway. */
809
810 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
811
812 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
813 /* If we're not in the cpu write domain, set ourself into the gtt
814 * write domain and manually flush cachelines (if required). This
815 * optimizes for the case when the gpu will use the data
816 * right away and we therefore have to clflush anyway. */
907 needs_clflush_after = cpu_write_needs_clflush(obj);
908 ret = i915_gem_object_set_to_gtt_domain(obj, true);
909 if (ret)
910 return ret;
817 if (obj->cache_level == I915_CACHE_NONE)
818 needs_clflush_after = 1;
819 if (obj->gtt_space) {
820 ret = i915_gem_object_set_to_gtt_domain(obj, true);
821 if (ret)
822 return ret;
823 }
911 }
824 }
912 /* Same trick applies to invalidate partially written cachelines read
913 * before writing. */
914 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
915 needs_clflush_before =
916 !cpu_cache_is_coherent(dev, obj->cache_level);
825 /* Same trick applies for invalidate partially written cachelines before
826 * writing. */
827 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
828 && obj->cache_level == I915_CACHE_NONE)
829 needs_clflush_before = 1;
917
830
918 soffset = offset = args->offset;
919 ret = i915_gem_object_get_pages_range(obj, soffset, soffset + sremain);
831 ret = i915_gem_object_get_pages(obj);
920 if (ret)
921 return ret;
922
923 i915_gem_object_pin_pages(obj);
924
832 if (ret)
833 return ret;
834
835 i915_gem_object_pin_pages(obj);
836
837 offset = args->offset;
925 obj->dirty = 1;
926
927 VM_OBJECT_WLOCK(obj->base.vm_obj);
928 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
929 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
930 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
931 int partial_cacheline_write;
932

--- 47 unchanged lines hidden (view full) ---

980 remain -= page_length;
981 user_data += page_length;
982 offset += page_length;
983 VM_OBJECT_WLOCK(obj->base.vm_obj);
984 }
985
986out:
987 i915_gem_object_unpin_pages(obj);
838 obj->dirty = 1;
839
840 VM_OBJECT_WLOCK(obj->base.vm_obj);
841 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
842 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
843 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
844 int partial_cacheline_write;
845

--- 47 unchanged lines hidden (view full) ---

893 remain -= page_length;
894 user_data += page_length;
895 offset += page_length;
896 VM_OBJECT_WLOCK(obj->base.vm_obj);
897 }
898
899out:
900 i915_gem_object_unpin_pages(obj);
988 i915_gem_object_put_pages_range(obj, soffset, soffset + sremain);
989
990 if (hit_slowpath) {
901
902 if (hit_slowpath) {
991 /*
992 * Fixup: Flush cpu caches in case we didn't flush the dirty
993 * cachelines in-line while writing and the object moved
994 * out of the cpu write domain while we've dropped the lock.
995 */
996 if (!needs_clflush_after &&
997 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
903 /* Fixup: Kill any reinstated backing storage pages */
904 if (obj->madv == __I915_MADV_PURGED)
905 i915_gem_object_truncate(obj);
906 /* and flush dirty cachelines in case the object isn't in the cpu write
907 * domain anymore. */
908 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
998 i915_gem_clflush_object(obj);
999 i915_gem_chipset_flush(dev);
1000 }
1001 }
1002
1003 if (needs_clflush_after)
1004 i915_gem_chipset_flush(dev);
1005

--- 14 unchanged lines hidden (view full) ---

1020 int ret;
1021
1022 if (args->size == 0)
1023 return 0;
1024
1025 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_READ))
1026 return -EFAULT;
1027
909 i915_gem_clflush_object(obj);
910 i915_gem_chipset_flush(dev);
911 }
912 }
913
914 if (needs_clflush_after)
915 i915_gem_chipset_flush(dev);
916

--- 14 unchanged lines hidden (view full) ---

931 int ret;
932
933 if (args->size == 0)
934 return 0;
935
936 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_READ))
937 return -EFAULT;
938
1028 if (likely(!i915_prefault_disable)) {
1029 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1030 args->size);
1031 if (ret)
1032 return -EFAULT;
1033 }
939 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
940 args->size);
941 if (ret)
942 return -EFAULT;
1034
1035 ret = i915_mutex_lock_interruptible(dev);
1036 if (ret)
1037 return ret;
1038
1039 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1040 if (&obj->base == NULL) {
1041 ret = -ENOENT;
1042 goto unlock;
1043 }
1044
1045 /* Bounds check destination. */
1046 if (args->offset > obj->base.size ||
1047 args->size > obj->base.size - args->offset) {
1048 ret = -EINVAL;
1049 goto out;
1050 }
1051
943
944 ret = i915_mutex_lock_interruptible(dev);
945 if (ret)
946 return ret;
947
948 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
949 if (&obj->base == NULL) {
950 ret = -ENOENT;
951 goto unlock;
952 }
953
954 /* Bounds check destination. */
955 if (args->offset > obj->base.size ||
956 args->size > obj->base.size - args->offset) {
957 ret = -EINVAL;
958 goto out;
959 }
960
1052#if 1
1053 KIB_NOTYET();
1054#else
961#ifdef FREEBSD_WIP
1055 /* prime objects have no backing filp to GEM pread/pwrite
1056 * pages from.
1057 */
1058 if (!obj->base.filp) {
1059 ret = -EINVAL;
1060 goto out;
1061 }
962 /* prime objects have no backing filp to GEM pread/pwrite
963 * pages from.
964 */
965 if (!obj->base.filp) {
966 ret = -EINVAL;
967 goto out;
968 }
1062#endif
969#endif /* FREEBSD_WIP */
1063
1064 CTR3(KTR_DRM, "pwrite %p %jx %jx", obj, args->offset, args->size);
1065
1066 ret = -EFAULT;
1067 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1068 * it would end up going through the fenced access, and we'll get
1069 * different detiling behavior between reading and writing.
1070 * pread/pwrite currently are reading and writing from the CPU
1071 * perspective, requiring manual detiling by the client.
1072 */
1073 if (obj->phys_obj) {
1074 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1075 goto out;
1076 }
1077
970
971 CTR3(KTR_DRM, "pwrite %p %jx %jx", obj, args->offset, args->size);
972
973 ret = -EFAULT;
974 /* We can only do the GTT pwrite on untiled buffers, as otherwise
975 * it would end up going through the fenced access, and we'll get
976 * different detiling behavior between reading and writing.
977 * pread/pwrite currently are reading and writing from the CPU
978 * perspective, requiring manual detiling by the client.
979 */
980 if (obj->phys_obj) {
981 ret = i915_gem_phys_pwrite(dev, obj, args, file);
982 goto out;
983 }
984
1078 if (obj->tiling_mode == I915_TILING_NONE &&
1079 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1080 cpu_write_needs_clflush(obj)) {
985 if (obj->cache_level == I915_CACHE_NONE &&
986 obj->tiling_mode == I915_TILING_NONE &&
987 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1081 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1082 /* Note that the gtt paths might fail with non-page-backed user
1083 * pointers (e.g. gtt mappings when moving data between
1084 * textures). Fallback to the shmem path in that case. */
1085 }
1086
1087 if (ret == -EFAULT || ret == -ENOSPC)
1088 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1089
1090out:
1091 drm_gem_object_unreference(&obj->base);
1092unlock:
1093 DRM_UNLOCK(dev);
1094 return ret;
1095}
1096
988 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
989 /* Note that the gtt paths might fail with non-page-backed user
990 * pointers (e.g. gtt mappings when moving data between
991 * textures). Fallback to the shmem path in that case. */
992 }
993
994 if (ret == -EFAULT || ret == -ENOSPC)
995 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
996
997out:
998 drm_gem_object_unreference(&obj->base);
999unlock:
1000 DRM_UNLOCK(dev);
1001 return ret;
1002}
1003
1097static int
1098i915_gem_check_wedge(struct drm_i915_private *dev_priv)
1004int
1005i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1006 bool interruptible)
1099{
1007{
1100 DRM_LOCK_ASSERT(dev_priv->dev);
1101
1102 if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
1008 if (atomic_read(&dev_priv->mm.wedged)) {
1009 struct completion *x = &dev_priv->error_completion;
1103 bool recovery_complete;
1104
1105 /* Give the error handler a chance to run. */
1010 bool recovery_complete;
1011
1012 /* Give the error handler a chance to run. */
1106 mtx_lock(&dev_priv->error_completion_lock);
1107 recovery_complete = (&dev_priv->error_completion) > 0;
1108 mtx_unlock(&dev_priv->error_completion_lock);
1013 mtx_lock(&x->lock);
1014 recovery_complete = x->done > 0;
1015 mtx_unlock(&x->lock);
1109
1016
1110 return (recovery_complete ? -EIO : -EAGAIN);
1017 /* Non-interruptible callers can't handle -EAGAIN, hence return
1018 * -EIO unconditionally for these. */
1019 if (!interruptible)
1020 return -EIO;
1021
1022 /* Recovery complete, but still wedged means reset failure. */
1023 if (recovery_complete)
1024 return -EIO;
1025
1026 return -EAGAIN;
1111 }
1112
1113 return 0;
1114}
1115
1116/*
1117 * Compare seqno against outstanding lazy request. Emit a request if they are
1118 * equal.
1119 */
1120static int
1121i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1122{
1123 int ret;
1124
1125 DRM_LOCK_ASSERT(ring->dev);
1126
1127 ret = 0;
1027 }
1028
1029 return 0;
1030}
1031
1032/*
1033 * Compare seqno against outstanding lazy request. Emit a request if they are
1034 * equal.
1035 */
1036static int
1037i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1038{
1039 int ret;
1040
1041 DRM_LOCK_ASSERT(ring->dev);
1042
1043 ret = 0;
1128 if (seqno == ring->outstanding_lazy_request) {
1129 struct drm_i915_gem_request *request;
1044 if (seqno == ring->outstanding_lazy_request)
1045 ret = i915_add_request(ring, NULL, NULL);
1130
1046
1131 request = malloc(sizeof(*request), DRM_I915_GEM,
1132 M_WAITOK | M_ZERO);
1133
1134 ret = i915_add_request(ring, NULL, request);
1135 if (ret != 0) {
1136 free(request, DRM_I915_GEM);
1137 return ret;
1138 }
1139
1140 MPASS(seqno == request->seqno);
1141 }
1142 return ret;
1143}
1144
1047 return ret;
1048}
1049
1050/**
1051 * __wait_seqno - wait until execution of seqno has finished
1052 * @ring: the ring expected to report seqno
1053 * @seqno: duh!
1054 * @interruptible: do an interruptible wait (normally yes)
1055 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1056 *
1057 * Returns 0 if the seqno was found within the alloted time. Else returns the
1058 * errno with remaining time filled in timeout argument.
1059 */
1145static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1060static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1146 bool interruptible)
1061 bool interruptible, struct timespec *timeout)
1147{
1148 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1062{
1063 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1149 int ret = 0, flags;
1064 struct timespec before, now, wait_time={1,0};
1065 sbintime_t timeout_sbt;
1066 long end;
1067 bool wait_forever = true;
1068 int ret, flags;
1150
1069
1151 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1070 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1152 return 0;
1153
1154 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
1155
1071 return 0;
1072
1073 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
1074
1156 mtx_lock(&dev_priv->irq_lock);
1157 if (!ring->irq_get(ring)) {
1158 mtx_unlock(&dev_priv->irq_lock);
1159 return -ENODEV;
1075 if (timeout != NULL) {
1076 wait_time = *timeout;
1077 wait_forever = false;
1160 }
1161
1078 }
1079
1080 timeout_sbt = tstosbt(wait_time);
1081
1082 if (WARN_ON(!ring->irq_get(ring)))
1083 return -ENODEV;
1084
1085 /* Record current time in case interrupted by signal, or wedged * */
1086 getrawmonotonic(&before);
1087
1088#define EXIT_COND \
1089 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1090 atomic_read(&dev_priv->mm.wedged))
1162 flags = interruptible ? PCATCH : 0;
1091 flags = interruptible ? PCATCH : 0;
1163 while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
1164 && !atomic_load_acq_int(&dev_priv->mm.wedged) &&
1165 ret == 0) {
1166 ret = -msleep(ring, &dev_priv->irq_lock, flags, "915gwr", 0);
1167 if (ret == -ERESTART)
1168 ret = -ERESTARTSYS;
1169 }
1170 ring->irq_put(ring);
1092 mtx_lock(&dev_priv->irq_lock);
1093 do {
1094 if (EXIT_COND) {
1095 end = 1;
1096 } else {
1097 ret = -msleep_sbt(&ring->irq_queue, &dev_priv->irq_lock, flags,
1098 "915gwr", timeout_sbt, 0, 0);
1099
1100 /*
1101 * NOTE Linux<->FreeBSD: Convert msleep_sbt() return
1102 * value to something close to wait_event*_timeout()
1103 * functions used on Linux.
1104 *
1105 * >0 -> condition is true (end = time remaining)
1106 * =0 -> sleep timed out
1107 * <0 -> error (interrupted)
1108 *
1109 * We fake the remaining time by returning 1. We
1110 * compute a proper value later.
1111 */
1112 if (EXIT_COND)
1113 /* We fake a remaining time of 1 tick. */
1114 end = 1;
1115 else if (ret == -EINTR || ret == -ERESTART)
1116 /* Interrupted. */
1117 end = -ERESTARTSYS;
1118 else
1119 /* Timeout. */
1120 end = 0;
1121 }
1122
1123 ret = i915_gem_check_wedge(dev_priv, interruptible);
1124 if (ret)
1125 end = ret;
1126 } while (end == 0 && wait_forever);
1171 mtx_unlock(&dev_priv->irq_lock);
1172
1127 mtx_unlock(&dev_priv->irq_lock);
1128
1173 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno, ret);
1129 getrawmonotonic(&now);
1174
1130
1175 return ret;
1131 ring->irq_put(ring);
1132 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno, end);
1133#undef EXIT_COND
1134
1135 if (timeout) {
1136 timespecsub(&now, &before);
1137 timespecsub(timeout, &now);
1138 }
1139
1140 switch (end) {
1141 case -EIO:
1142 case -EAGAIN: /* Wedged */
1143 case -ERESTARTSYS: /* Signal */
1144 case -ETIMEDOUT: /* Timeout */
1145 return (int)end;
1146 case 0: /* Timeout */
1147 return -ETIMEDOUT;
1148 default: /* Completed */
1149 WARN_ON(end < 0); /* We're not aware of other errors */
1150 return 0;
1151 }
1176}
1177
1178/**
1179 * Waits for a sequence number to be signaled, and cleans up the
1180 * request and object lists appropriately for that event.
1181 */
1182int
1152}
1153
1154/**
1155 * Waits for a sequence number to be signaled, and cleans up the
1156 * request and object lists appropriately for that event.
1157 */
1158int
1183i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno)
1159i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1184{
1185 struct drm_device *dev = ring->dev;
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1160{
1161 struct drm_device *dev = ring->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 bool interruptible = dev_priv->mm.interruptible;
1187 int ret;
1188
1164 int ret;
1165
1189 KASSERT(seqno != 0, ("Zero seqno"));
1166 DRM_LOCK_ASSERT(dev);
1167 BUG_ON(seqno == 0);
1190
1168
1191 ret = i915_gem_check_wedge(dev_priv);
1169 ret = i915_gem_check_wedge(dev_priv, interruptible);
1192 if (ret)
1193 return ret;
1194
1195 ret = i915_gem_check_olr(ring, seqno);
1196 if (ret)
1197 return ret;
1198
1170 if (ret)
1171 return ret;
1172
1173 ret = i915_gem_check_olr(ring, seqno);
1174 if (ret)
1175 return ret;
1176
1199 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible);
1200 if (atomic_load_acq_int(&dev_priv->mm.wedged))
1201 ret = -EAGAIN;
1202
1203 return ret;
1177 return __wait_seqno(ring, seqno, interruptible, NULL);
1204}
1205
1206/**
1207 * Ensures that all rendering to the object has completed and the object is
1208 * safe to unbind from the GTT or access from the CPU.
1209 */
1210static __must_check int
1178}
1179
1180/**
1181 * Ensures that all rendering to the object has completed and the object is
1182 * safe to unbind from the GTT or access from the CPU.
1183 */
1184static __must_check int
1211i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
1185i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1186 bool readonly)
1212{
1187{
1188 struct intel_ring_buffer *ring = obj->ring;
1189 u32 seqno;
1213 int ret;
1214
1190 int ret;
1191
1215 KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
1216 ("In GPU write domain"));
1192 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1193 if (seqno == 0)
1194 return 0;
1217
1195
1218 CTR5(KTR_DRM, "object_wait_rendering %p %s %x %d %d", obj,
1219 obj->ring != NULL ? obj->ring->name : "none", obj->gtt_offset,
1220 obj->active, obj->last_rendering_seqno);
1221 if (obj->active) {
1222 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
1223 if (ret != 0)
1224 return (ret);
1225 i915_gem_retire_requests_ring(obj->ring);
1196 ret = i915_wait_seqno(ring, seqno);
1197 if (ret)
1198 return ret;
1199
1200 i915_gem_retire_requests_ring(ring);
1201
1202 /* Manually manage the write flush as we may have not yet
1203 * retired the buffer.
1204 */
1205 if (obj->last_write_seqno &&
1206 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1207 obj->last_write_seqno = 0;
1208 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1226 }
1227
1228 return 0;
1229}
1230
1209 }
1210
1211 return 0;
1212}
1213
1214/* A nonblocking variant of the above wait. This is a highly dangerous routine
1215 * as the object state may change during this call.
1216 */
1217static __must_check int
1218i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1219 bool readonly)
1220{
1221 struct drm_device *dev = obj->base.dev;
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 struct intel_ring_buffer *ring = obj->ring;
1224 u32 seqno;
1225 int ret;
1226
1227 DRM_LOCK_ASSERT(dev);
1228 BUG_ON(!dev_priv->mm.interruptible);
1229
1230 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1231 if (seqno == 0)
1232 return 0;
1233
1234 ret = i915_gem_check_wedge(dev_priv, true);
1235 if (ret)
1236 return ret;
1237
1238 ret = i915_gem_check_olr(ring, seqno);
1239 if (ret)
1240 return ret;
1241
1242 DRM_UNLOCK(dev);
1243 ret = __wait_seqno(ring, seqno, true, NULL);
1244 DRM_LOCK(dev);
1245
1246 i915_gem_retire_requests_ring(ring);
1247
1248 /* Manually manage the write flush as we may have not yet
1249 * retired the buffer.
1250 */
1251 if (ret == 0 &&
1252 obj->last_write_seqno &&
1253 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1254 obj->last_write_seqno = 0;
1255 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1256 }
1257
1258 return ret;
1259}
1260
1261/**
1262 * Called when user space prepares to use an object with the CPU, either
1263 * through the mmap ioctl's mapping or a GTT mapping.
1264 */
1231int
1232i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1233 struct drm_file *file)
1234{
1235 struct drm_i915_gem_set_domain *args = data;
1236 struct drm_i915_gem_object *obj;
1237 uint32_t read_domains = args->read_domains;
1238 uint32_t write_domain = args->write_domain;

--- 17 unchanged lines hidden (view full) ---

1256 return ret;
1257
1258 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1259 if (&obj->base == NULL) {
1260 ret = -ENOENT;
1261 goto unlock;
1262 }
1263
1265int
1266i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1267 struct drm_file *file)
1268{
1269 struct drm_i915_gem_set_domain *args = data;
1270 struct drm_i915_gem_object *obj;
1271 uint32_t read_domains = args->read_domains;
1272 uint32_t write_domain = args->write_domain;

--- 17 unchanged lines hidden (view full) ---

1290 return ret;
1291
1292 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1293 if (&obj->base == NULL) {
1294 ret = -ENOENT;
1295 goto unlock;
1296 }
1297
1298 /* Try to flush the object off the GPU without holding the lock.
1299 * We will repeat the flush holding the lock in the normal manner
1300 * to catch cases where we are gazumped.
1301 */
1302 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1303 if (ret)
1304 goto unref;
1305
1264 if (read_domains & I915_GEM_DOMAIN_GTT) {
1265 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1266
1267 /* Silently promote "you're not bound, there was nothing to do"
1268 * to success, since the client was just asking us to
1269 * make sure everything was done.
1270 */
1271 if (ret == -EINVAL)
1272 ret = 0;
1273 } else {
1274 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1275 }
1276
1306 if (read_domains & I915_GEM_DOMAIN_GTT) {
1307 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1308
1309 /* Silently promote "you're not bound, there was nothing to do"
1310 * to success, since the client was just asking us to
1311 * make sure everything was done.
1312 */
1313 if (ret == -EINVAL)
1314 ret = 0;
1315 } else {
1316 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1317 }
1318
1319unref:
1277 drm_gem_object_unreference(&obj->base);
1278unlock:
1279 DRM_UNLOCK(dev);
1280 return ret;
1281}
1282
1283/**
1284 * Called when user space has done writes to this buffer

--- 44 unchanged lines hidden (view full) ---

1329 vm_offset_t addr;
1330 vm_size_t size;
1331 int error, rv;
1332
1333 obj = drm_gem_object_lookup(dev, file, args->handle);
1334 if (obj == NULL)
1335 return -ENOENT;
1336
1320 drm_gem_object_unreference(&obj->base);
1321unlock:
1322 DRM_UNLOCK(dev);
1323 return ret;
1324}
1325
1326/**
1327 * Called when user space has done writes to this buffer

--- 44 unchanged lines hidden (view full) ---

1372 vm_offset_t addr;
1373 vm_size_t size;
1374 int error, rv;
1375
1376 obj = drm_gem_object_lookup(dev, file, args->handle);
1377 if (obj == NULL)
1378 return -ENOENT;
1379
1380#ifdef FREEBSD_WIP
1381 /* prime objects have no backing filp to GEM mmap
1382 * pages from.
1383 */
1384 if (!obj->filp) {
1385 drm_gem_object_unreference_unlocked(obj);
1386 return -EINVAL;
1387 }
1388#endif /* FREEBSD_WIP */
1389
1337 error = 0;
1338 if (args->size == 0)
1339 goto out;
1340 p = curproc;
1341 map = &p->p_vmspace->vm_map;
1342 size = round_page(args->size);
1343 PROC_LOCK(p);
1344 if (map->size + size > lim_cur_proc(p, RLIMIT_VMEM)) {

--- 10 unchanged lines hidden (view full) ---

1355 VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE);
1356 if (rv != KERN_SUCCESS) {
1357 vm_object_deallocate(obj->vm_obj);
1358 error = -vm_mmap_to_errno(rv);
1359 } else {
1360 args->addr_ptr = (uint64_t)addr;
1361 }
1362out:
1390 error = 0;
1391 if (args->size == 0)
1392 goto out;
1393 p = curproc;
1394 map = &p->p_vmspace->vm_map;
1395 size = round_page(args->size);
1396 PROC_LOCK(p);
1397 if (map->size + size > lim_cur_proc(p, RLIMIT_VMEM)) {

--- 10 unchanged lines hidden (view full) ---

1408 VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE);
1409 if (rv != KERN_SUCCESS) {
1410 vm_object_deallocate(obj->vm_obj);
1411 error = -vm_mmap_to_errno(rv);
1412 } else {
1413 args->addr_ptr = (uint64_t)addr;
1414 }
1415out:
1363 drm_gem_object_unreference(obj);
1416 drm_gem_object_unreference_unlocked(obj);
1364 return (error);
1365}
1366
1367static int
1368i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1369 vm_ooffset_t foff, struct ucred *cred, u_short *color)
1370{
1371
1417 return (error);
1418}
1419
1420static int
1421i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1422 vm_ooffset_t foff, struct ucred *cred, u_short *color)
1423{
1424
1425 /*
1426 * NOTE Linux<->FreeBSD: drm_gem_mmap_single() takes care of
1427 * calling drm_gem_object_reference(). That's why we don't
1428 * do this here. i915_gem_pager_dtor(), below, will call
1429 * drm_gem_object_unreference().
1430 *
1431 * On Linux, drm_gem_vm_open() references the object because
1432 * it's called the mapping is copied. drm_gem_vm_open() is not
1433 * called when the mapping is created. So the possible sequences
1434 * are:
1435 * 1. drm_gem_mmap(): ref++
1436 * 2. drm_gem_vm_close(): ref--
1437 *
1438 * 1. drm_gem_mmap(): ref++
1439 * 2. drm_gem_vm_open(): ref++ (for the copied vma)
1440 * 3. drm_gem_vm_close(): ref-- (for the copied vma)
1441 * 4. drm_gem_vm_close(): ref-- (for the initial vma)
1442 *
1443 * On FreeBSD, i915_gem_pager_ctor() is called once during the
1444 * creation of the mapping. No callback is called when the
1445 * mapping is shared during a fork(). i915_gem_pager_dtor() is
1446 * called when the last reference to the mapping is dropped. So
1447 * the only sequence is:
1448 * 1. drm_gem_mmap_single(): ref++
1449 * 2. i915_gem_pager_ctor(): <noop>
1450 * 3. i915_gem_pager_dtor(): ref--
1451 */
1452
1372 *color = 0; /* XXXKIB */
1373 return (0);
1374}
1375
1376/**
1377 * i915_gem_fault - fault a page into the GTT
1378 * vma: VMA in question
1379 * vmf: fault info

--- 11 unchanged lines hidden (view full) ---

1391 */
1392
1393int i915_intr_pf;
1394
1395static int
1396i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1397 vm_page_t *mres)
1398{
1453 *color = 0; /* XXXKIB */
1454 return (0);
1455}
1456
1457/**
1458 * i915_gem_fault - fault a page into the GTT
1459 * vma: VMA in question
1460 * vmf: fault info

--- 11 unchanged lines hidden (view full) ---

1472 */
1473
1474int i915_intr_pf;
1475
1476static int
1477i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1478 vm_page_t *mres)
1479{
1399 struct drm_gem_object *gem_obj;
1400 struct drm_i915_gem_object *obj;
1401 struct drm_device *dev;
1402 drm_i915_private_t *dev_priv;
1480 struct drm_gem_object *gem_obj = vm_obj->handle;
1481 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
1482 struct drm_device *dev = obj->base.dev;
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1403 vm_page_t page, oldpage;
1484 vm_page_t page, oldpage;
1404 int cause, ret;
1405 bool write;
1406
1407 gem_obj = vm_obj->handle;
1408 obj = to_intel_bo(gem_obj);
1409 dev = obj->base.dev;
1410 dev_priv = dev->dev_private;
1411#if 0
1412 write = (prot & VM_PROT_WRITE) != 0;
1485 int ret = 0;
1486#ifdef FREEBSD_WIP
1487 bool write = (prot & VM_PROT_WRITE) != 0;
1413#else
1488#else
1414 write = true;
1415#endif
1489 bool write = true;
1490#endif /* FREEBSD_WIP */
1491 bool pinned;
1492
1416 vm_object_pip_add(vm_obj, 1);
1417
1418 /*
1419 * Remove the placeholder page inserted by vm_fault() from the
1420 * object before dropping the object lock. If
1421 * i915_gem_release_mmap() is active in parallel on this gem
1422 * object, then it owns the drm device sx and might find the
1423 * placeholder already. Then, since the page is busy,
1424 * i915_gem_release_mmap() sleeps waiting for the busy state
1493 vm_object_pip_add(vm_obj, 1);
1494
1495 /*
1496 * Remove the placeholder page inserted by vm_fault() from the
1497 * object before dropping the object lock. If
1498 * i915_gem_release_mmap() is active in parallel on this gem
1499 * object, then it owns the drm device sx and might find the
1500 * placeholder already. Then, since the page is busy,
1501 * i915_gem_release_mmap() sleeps waiting for the busy state
1425 * of the page cleared. We will be not able to acquire drm
1502 * of the page cleared. We will be unable to acquire drm
1426 * device lock until i915_gem_release_mmap() is able to make a
1427 * progress.
1428 */
1429 if (*mres != NULL) {
1430 oldpage = *mres;
1431 vm_page_lock(oldpage);
1432 vm_page_remove(oldpage);
1433 vm_page_unlock(oldpage);
1434 *mres = NULL;
1435 } else
1436 oldpage = NULL;
1437 VM_OBJECT_WUNLOCK(vm_obj);
1438retry:
1503 * device lock until i915_gem_release_mmap() is able to make a
1504 * progress.
1505 */
1506 if (*mres != NULL) {
1507 oldpage = *mres;
1508 vm_page_lock(oldpage);
1509 vm_page_remove(oldpage);
1510 vm_page_unlock(oldpage);
1511 *mres = NULL;
1512 } else
1513 oldpage = NULL;
1514 VM_OBJECT_WUNLOCK(vm_obj);
1515retry:
1439 cause = ret = 0;
1516 ret = 0;
1517 pinned = 0;
1440 page = NULL;
1441
1442 if (i915_intr_pf) {
1443 ret = i915_mutex_lock_interruptible(dev);
1518 page = NULL;
1519
1520 if (i915_intr_pf) {
1521 ret = i915_mutex_lock_interruptible(dev);
1444 if (ret != 0) {
1445 cause = 10;
1522 if (ret != 0)
1446 goto out;
1523 goto out;
1447 }
1448 } else
1449 DRM_LOCK(dev);
1450
1451 /*
1452 * Since the object lock was dropped, other thread might have
1453 * faulted on the same GTT address and instantiated the
1454 * mapping for the page. Recheck.
1455 */

--- 7 unchanged lines hidden (view full) ---

1463 vm_page_busy_sleep(page, "915pee");
1464 goto retry;
1465 }
1466 goto have_page;
1467 } else
1468 VM_OBJECT_WUNLOCK(vm_obj);
1469
1470 /* Now bind it into the GTT if needed */
1524 } else
1525 DRM_LOCK(dev);
1526
1527 /*
1528 * Since the object lock was dropped, other thread might have
1529 * faulted on the same GTT address and instantiated the
1530 * mapping for the page. Recheck.
1531 */

--- 7 unchanged lines hidden (view full) ---

1539 vm_page_busy_sleep(page, "915pee");
1540 goto retry;
1541 }
1542 goto have_page;
1543 } else
1544 VM_OBJECT_WUNLOCK(vm_obj);
1545
1546 /* Now bind it into the GTT if needed */
1471 if (!obj->map_and_fenceable) {
1472 ret = i915_gem_object_unbind(obj);
1473 if (ret != 0) {
1474 cause = 20;
1475 goto unlock;
1476 }
1477 }
1478 if (!obj->gtt_space) {
1479 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1480 if (ret != 0) {
1481 cause = 30;
1482 goto unlock;
1483 }
1547 ret = i915_gem_object_pin(obj, 0, true, false);
1548 if (ret)
1549 goto unlock;
1550 pinned = 1;
1484
1551
1485 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1486 if (ret != 0) {
1487 cause = 40;
1488 goto unlock;
1489 }
1490 }
1552 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1553 if (ret)
1554 goto unpin;
1491
1555
1492 if (!obj->has_global_gtt_mapping)
1493 i915_gem_gtt_bind_object(obj, obj->cache_level);
1494
1495 ret = i915_gem_object_get_fence(obj);
1556 ret = i915_gem_object_get_fence(obj);
1496 if (ret != 0) {
1497 cause = 50;
1498 goto unlock;
1499 }
1557 if (ret)
1558 goto unpin;
1500
1559
1501 if (i915_gem_object_is_inactive(obj))
1502 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1503
1504 obj->fault_mappable = true;
1560 obj->fault_mappable = true;
1561
1505 VM_OBJECT_WLOCK(vm_obj);
1562 VM_OBJECT_WLOCK(vm_obj);
1506 page = PHYS_TO_VM_PAGE(dev->agp->base + obj->gtt_offset + offset);
1563 page = PHYS_TO_VM_PAGE(dev_priv->mm.gtt_base_addr + obj->gtt_offset + offset);
1507 KASSERT((page->flags & PG_FICTITIOUS) != 0,
1508 ("physical address %#jx not fictitious",
1564 KASSERT((page->flags & PG_FICTITIOUS) != 0,
1565 ("physical address %#jx not fictitious",
1509 (uintmax_t)(dev->agp->base + obj->gtt_offset + offset)));
1566 (uintmax_t)(dev_priv->mm.gtt_base_addr + obj->gtt_offset + offset)));
1510 if (page == NULL) {
1511 VM_OBJECT_WUNLOCK(vm_obj);
1567 if (page == NULL) {
1568 VM_OBJECT_WUNLOCK(vm_obj);
1512 cause = 60;
1513 ret = -EFAULT;
1569 ret = -EFAULT;
1514 goto unlock;
1570 goto unpin;
1515 }
1516 KASSERT((page->flags & PG_FICTITIOUS) != 0,
1517 ("not fictitious %p", page));
1518 KASSERT(page->wire_count == 1, ("wire_count not 1 %p", page));
1519
1520 if (vm_page_busied(page)) {
1571 }
1572 KASSERT((page->flags & PG_FICTITIOUS) != 0,
1573 ("not fictitious %p", page));
1574 KASSERT(page->wire_count == 1, ("wire_count not 1 %p", page));
1575
1576 if (vm_page_busied(page)) {
1577 i915_gem_object_unpin(obj);
1521 DRM_UNLOCK(dev);
1522 vm_page_lock(page);
1523 VM_OBJECT_WUNLOCK(vm_obj);
1524 vm_page_busy_sleep(page, "915pbs");
1525 goto retry;
1526 }
1527 if (vm_page_insert(page, vm_obj, OFF_TO_IDX(offset))) {
1578 DRM_UNLOCK(dev);
1579 vm_page_lock(page);
1580 VM_OBJECT_WUNLOCK(vm_obj);
1581 vm_page_busy_sleep(page, "915pbs");
1582 goto retry;
1583 }
1584 if (vm_page_insert(page, vm_obj, OFF_TO_IDX(offset))) {
1585 i915_gem_object_unpin(obj);
1528 DRM_UNLOCK(dev);
1529 VM_OBJECT_WUNLOCK(vm_obj);
1530 VM_WAIT;
1531 goto retry;
1532 }
1533 page->valid = VM_PAGE_BITS_ALL;
1534have_page:
1535 *mres = page;
1536 vm_page_xbusy(page);
1537
1538 CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot,
1539 page->phys_addr);
1586 DRM_UNLOCK(dev);
1587 VM_OBJECT_WUNLOCK(vm_obj);
1588 VM_WAIT;
1589 goto retry;
1590 }
1591 page->valid = VM_PAGE_BITS_ALL;
1592have_page:
1593 *mres = page;
1594 vm_page_xbusy(page);
1595
1596 CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot,
1597 page->phys_addr);
1598 if (pinned) {
1599 /*
1600 * We may have not pinned the object if the page was
1601 * found by the call to vm_page_lookup()
1602 */
1603 i915_gem_object_unpin(obj);
1604 }
1540 DRM_UNLOCK(dev);
1541 if (oldpage != NULL) {
1542 vm_page_lock(oldpage);
1543 vm_page_free(oldpage);
1544 vm_page_unlock(oldpage);
1545 }
1546 vm_object_pip_wakeup(vm_obj);
1547 return (VM_PAGER_OK);
1548
1605 DRM_UNLOCK(dev);
1606 if (oldpage != NULL) {
1607 vm_page_lock(oldpage);
1608 vm_page_free(oldpage);
1609 vm_page_unlock(oldpage);
1610 }
1611 vm_object_pip_wakeup(vm_obj);
1612 return (VM_PAGER_OK);
1613
1614unpin:
1615 i915_gem_object_unpin(obj);
1549unlock:
1550 DRM_UNLOCK(dev);
1551out:
1552 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1616unlock:
1617 DRM_UNLOCK(dev);
1618out:
1619 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1553 CTR5(KTR_DRM, "fault_fail %p %jx %x err %d %d", gem_obj, offset, prot,
1554 -ret, cause);
1620 CTR4(KTR_DRM, "fault_fail %p %jx %x err %d", gem_obj, offset, prot,
1621 -ret);
1555 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1556 kern_yield(PRI_USER);
1557 goto retry;
1558 }
1559 VM_OBJECT_WLOCK(vm_obj);
1560 vm_object_pip_wakeup(vm_obj);
1561 return (VM_PAGER_ERROR);
1562}
1563
1564static void
1565i915_gem_pager_dtor(void *handle)
1566{
1622 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1623 kern_yield(PRI_USER);
1624 goto retry;
1625 }
1626 VM_OBJECT_WLOCK(vm_obj);
1627 vm_object_pip_wakeup(vm_obj);
1628 return (VM_PAGER_ERROR);
1629}
1630
1631static void
1632i915_gem_pager_dtor(void *handle)
1633{
1567 struct drm_gem_object *obj;
1568 struct drm_device *dev;
1634 struct drm_gem_object *obj = handle;
1635 struct drm_device *dev = obj->dev;
1569
1636
1570 obj = handle;
1571 dev = obj->dev;
1572
1573 DRM_LOCK(dev);
1637 DRM_LOCK(dev);
1574 drm_gem_free_mmap_offset(obj);
1575 i915_gem_release_mmap(to_intel_bo(obj));
1576 drm_gem_object_unreference(obj);
1577 DRM_UNLOCK(dev);
1578}
1579
1580struct cdev_pager_ops i915_gem_pager_ops = {
1581 .cdev_pg_fault = i915_gem_pager_fault,
1582 .cdev_pg_ctor = i915_gem_pager_ctor,
1583 .cdev_pg_dtor = i915_gem_pager_dtor

--- 118 unchanged lines hidden (view full) ---

1702
1703 /* Previous hardware however needs to be aligned to a power-of-two
1704 * tile height. The simplest method for determining this is to reuse
1705 * the power-of-tile object size.
1706 */
1707 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1708}
1709
1638 drm_gem_object_unreference(obj);
1639 DRM_UNLOCK(dev);
1640}
1641
1642struct cdev_pager_ops i915_gem_pager_ops = {
1643 .cdev_pg_fault = i915_gem_pager_fault,
1644 .cdev_pg_ctor = i915_gem_pager_ctor,
1645 .cdev_pg_dtor = i915_gem_pager_dtor

--- 118 unchanged lines hidden (view full) ---

1764
1765 /* Previous hardware however needs to be aligned to a power-of-two
1766 * tile height. The simplest method for determining this is to reuse
1767 * the power-of-tile object size.
1768 */
1769 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1770}
1771
1772static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1773{
1774 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1775 int ret;
1776
1777 if (obj->base.on_map)
1778 return 0;
1779
1780 dev_priv->mm.shrinker_no_lock_stealing = true;
1781
1782 ret = drm_gem_create_mmap_offset(&obj->base);
1783 if (ret != -ENOSPC)
1784 goto out;
1785
1786 /* Badly fragmented mmap space? The only way we can recover
1787 * space is by destroying unwanted objects. We can't randomly release
1788 * mmap_offsets as userspace expects them to be persistent for the
1789 * lifetime of the objects. The closest we can is to release the
1790 * offsets on purgeable objects by truncating it and marking it purged,
1791 * which prevents userspace from ever using that object again.
1792 */
1793 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1794 ret = drm_gem_create_mmap_offset(&obj->base);
1795 if (ret != -ENOSPC)
1796 goto out;
1797
1798 i915_gem_shrink_all(dev_priv);
1799 ret = drm_gem_create_mmap_offset(&obj->base);
1800out:
1801 dev_priv->mm.shrinker_no_lock_stealing = false;
1802
1803 return ret;
1804}
1805
1806static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1807{
1808 if (!obj->base.on_map)
1809 return;
1810
1811 drm_gem_free_mmap_offset(&obj->base);
1812}
1813
1710int
1711i915_gem_mmap_gtt(struct drm_file *file,
1712 struct drm_device *dev,
1713 uint32_t handle,
1714 uint64_t *offset)
1715{
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 struct drm_i915_gem_object *obj;

--- 15 unchanged lines hidden (view full) ---

1733 }
1734
1735 if (obj->madv != I915_MADV_WILLNEED) {
1736 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1737 ret = -EINVAL;
1738 goto out;
1739 }
1740
1814int
1815i915_gem_mmap_gtt(struct drm_file *file,
1816 struct drm_device *dev,
1817 uint32_t handle,
1818 uint64_t *offset)
1819{
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 struct drm_i915_gem_object *obj;

--- 15 unchanged lines hidden (view full) ---

1837 }
1838
1839 if (obj->madv != I915_MADV_WILLNEED) {
1840 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1841 ret = -EINVAL;
1842 goto out;
1843 }
1844
1741 ret = drm_gem_create_mmap_offset(&obj->base);
1845 ret = i915_gem_object_create_mmap_offset(obj);
1742 if (ret)
1743 goto out;
1744
1745 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1746 DRM_GEM_MAPPING_KEY;
1747
1748out:
1749 drm_gem_object_unreference(&obj->base);

--- 31 unchanged lines hidden (view full) ---

1781i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1782{
1783 vm_object_t vm_obj;
1784
1785 vm_obj = obj->base.vm_obj;
1786 VM_OBJECT_WLOCK(vm_obj);
1787 vm_object_page_remove(vm_obj, 0, 0, false);
1788 VM_OBJECT_WUNLOCK(vm_obj);
1846 if (ret)
1847 goto out;
1848
1849 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1850 DRM_GEM_MAPPING_KEY;
1851
1852out:
1853 drm_gem_object_unreference(&obj->base);

--- 31 unchanged lines hidden (view full) ---

1885i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1886{
1887 vm_object_t vm_obj;
1888
1889 vm_obj = obj->base.vm_obj;
1890 VM_OBJECT_WLOCK(vm_obj);
1891 vm_object_page_remove(vm_obj, 0, 0, false);
1892 VM_OBJECT_WUNLOCK(vm_obj);
1789 drm_gem_free_mmap_offset(&obj->base);
1790 obj->madv = I915_MADV_PURGED_INTERNAL;
1893 i915_gem_object_free_mmap_offset(obj);
1894
1895 obj->madv = __I915_MADV_PURGED;
1791}
1792
1793static inline int
1794i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1795{
1796 return obj->madv == I915_MADV_DONTNEED;
1797}
1798

--- 42 unchanged lines hidden (view full) ---

1841 ma[i], i, intel_gtt_read_pte(i));
1842 }
1843 }
1844 }
1845}
1846#endif
1847
1848static void
1896}
1897
1898static inline int
1899i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1900{
1901 return obj->madv == I915_MADV_DONTNEED;
1902}
1903

--- 42 unchanged lines hidden (view full) ---

1946 ma[i], i, intel_gtt_read_pte(i));
1947 }
1948 }
1949 }
1950}
1951#endif
1952
1953static void
1849i915_gem_object_put_pages_range(struct drm_i915_gem_object *obj,
1850 off_t start, off_t end)
1851{
1852 vm_object_t vm_obj;
1853
1854 vm_obj = obj->base.vm_obj;
1855 VM_OBJECT_WLOCK(vm_obj);
1856 i915_gem_object_put_pages_range_locked(obj,
1857 OFF_TO_IDX(trunc_page(start)), OFF_TO_IDX(round_page(end)));
1858 VM_OBJECT_WUNLOCK(vm_obj);
1859}
1860
1861static void
1862i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1863{
1864 int page_count = obj->base.size / PAGE_SIZE;
1954i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1955{
1956 int page_count = obj->base.size / PAGE_SIZE;
1865 int i;
1957 int ret, i;
1866
1958
1867 KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
1959 BUG_ON(obj->madv == __I915_MADV_PURGED);
1868
1960
1869 if (obj->tiling_mode != I915_TILING_NONE)
1961 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1962 if (ret) {
1963 /* In the event of a disaster, abandon all caches and
1964 * hope for the best.
1965 */
1966 WARN_ON(ret != -EIO);
1967 i915_gem_clflush_object(obj);
1968 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1969 }
1970
1971 if (i915_gem_object_needs_bit17_swizzle(obj))
1870 i915_gem_object_save_bit_17_swizzle(obj);
1871
1872 if (obj->madv == I915_MADV_DONTNEED)
1873 obj->dirty = 0;
1874
1875 VM_OBJECT_WLOCK(obj->base.vm_obj);
1876#if GEM_PARANOID_CHECK_GTT
1877 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);

--- 15 unchanged lines hidden (view full) ---

1893 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
1894 obj->dirty = 0;
1895
1896 free(obj->pages, DRM_I915_GEM);
1897 obj->pages = NULL;
1898}
1899
1900static int
1972 i915_gem_object_save_bit_17_swizzle(obj);
1973
1974 if (obj->madv == I915_MADV_DONTNEED)
1975 obj->dirty = 0;
1976
1977 VM_OBJECT_WLOCK(obj->base.vm_obj);
1978#if GEM_PARANOID_CHECK_GTT
1979 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);

--- 15 unchanged lines hidden (view full) ---

1995 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
1996 obj->dirty = 0;
1997
1998 free(obj->pages, DRM_I915_GEM);
1999 obj->pages = NULL;
2000}
2001
2002static int
1901i915_gpu_is_active(struct drm_device *dev)
2003i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1902{
2004{
1903 drm_i915_private_t *dev_priv = dev->dev_private;
2005 const struct drm_i915_gem_object_ops *ops = obj->ops;
1904
2006
1905 return (!list_empty(&dev_priv->mm.flushing_list) ||
1906 !list_empty(&dev_priv->mm.active_list));
1907}
2007 if (obj->pages == NULL)
2008 return 0;
1908
2009
1909static void
1910i915_gem_lowmem(void *arg)
1911{
1912 struct drm_device *dev;
1913 struct drm_i915_private *dev_priv;
1914 struct drm_i915_gem_object *obj, *next;
1915 int cnt, cnt_fail, cnt_total;
2010 BUG_ON(obj->gtt_space);
1916
2011
1917 dev = arg;
1918 dev_priv = dev->dev_private;
2012 if (obj->pages_pin_count)
2013 return -EBUSY;
1919
2014
1920 if (!sx_try_xlock(&dev->dev_struct_lock))
1921 return;
2015 /* ->put_pages might need to allocate memory for the bit17 swizzle
2016 * array, hence protect them from being reaped by removing them from gtt
2017 * lists early. */
2018 list_del(&obj->gtt_list);
1922
2019
1923 CTR0(KTR_DRM, "gem_lowmem");
2020 ops->put_pages(obj);
2021 obj->pages = NULL;
1924
2022
1925rescan:
1926 /* first scan for clean buffers */
1927 i915_gem_retire_requests(dev);
2023 if (i915_gem_object_is_purgeable(obj))
2024 i915_gem_object_truncate(obj);
1928
2025
1929 cnt_total = cnt_fail = cnt = 0;
2026 return 0;
2027}
1930
2028
1931 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
1932 mm_list) {
1933 if (i915_gem_object_is_purgeable(obj)) {
1934 if (i915_gem_object_unbind(obj) != 0)
1935 cnt_total++;
1936 } else
1937 cnt_total++;
1938 }
2029static long
2030__i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
2031 bool purgeable_only)
2032{
2033 struct drm_i915_gem_object *obj, *next;
2034 long count = 0;
1939
2035
1940 /* second pass, evict/count anything still on the inactive list */
1941 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
1942 mm_list) {
1943 if (i915_gem_object_unbind(obj) == 0)
1944 cnt++;
1945 else
1946 cnt_fail++;
2036 list_for_each_entry_safe(obj, next,
2037 &dev_priv->mm.unbound_list,
2038 gtt_list) {
2039 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2040 i915_gem_object_put_pages(obj) == 0) {
2041 count += obj->base.size >> PAGE_SHIFT;
2042 if (target != -1 && count >= target)
2043 return count;
2044 }
1947 }
1948
2045 }
2046
1949 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
1950 /*
1951 * We are desperate for pages, so as a last resort, wait
1952 * for the GPU to finish and discard whatever we can.
1953 * This has a dramatic impact to reduce the number of
1954 * OOM-killer events whilst running the GPU aggressively.
1955 */
1956 if (i915_gpu_idle(dev) == 0)
1957 goto rescan;
2047 list_for_each_entry_safe(obj, next,
2048 &dev_priv->mm.inactive_list,
2049 mm_list) {
2050 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2051 i915_gem_object_unbind(obj) == 0 &&
2052 i915_gem_object_put_pages(obj) == 0) {
2053 count += obj->base.size >> PAGE_SHIFT;
2054 if (target != -1 && count >= target)
2055 return count;
2056 }
1958 }
2057 }
1959 DRM_UNLOCK(dev);
2058
2059 return count;
1960}
1961
2060}
2061
2062static long
2063i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2064{
2065 return __i915_gem_shrink(dev_priv, target, true);
2066}
2067
2068static void
2069i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2070{
2071 struct drm_i915_gem_object *obj, *next;
2072
2073 i915_gem_evict_everything(dev_priv->dev);
2074
2075 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
2076 i915_gem_object_put_pages(obj);
2077}
2078
1962static int
1963i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
1964 off_t start, off_t end)
1965{
1966 vm_object_t vm_obj;
1967 vm_page_t page;
1968 vm_pindex_t si, ei, i;
1969 bool need_swizzle, fresh;

--- 14 unchanged lines hidden (view full) ---

1984 return (0);
1985failed:
1986 i915_gem_object_put_pages_range_locked(obj, si, i);
1987 VM_OBJECT_WUNLOCK(vm_obj);
1988 return (-EIO);
1989}
1990
1991static int
2079static int
2080i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
2081 off_t start, off_t end)
2082{
2083 vm_object_t vm_obj;
2084 vm_page_t page;
2085 vm_pindex_t si, ei, i;
2086 bool need_swizzle, fresh;

--- 14 unchanged lines hidden (view full) ---

2101 return (0);
2102failed:
2103 i915_gem_object_put_pages_range_locked(obj, si, i);
2104 VM_OBJECT_WUNLOCK(vm_obj);
2105 return (-EIO);
2106}
2107
2108static int
1992i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1993 int flags)
2109i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1994{
1995 vm_object_t vm_obj;
1996 vm_page_t page;
1997 vm_pindex_t i, page_count;
1998 int res;
1999
2110{
2111 vm_object_t vm_obj;
2112 vm_page_t page;
2113 vm_pindex_t i, page_count;
2114 int res;
2115
2116 /* Assert that the object is not currently in any GPU domain. As it
2117 * wasn't in the GTT, there shouldn't be any way it could have been in
2118 * a GPU cache
2119 */
2120 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2121 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2000 KASSERT(obj->pages == NULL, ("Obj already has pages"));
2001
2002 page_count = OFF_TO_IDX(obj->base.size);
2003 obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2004 M_WAITOK);
2005 res = i915_gem_object_get_pages_range(obj, 0, obj->base.size);
2006 if (res != 0) {
2007 free(obj->pages, DRM_I915_GEM);

--- 7 unchanged lines hidden (view full) ---

2015 KASSERT(page->pindex == i, ("pindex %jx %jx",
2016 (uintmax_t)page->pindex, (uintmax_t)i));
2017 obj->pages[i] = page;
2018 }
2019 VM_OBJECT_WUNLOCK(vm_obj);
2020 return (0);
2021}
2022
2122 KASSERT(obj->pages == NULL, ("Obj already has pages"));
2123
2124 page_count = OFF_TO_IDX(obj->base.size);
2125 obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2126 M_WAITOK);
2127 res = i915_gem_object_get_pages_range(obj, 0, obj->base.size);
2128 if (res != 0) {
2129 free(obj->pages, DRM_I915_GEM);

--- 7 unchanged lines hidden (view full) ---

2137 KASSERT(page->pindex == i, ("pindex %jx %jx",
2138 (uintmax_t)page->pindex, (uintmax_t)i));
2139 obj->pages[i] = page;
2140 }
2141 VM_OBJECT_WUNLOCK(vm_obj);
2142 return (0);
2143}
2144
2145/* Ensure that the associated pages are gathered from the backing storage
2146 * and pinned into our object. i915_gem_object_get_pages() may be called
2147 * multiple times before they are released by a single call to
2148 * i915_gem_object_put_pages() - once the pages are no longer referenced
2149 * either as a result of memory pressure (reaping pages under the shrinker)
2150 * or as the object is itself released.
2151 */
2152int
2153i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2154{
2155 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2156 const struct drm_i915_gem_object_ops *ops = obj->ops;
2157 int ret;
2158
2159 if (obj->pages)
2160 return 0;
2161
2162 BUG_ON(obj->pages_pin_count);
2163
2164 ret = ops->get_pages(obj);
2165 if (ret)
2166 return ret;
2167
2168 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2169 return 0;
2170}
2171
2023void
2024i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2172void
2173i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2025 struct intel_ring_buffer *ring, uint32_t seqno)
2174 struct intel_ring_buffer *ring)
2026{
2027 struct drm_device *dev = obj->base.dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2175{
2176 struct drm_device *dev = obj->base.dev;
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct drm_i915_fence_reg *reg;
2178 u32 seqno = intel_ring_get_seqno(ring);
2030
2179
2031 KASSERT(ring != NULL, ("NULL ring"));
2180 BUG_ON(ring == NULL);
2032 obj->ring = ring;
2033
2034 /* Add a reference if we're newly entering the active list. */
2035 if (!obj->active) {
2036 drm_gem_object_reference(&obj->base);
2037 obj->active = 1;
2038 }
2039
2040 /* Move from whatever list we were on to the tail of execution. */
2041 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2042 list_move_tail(&obj->ring_list, &ring->active_list);
2043
2181 obj->ring = ring;
2182
2183 /* Add a reference if we're newly entering the active list. */
2184 if (!obj->active) {
2185 drm_gem_object_reference(&obj->base);
2186 obj->active = 1;
2187 }
2188
2189 /* Move from whatever list we were on to the tail of execution. */
2190 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2191 list_move_tail(&obj->ring_list, &ring->active_list);
2192
2044 obj->last_rendering_seqno = seqno;
2193 obj->last_read_seqno = seqno;
2194
2045 if (obj->fenced_gpu_access) {
2046 obj->last_fenced_seqno = seqno;
2047
2048 /* Bump MRU to take account of the delayed flush */
2049 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2195 if (obj->fenced_gpu_access) {
2196 obj->last_fenced_seqno = seqno;
2197
2198 /* Bump MRU to take account of the delayed flush */
2199 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2200 struct drm_i915_fence_reg *reg;
2201
2050 reg = &dev_priv->fence_regs[obj->fence_reg];
2051 list_move_tail(&reg->lru_list,
2052 &dev_priv->mm.fence_list);
2053 }
2054 }
2055}
2056
2057static void
2202 reg = &dev_priv->fence_regs[obj->fence_reg];
2203 list_move_tail(&reg->lru_list,
2204 &dev_priv->mm.fence_list);
2205 }
2206 }
2207}
2208
2209static void
2058i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2059{
2060 list_del_init(&obj->ring_list);
2061 obj->last_rendering_seqno = 0;
2062 obj->last_fenced_seqno = 0;
2063}
2064
2065static void
2066i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2067{
2068 struct drm_device *dev = obj->base.dev;
2069 drm_i915_private_t *dev_priv = dev->dev_private;
2070
2071 KASSERT(obj->active, ("Object not active"));
2072 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2073
2074 i915_gem_object_move_off_active(obj);
2075}
2076
2077static void
2078i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2079{
2080 struct drm_device *dev = obj->base.dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082
2210i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2211{
2212 struct drm_device *dev = obj->base.dev;
2213 struct drm_i915_private *dev_priv = dev->dev_private;
2214
2215 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2216 BUG_ON(!obj->active);
2217
2083 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2084
2218 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2219
2085 KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2086 KASSERT(obj->active, ("Object not active"));
2220 list_del_init(&obj->ring_list);
2087 obj->ring = NULL;
2088
2221 obj->ring = NULL;
2222
2089 i915_gem_object_move_off_active(obj);
2223 obj->last_read_seqno = 0;
2224 obj->last_write_seqno = 0;
2225 obj->base.write_domain = 0;
2226
2227 obj->last_fenced_seqno = 0;
2090 obj->fenced_gpu_access = false;
2091
2092 obj->active = 0;
2228 obj->fenced_gpu_access = false;
2229
2230 obj->active = 0;
2093 obj->pending_gpu_write = false;
2094 drm_gem_object_unreference(&obj->base);
2095
2231 drm_gem_object_unreference(&obj->base);
2232
2096#if 1
2097 KIB_NOTYET();
2098#else
2099 WARN_ON(i915_verify_lists(dev));
2233 WARN_ON(i915_verify_lists(dev));
2100#endif
2101}
2102
2234}
2235
2103static u32
2104i915_gem_get_seqno(struct drm_device *dev)
2236static int
2237i915_gem_handle_seqno_wrap(struct drm_device *dev)
2105{
2238{
2106 drm_i915_private_t *dev_priv = dev->dev_private;
2107 u32 seqno = dev_priv->next_seqno;
2239 struct drm_i915_private *dev_priv = dev->dev_private;
2240 struct intel_ring_buffer *ring;
2241 int ret, i, j;
2108
2242
2109 /* reserve 0 for non-seqno */
2110 if (++dev_priv->next_seqno == 0)
2111 dev_priv->next_seqno = 1;
2243 /* The hardware uses various monotonic 32-bit counters, if we
2244 * detect that they will wraparound we need to idle the GPU
2245 * and reset those counters.
2246 */
2247 ret = 0;
2248 for_each_ring(ring, dev_priv, i) {
2249 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2250 ret |= ring->sync_seqno[j] != 0;
2251 }
2252 if (ret == 0)
2253 return ret;
2112
2254
2113 return seqno;
2255 ret = i915_gpu_idle(dev);
2256 if (ret)
2257 return ret;
2258
2259 i915_gem_retire_requests(dev);
2260 for_each_ring(ring, dev_priv, i) {
2261 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2262 ring->sync_seqno[j] = 0;
2263 }
2264
2265 return 0;
2114}
2115
2266}
2267
2116u32
2117i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2268int
2269i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2118{
2270{
2119 if (ring->outstanding_lazy_request == 0)
2120 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2121
2272
2122 return ring->outstanding_lazy_request;
2273 /* reserve 0 for non-seqno */
2274 if (dev_priv->next_seqno == 0) {
2275 int ret = i915_gem_handle_seqno_wrap(dev);
2276 if (ret)
2277 return ret;
2278
2279 dev_priv->next_seqno = 1;
2280 }
2281
2282 *seqno = dev_priv->next_seqno++;
2283 return 0;
2123}
2124
2125int
2126i915_add_request(struct intel_ring_buffer *ring,
2127 struct drm_file *file,
2284}
2285
2286int
2287i915_add_request(struct intel_ring_buffer *ring,
2288 struct drm_file *file,
2128 struct drm_i915_gem_request *request)
2289 u32 *out_seqno)
2129{
2130 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2290{
2291 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2131 struct drm_i915_file_private *file_priv;
2132 uint32_t seqno;
2292 struct drm_i915_gem_request *request;
2133 u32 request_ring_position;
2134 int was_empty;
2135 int ret;
2136
2293 u32 request_ring_position;
2294 int was_empty;
2295 int ret;
2296
2137 KASSERT(request != NULL, ("NULL request in add"));
2138 DRM_LOCK_ASSERT(ring->dev);
2297 /*
2298 * Emit any outstanding flushes - execbuf can fail to emit the flush
2299 * after having emitted the batchbuffer command. Hence we need to fix
2300 * things up similar to emitting the lazy request. The difference here
2301 * is that the flush _must_ happen before the next request, no matter
2302 * what.
2303 */
2304 ret = intel_ring_flush_all_caches(ring);
2305 if (ret)
2306 return ret;
2139
2307
2140 seqno = i915_gem_next_request_seqno(ring);
2141 request_ring_position = intel_ring_get_tail(ring);
2308 request = malloc(sizeof(*request), DRM_I915_GEM, M_NOWAIT);
2309 if (request == NULL)
2310 return -ENOMEM;
2142
2311
2143 ret = ring->add_request(ring, &seqno);
2144 if (ret != 0)
2145 return ret;
2146
2312
2147 CTR2(KTR_DRM, "request_add %s %d", ring->name, seqno);
2313 /* Record the position of the start of the request so that
2314 * should we detect the updated seqno part-way through the
2315 * GPU processing the request, we never over-estimate the
2316 * position of the head.
2317 */
2318 request_ring_position = intel_ring_get_tail(ring);
2148
2319
2149 request->seqno = seqno;
2320 ret = ring->add_request(ring);
2321 if (ret) {
2322 free(request, DRM_I915_GEM);
2323 return ret;
2324 }
2325
2326 request->seqno = intel_ring_get_seqno(ring);
2150 request->ring = ring;
2151 request->tail = request_ring_position;
2327 request->ring = ring;
2328 request->tail = request_ring_position;
2152 request->emitted_jiffies = ticks;
2329 request->emitted_jiffies = jiffies;
2153 was_empty = list_empty(&ring->request_list);
2154 list_add_tail(&request->list, &ring->request_list);
2330 was_empty = list_empty(&ring->request_list);
2331 list_add_tail(&request->list, &ring->request_list);
2332 request->file_priv = NULL;
2155
2156 if (file) {
2333
2334 if (file) {
2157 file_priv = file->driver_priv;
2335 struct drm_i915_file_private *file_priv = file->driver_priv;
2158
2336
2159 mtx_lock(&file_priv->mm.lck);
2337 mtx_lock(&file_priv->mm.lock);
2160 request->file_priv = file_priv;
2161 list_add_tail(&request->client_list,
2162 &file_priv->mm.request_list);
2338 request->file_priv = file_priv;
2339 list_add_tail(&request->client_list,
2340 &file_priv->mm.request_list);
2163 mtx_unlock(&file_priv->mm.lck);
2341 mtx_unlock(&file_priv->mm.lock);
2164 }
2165
2342 }
2343
2344 CTR2(KTR_DRM, "request_add %s %d", ring->name, request->seqno);
2166 ring->outstanding_lazy_request = 0;
2167
2168 if (!dev_priv->mm.suspended) {
2169 if (i915_enable_hangcheck) {
2170 callout_schedule(&dev_priv->hangcheck_timer,
2171 DRM_I915_HANGCHECK_PERIOD);
2172 }
2345 ring->outstanding_lazy_request = 0;
2346
2347 if (!dev_priv->mm.suspended) {
2348 if (i915_enable_hangcheck) {
2349 callout_schedule(&dev_priv->hangcheck_timer,
2350 DRM_I915_HANGCHECK_PERIOD);
2351 }
2173 if (was_empty)
2174 taskqueue_enqueue_timeout(dev_priv->tq,
2175 &dev_priv->mm.retire_task, hz);
2352 if (was_empty) {
2353 taskqueue_enqueue_timeout(dev_priv->wq,
2354 &dev_priv->mm.retire_work, hz);
2355 intel_mark_busy(dev_priv->dev);
2356 }
2176 }
2177
2357 }
2358
2359 if (out_seqno)
2360 *out_seqno = request->seqno;
2178 return 0;
2179}
2180
2181static inline void
2182i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2183{
2184 struct drm_i915_file_private *file_priv = request->file_priv;
2185
2186 if (!file_priv)
2187 return;
2188
2361 return 0;
2362}
2363
2364static inline void
2365i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2366{
2367 struct drm_i915_file_private *file_priv = request->file_priv;
2368
2369 if (!file_priv)
2370 return;
2371
2189 DRM_LOCK_ASSERT(request->ring->dev);
2190
2191 mtx_lock(&file_priv->mm.lck);
2372 mtx_lock(&file_priv->mm.lock);
2192 if (request->file_priv) {
2193 list_del(&request->client_list);
2194 request->file_priv = NULL;
2195 }
2373 if (request->file_priv) {
2374 list_del(&request->client_list);
2375 request->file_priv = NULL;
2376 }
2196 mtx_unlock(&file_priv->mm.lck);
2377 mtx_unlock(&file_priv->mm.lock);
2197}
2198
2199static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2200 struct intel_ring_buffer *ring)
2201{
2202 if (ring->dev != NULL)
2203 DRM_LOCK_ASSERT(ring->dev);
2204

--- 11 unchanged lines hidden (view full) ---

2216
2217 while (!list_empty(&ring->active_list)) {
2218 struct drm_i915_gem_object *obj;
2219
2220 obj = list_first_entry(&ring->active_list,
2221 struct drm_i915_gem_object,
2222 ring_list);
2223
2378}
2379
2380static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2381 struct intel_ring_buffer *ring)
2382{
2383 if (ring->dev != NULL)
2384 DRM_LOCK_ASSERT(ring->dev);
2385

--- 11 unchanged lines hidden (view full) ---

2397
2398 while (!list_empty(&ring->active_list)) {
2399 struct drm_i915_gem_object *obj;
2400
2401 obj = list_first_entry(&ring->active_list,
2402 struct drm_i915_gem_object,
2403 ring_list);
2404
2224 obj->base.write_domain = 0;
2225 list_del_init(&obj->gpu_write_list);
2226 i915_gem_object_move_to_inactive(obj);
2227 }
2228}
2229
2230static void i915_gem_reset_fences(struct drm_device *dev)
2231{
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233 int i;

--- 19 unchanged lines hidden (view full) ---

2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254 struct drm_i915_gem_object *obj;
2255 struct intel_ring_buffer *ring;
2256 int i;
2257
2258 for_each_ring(ring, dev_priv, i)
2259 i915_gem_reset_ring_lists(dev_priv, ring);
2260
2405 i915_gem_object_move_to_inactive(obj);
2406 }
2407}
2408
2409static void i915_gem_reset_fences(struct drm_device *dev)
2410{
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 int i;

--- 19 unchanged lines hidden (view full) ---

2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct drm_i915_gem_object *obj;
2434 struct intel_ring_buffer *ring;
2435 int i;
2436
2437 for_each_ring(ring, dev_priv, i)
2438 i915_gem_reset_ring_lists(dev_priv, ring);
2439
2261 /* Remove anything from the flushing lists. The GPU cache is likely
2262 * to be lost on reset along with the data, so simply move the
2263 * lost bo to the inactive list.
2264 */
2265 while (!list_empty(&dev_priv->mm.flushing_list)) {
2266 obj = list_first_entry(&dev_priv->mm.flushing_list,
2267 struct drm_i915_gem_object,
2268 mm_list);
2269
2270 obj->base.write_domain = 0;
2271 list_del_init(&obj->gpu_write_list);
2272 i915_gem_object_move_to_inactive(obj);
2273 }
2274
2275 /* Move everything out of the GPU domains to ensure we do any
2276 * necessary invalidation upon reuse.
2277 */
2440 /* Move everything out of the GPU domains to ensure we do any
2441 * necessary invalidation upon reuse.
2442 */
2278 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2443 list_for_each_entry(obj,
2444 &dev_priv->mm.inactive_list,
2445 mm_list)
2446 {
2279 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2280 }
2281
2282 /* The fence registers are invalidated so clear them out */
2283 i915_gem_reset_fences(dev);
2284}
2285
2286/**
2287 * This function clears the request list as sequence numbers are passed.
2288 */
2289void
2290i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2291{
2292 uint32_t seqno;
2447 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2448 }
2449
2450 /* The fence registers are invalidated so clear them out */
2451 i915_gem_reset_fences(dev);
2452}
2453
2454/**
2455 * This function clears the request list as sequence numbers are passed.
2456 */
2457void
2458i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2459{
2460 uint32_t seqno;
2293 int i;
2294
2295 if (list_empty(&ring->request_list))
2296 return;
2297
2461
2462 if (list_empty(&ring->request_list))
2463 return;
2464
2298 seqno = ring->get_seqno(ring);
2465 WARN_ON(i915_verify_lists(ring->dev));
2466
2467 seqno = ring->get_seqno(ring, true);
2299 CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
2300
2468 CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
2469
2301 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
2302 if (seqno >= ring->sync_seqno[i])
2303 ring->sync_seqno[i] = 0;
2304
2305 while (!list_empty(&ring->request_list)) {
2306 struct drm_i915_gem_request *request;
2307
2308 request = list_first_entry(&ring->request_list,
2309 struct drm_i915_gem_request,
2310 list);
2311
2312 if (!i915_seqno_passed(seqno, request->seqno))
2313 break;
2314
2315 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
2316 ring->name, seqno);
2470 while (!list_empty(&ring->request_list)) {
2471 struct drm_i915_gem_request *request;
2472
2473 request = list_first_entry(&ring->request_list,
2474 struct drm_i915_gem_request,
2475 list);
2476
2477 if (!i915_seqno_passed(seqno, request->seqno))
2478 break;
2479
2480 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
2481 ring->name, seqno);
2482 /* We know the GPU must have read the request to have
2483 * sent us the seqno + interrupt, so use the position
2484 * of tail of the request to update the last known position
2485 * of the GPU head.
2486 */
2317 ring->last_retired_head = request->tail;
2318
2319 list_del(&request->list);
2320 i915_gem_request_remove_from_client(request);
2321 free(request, DRM_I915_GEM);
2322 }
2323
2324 /* Move any buffers on the active list that are no longer referenced
2325 * by the ringbuffer to the flushing/inactive lists as appropriate.
2326 */
2327 while (!list_empty(&ring->active_list)) {
2328 struct drm_i915_gem_object *obj;
2329
2330 obj = list_first_entry(&ring->active_list,
2331 struct drm_i915_gem_object,
2332 ring_list);
2333
2487 ring->last_retired_head = request->tail;
2488
2489 list_del(&request->list);
2490 i915_gem_request_remove_from_client(request);
2491 free(request, DRM_I915_GEM);
2492 }
2493
2494 /* Move any buffers on the active list that are no longer referenced
2495 * by the ringbuffer to the flushing/inactive lists as appropriate.
2496 */
2497 while (!list_empty(&ring->active_list)) {
2498 struct drm_i915_gem_object *obj;
2499
2500 obj = list_first_entry(&ring->active_list,
2501 struct drm_i915_gem_object,
2502 ring_list);
2503
2334 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2504 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2335 break;
2336
2505 break;
2506
2337 if (obj->base.write_domain != 0)
2338 i915_gem_object_move_to_flushing(obj);
2339 else
2340 i915_gem_object_move_to_inactive(obj);
2507 i915_gem_object_move_to_inactive(obj);
2341 }
2342
2508 }
2509
2343 if (ring->trace_irq_seqno &&
2344 i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2345 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2346 mtx_lock(&dev_priv->irq_lock);
2510 if (unlikely(ring->trace_irq_seqno &&
2511 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2347 ring->irq_put(ring);
2512 ring->irq_put(ring);
2348 mtx_unlock(&dev_priv->irq_lock);
2349 ring->trace_irq_seqno = 0;
2350 }
2513 ring->trace_irq_seqno = 0;
2514 }
2515
2516 WARN_ON(i915_verify_lists(ring->dev));
2351}
2352
2353void
2354i915_gem_retire_requests(struct drm_device *dev)
2355{
2356 drm_i915_private_t *dev_priv = dev->dev_private;
2357 struct intel_ring_buffer *ring;
2358 int i;
2359
2360 for_each_ring(ring, dev_priv, i)
2361 i915_gem_retire_requests_ring(ring);
2362}
2363
2364static void
2517}
2518
2519void
2520i915_gem_retire_requests(struct drm_device *dev)
2521{
2522 drm_i915_private_t *dev_priv = dev->dev_private;
2523 struct intel_ring_buffer *ring;
2524 int i;
2525
2526 for_each_ring(ring, dev_priv, i)
2527 i915_gem_retire_requests_ring(ring);
2528}
2529
2530static void
2365i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2366 uint32_t flush_domains)
2531i915_gem_retire_work_handler(void *arg, int pending)
2367{
2532{
2368 struct drm_i915_gem_object *obj, *next;
2369 uint32_t old_write_domain;
2370
2371 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2372 gpu_write_list) {
2373 if (obj->base.write_domain & flush_domains) {
2374 old_write_domain = obj->base.write_domain;
2375 obj->base.write_domain = 0;
2376 list_del_init(&obj->gpu_write_list);
2377 i915_gem_object_move_to_active(obj, ring,
2378 i915_gem_next_request_seqno(ring));
2379
2380 CTR3(KTR_DRM, "object_change_domain process_flush %p %x %x",
2381 obj, obj->base.read_domains, old_write_domain);
2382 }
2383 }
2384}
2385
2386int
2387i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2388 uint32_t flush_domains)
2389{
2390 int ret;
2391
2392 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2393 return 0;
2394
2395 CTR3(KTR_DRM, "ring_flush %s %x %x", ring->name, invalidate_domains,
2396 flush_domains);
2397 ret = ring->flush(ring, invalidate_domains, flush_domains);
2398 if (ret)
2399 return ret;
2400
2401 if (flush_domains & I915_GEM_GPU_DOMAINS)
2402 i915_gem_process_flushing_list(ring, flush_domains);
2403 return 0;
2404}
2405
2406static void
2407i915_gem_retire_task_handler(void *arg, int pending)
2408{
2409 drm_i915_private_t *dev_priv;
2410 struct drm_device *dev;
2411 struct intel_ring_buffer *ring;
2412 bool idle;
2413 int i;
2414
2415 dev_priv = arg;
2416 dev = dev_priv->dev;
2417
2418 /* Come back later if the device is busy... */
2419 if (!sx_try_xlock(&dev->dev_struct_lock)) {
2533 drm_i915_private_t *dev_priv;
2534 struct drm_device *dev;
2535 struct intel_ring_buffer *ring;
2536 bool idle;
2537 int i;
2538
2539 dev_priv = arg;
2540 dev = dev_priv->dev;
2541
2542 /* Come back later if the device is busy... */
2543 if (!sx_try_xlock(&dev->dev_struct_lock)) {
2420 taskqueue_enqueue_timeout(dev_priv->tq,
2421 &dev_priv->mm.retire_task, hz);
2544 taskqueue_enqueue_timeout(dev_priv->wq,
2545 &dev_priv->mm.retire_work, hz);
2422 return;
2423 }
2424
2425 CTR0(KTR_DRM, "retire_task");
2426
2427 i915_gem_retire_requests(dev);
2428
2429 /* Send a periodic flush down the ring so we don't hold onto GEM
2430 * objects indefinitely.
2431 */
2432 idle = true;
2433 for_each_ring(ring, dev_priv, i) {
2546 return;
2547 }
2548
2549 CTR0(KTR_DRM, "retire_task");
2550
2551 i915_gem_retire_requests(dev);
2552
2553 /* Send a periodic flush down the ring so we don't hold onto GEM
2554 * objects indefinitely.
2555 */
2556 idle = true;
2557 for_each_ring(ring, dev_priv, i) {
2434 struct intel_ring_buffer *ring = &dev_priv->rings[i];
2558 if (ring->gpu_caches_dirty)
2559 i915_add_request(ring, NULL, NULL);
2435
2560
2436 if (!list_empty(&ring->gpu_write_list)) {
2437 struct drm_i915_gem_request *request;
2438 int ret;
2439
2440 ret = i915_gem_flush_ring(ring,
2441 0, I915_GEM_GPU_DOMAINS);
2442 request = malloc(sizeof(*request), DRM_I915_GEM,
2443 M_WAITOK | M_ZERO);
2444 if (ret || request == NULL ||
2445 i915_add_request(ring, NULL, request))
2446 free(request, DRM_I915_GEM);
2447 }
2448
2449 idle &= list_empty(&ring->request_list);
2450 }
2451
2452 if (!dev_priv->mm.suspended && !idle)
2561 idle &= list_empty(&ring->request_list);
2562 }
2563
2564 if (!dev_priv->mm.suspended && !idle)
2453 taskqueue_enqueue_timeout(dev_priv->tq,
2454 &dev_priv->mm.retire_task, hz);
2565 taskqueue_enqueue_timeout(dev_priv->wq,
2566 &dev_priv->mm.retire_work, hz);
2567 if (idle)
2568 intel_mark_idle(dev);
2455
2456 DRM_UNLOCK(dev);
2457}
2458
2569
2570 DRM_UNLOCK(dev);
2571}
2572
2573/**
2574 * Ensures that an object will eventually get non-busy by flushing any required
2575 * write domains, emitting any outstanding lazy request and retiring and
2576 * completed requests.
2577 */
2578static int
2579i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2580{
2581 int ret;
2582
2583 if (obj->active) {
2584 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2585 if (ret)
2586 return ret;
2587
2588 i915_gem_retire_requests_ring(obj->ring);
2589 }
2590
2591 return 0;
2592}
2593
2594/**
2595 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2596 * @DRM_IOCTL_ARGS: standard ioctl arguments
2597 *
2598 * Returns 0 if successful, else an error is returned with the remaining time in
2599 * the timeout parameter.
2600 * -ETIME: object is still busy after timeout
2601 * -ERESTARTSYS: signal interrupted the wait
2602 * -ENONENT: object doesn't exist
2603 * Also possible, but rare:
2604 * -EAGAIN: GPU wedged
2605 * -ENOMEM: damn
2606 * -ENODEV: Internal IRQ fail
2607 * -E?: The add request failed
2608 *
2609 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2610 * non-zero timeout parameter the wait ioctl will wait for the given number of
2611 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2612 * without holding struct_mutex the object may become re-busied before this
2613 * function completes. A similar but shorter * race condition exists in the busy
2614 * ioctl
2615 */
2459int
2616int
2617i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2618{
2619 struct drm_i915_gem_wait *args = data;
2620 struct drm_i915_gem_object *obj;
2621 struct intel_ring_buffer *ring = NULL;
2622 struct timespec timeout_stack, *timeout = NULL;
2623 u32 seqno = 0;
2624 int ret = 0;
2625
2626 if (args->timeout_ns >= 0) {
2627 timeout_stack.tv_sec = args->timeout_ns / 1000000;
2628 timeout_stack.tv_nsec = args->timeout_ns % 1000000;
2629 timeout = &timeout_stack;
2630 }
2631
2632 ret = i915_mutex_lock_interruptible(dev);
2633 if (ret)
2634 return ret;
2635
2636 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2637 if (&obj->base == NULL) {
2638 DRM_UNLOCK(dev);
2639 return -ENOENT;
2640 }
2641
2642 /* Need to make sure the object gets inactive eventually. */
2643 ret = i915_gem_object_flush_active(obj);
2644 if (ret)
2645 goto out;
2646
2647 if (obj->active) {
2648 seqno = obj->last_read_seqno;
2649 ring = obj->ring;
2650 }
2651
2652 if (seqno == 0)
2653 goto out;
2654
2655 /* Do this after OLR check to make sure we make forward progress polling
2656 * on this IOCTL with a 0 timeout (like busy ioctl)
2657 */
2658 if (!args->timeout_ns) {
2659 ret = -ETIMEDOUT;
2660 goto out;
2661 }
2662
2663 drm_gem_object_unreference(&obj->base);
2664 DRM_UNLOCK(dev);
2665
2666 ret = __wait_seqno(ring, seqno, true, timeout);
2667 if (timeout) {
2668 args->timeout_ns = timeout->tv_sec * 1000000 + timeout->tv_nsec;
2669 }
2670 return ret;
2671
2672out:
2673 drm_gem_object_unreference(&obj->base);
2674 DRM_UNLOCK(dev);
2675 return ret;
2676}
2677
2678/**
2679 * i915_gem_object_sync - sync an object to a ring.
2680 *
2681 * @obj: object which may be in use on another ring.
2682 * @to: ring we wish to use the object on. May be NULL.
2683 *
2684 * This code is meant to abstract object synchronization with the GPU.
2685 * Calling with NULL implies synchronizing the object with the CPU
2686 * rather than a particular GPU ring.
2687 *
2688 * Returns 0 if successful, else propagates up the lower layer error.
2689 */
2690int
2460i915_gem_object_sync(struct drm_i915_gem_object *obj,
2461 struct intel_ring_buffer *to)
2462{
2463 struct intel_ring_buffer *from = obj->ring;
2464 u32 seqno;
2465 int ret, idx;
2466
2467 if (from == NULL || to == from)
2468 return 0;
2469
2470 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2691i915_gem_object_sync(struct drm_i915_gem_object *obj,
2692 struct intel_ring_buffer *to)
2693{
2694 struct intel_ring_buffer *from = obj->ring;
2695 u32 seqno;
2696 int ret, idx;
2697
2698 if (from == NULL || to == from)
2699 return 0;
2700
2701 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2471 return i915_gem_object_wait_rendering(obj);
2702 return i915_gem_object_wait_rendering(obj, false);
2472
2473 idx = intel_ring_sync_index(from, to);
2474
2703
2704 idx = intel_ring_sync_index(from, to);
2705
2475 seqno = obj->last_rendering_seqno;
2706 seqno = obj->last_read_seqno;
2476 if (seqno <= from->sync_seqno[idx])
2477 return 0;
2478
2707 if (seqno <= from->sync_seqno[idx])
2708 return 0;
2709
2479 if (seqno == from->outstanding_lazy_request) {
2480 struct drm_i915_gem_request *request;
2710 ret = i915_gem_check_olr(obj->ring, seqno);
2711 if (ret)
2712 return ret;
2481
2713
2482 request = malloc(sizeof(*request), DRM_I915_GEM,
2483 M_WAITOK | M_ZERO);
2484 ret = i915_add_request(from, NULL, request);
2485 if (ret) {
2486 free(request, DRM_I915_GEM);
2487 return ret;
2488 }
2489 seqno = request->seqno;
2490 }
2491
2492
2493 ret = to->sync_to(to, from, seqno);
2494 if (!ret)
2714 ret = to->sync_to(to, from, seqno);
2715 if (!ret)
2495 from->sync_seqno[idx] = seqno;
2716 /* We use last_read_seqno because sync_to()
2717 * might have just caused seqno wrap under
2718 * the radar.
2719 */
2720 from->sync_seqno[idx] = obj->last_read_seqno;
2496
2497 return ret;
2498}
2499
2500static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2501{
2502 u32 old_write_domain, old_read_domains;
2503

--- 24 unchanged lines hidden (view full) ---

2528{
2529 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2530 int ret = 0;
2531
2532 if (obj->gtt_space == NULL)
2533 return 0;
2534
2535 if (obj->pin_count)
2721
2722 return ret;
2723}
2724
2725static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2726{
2727 u32 old_write_domain, old_read_domains;
2728

--- 24 unchanged lines hidden (view full) ---

2753{
2754 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2755 int ret = 0;
2756
2757 if (obj->gtt_space == NULL)
2758 return 0;
2759
2760 if (obj->pin_count)
2536 return -EINVAL;
2761 return -EBUSY;
2537
2762
2763 BUG_ON(obj->pages == NULL);
2764
2538 ret = i915_gem_object_finish_gpu(obj);
2765 ret = i915_gem_object_finish_gpu(obj);
2539 if (ret == -ERESTARTSYS || ret == -EINTR)
2766 if (ret)
2540 return ret;
2767 return ret;
2768 /* Continue on if we fail due to EIO, the GPU is hung so we
2769 * should be safe and we need to cleanup or else we might
2770 * cause memory corruption through use-after-free.
2771 */
2541
2542 i915_gem_object_finish_gtt(obj);
2543
2772
2773 i915_gem_object_finish_gtt(obj);
2774
2544 if (ret == 0)
2545 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2546 if (ret == -ERESTARTSYS || ret == -EINTR)
2547 return ret;
2548 if (ret != 0) {
2549 i915_gem_clflush_object(obj);
2550 obj->base.read_domains = obj->base.write_domain =
2551 I915_GEM_DOMAIN_CPU;
2552 }
2553
2554 /* release the fence reg _after_ flushing */
2555 ret = i915_gem_object_put_fence(obj);
2556 if (ret)
2557 return ret;
2558
2559 if (obj->has_global_gtt_mapping)
2560 i915_gem_gtt_unbind_object(obj);
2561 if (obj->has_aliasing_ppgtt_mapping) {
2562 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2563 obj->has_aliasing_ppgtt_mapping = 0;
2564 }
2565 i915_gem_gtt_finish_object(obj);
2566
2775 /* release the fence reg _after_ flushing */
2776 ret = i915_gem_object_put_fence(obj);
2777 if (ret)
2778 return ret;
2779
2780 if (obj->has_global_gtt_mapping)
2781 i915_gem_gtt_unbind_object(obj);
2782 if (obj->has_aliasing_ppgtt_mapping) {
2783 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2784 obj->has_aliasing_ppgtt_mapping = 0;
2785 }
2786 i915_gem_gtt_finish_object(obj);
2787
2567 i915_gem_object_put_pages_gtt(obj);
2568
2569 list_del_init(&obj->gtt_list);
2570 list_del_init(&obj->mm_list);
2788 list_del(&obj->mm_list);
2789 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2790 /* Avoid an unnecessary call to unbind on rebind. */
2571 obj->map_and_fenceable = true;
2572
2573 drm_mm_put_block(obj->gtt_space);
2574 obj->gtt_space = NULL;
2575 obj->gtt_offset = 0;
2576
2791 obj->map_and_fenceable = true;
2792
2793 drm_mm_put_block(obj->gtt_space);
2794 obj->gtt_space = NULL;
2795 obj->gtt_offset = 0;
2796
2577 if (i915_gem_object_is_purgeable(obj))
2578 i915_gem_object_truncate(obj);
2579 CTR1(KTR_DRM, "object_unbind %p", obj);
2580
2581 return ret;
2797 return 0;
2582}
2583
2798}
2799
2584static int
2585i915_ring_idle(struct intel_ring_buffer *ring)
2586{
2587 int ret;
2588
2589 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2590 return 0;
2591
2592 if (!list_empty(&ring->gpu_write_list)) {
2593 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2594 I915_GEM_GPU_DOMAINS);
2595 if (ret != 0)
2596 return ret;
2597 }
2598
2599 return (i915_wait_request(ring, i915_gem_next_request_seqno(ring)));
2600}
2601
2602int i915_gpu_idle(struct drm_device *dev)
2603{
2604 drm_i915_private_t *dev_priv = dev->dev_private;
2605 struct intel_ring_buffer *ring;
2606 int ret, i;
2607
2608 /* Flush everything onto the inactive list. */
2609 for_each_ring(ring, dev_priv, i) {
2610 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2611 if (ret)
2612 return ret;
2613
2800int i915_gpu_idle(struct drm_device *dev)
2801{
2802 drm_i915_private_t *dev_priv = dev->dev_private;
2803 struct intel_ring_buffer *ring;
2804 int ret, i;
2805
2806 /* Flush everything onto the inactive list. */
2807 for_each_ring(ring, dev_priv, i) {
2808 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2809 if (ret)
2810 return ret;
2811
2614 ret = i915_ring_idle(ring);
2812 ret = intel_ring_idle(ring);
2615 if (ret)
2616 return ret;
2813 if (ret)
2814 return ret;
2617
2618 /* Is the device fubar? */
2619 if (!list_empty(&ring->gpu_write_list))
2620 return -EBUSY;
2621 }
2622
2623 return 0;
2624}
2625
2626static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2627 struct drm_i915_gem_object *obj)
2628{

--- 48 unchanged lines hidden (view full) ---

2677 drm_i915_private_t *dev_priv = dev->dev_private;
2678 u32 val;
2679
2680 if (obj) {
2681 u32 size = obj->gtt_space->size;
2682 int pitch_val;
2683 int tile_width;
2684
2815 }
2816
2817 return 0;
2818}
2819
2820static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2821 struct drm_i915_gem_object *obj)
2822{

--- 48 unchanged lines hidden (view full) ---

2871 drm_i915_private_t *dev_priv = dev->dev_private;
2872 u32 val;
2873
2874 if (obj) {
2875 u32 size = obj->gtt_space->size;
2876 int pitch_val;
2877 int tile_width;
2878
2685 if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2879 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2686 (size & -size) != size ||
2880 (size & -size) != size ||
2687 (obj->gtt_offset & (size - 1)))
2688 printf(
2881 (obj->gtt_offset & (size - 1)),
2689 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2690 obj->gtt_offset, obj->map_and_fenceable, size);
2691
2692 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2693 tile_width = 128;
2694 else
2695 tile_width = 512;
2696

--- 24 unchanged lines hidden (view full) ---

2721{
2722 drm_i915_private_t *dev_priv = dev->dev_private;
2723 uint32_t val;
2724
2725 if (obj) {
2726 u32 size = obj->gtt_space->size;
2727 uint32_t pitch_val;
2728
2882 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2883 obj->gtt_offset, obj->map_and_fenceable, size);
2884
2885 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2886 tile_width = 128;
2887 else
2888 tile_width = 512;
2889

--- 24 unchanged lines hidden (view full) ---

2914{
2915 drm_i915_private_t *dev_priv = dev->dev_private;
2916 uint32_t val;
2917
2918 if (obj) {
2919 u32 size = obj->gtt_space->size;
2920 uint32_t pitch_val;
2921
2729 if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2922 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2730 (size & -size) != size ||
2923 (size & -size) != size ||
2731 (obj->gtt_offset & (size - 1)))
2732 printf(
2924 (obj->gtt_offset & (size - 1)),
2733 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2734 obj->gtt_offset, size);
2735
2736 pitch_val = obj->stride / 128;
2737 pitch_val = ffs(pitch_val) - 1;
2738
2739 val = obj->gtt_offset;
2740 if (obj->tiling_mode == I915_TILING_Y)

--- 23 unchanged lines hidden (view full) ---

2764}
2765
2766static inline int fence_number(struct drm_i915_private *dev_priv,
2767 struct drm_i915_fence_reg *fence)
2768{
2769 return fence - dev_priv->fence_regs;
2770}
2771
2925 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2926 obj->gtt_offset, size);
2927
2928 pitch_val = obj->stride / 128;
2929 pitch_val = ffs(pitch_val) - 1;
2930
2931 val = obj->gtt_offset;
2932 if (obj->tiling_mode == I915_TILING_Y)

--- 23 unchanged lines hidden (view full) ---

2956}
2957
2958static inline int fence_number(struct drm_i915_private *dev_priv,
2959 struct drm_i915_fence_reg *fence)
2960{
2961 return fence - dev_priv->fence_regs;
2962}
2963
2964static void i915_gem_write_fence__ipi(void *data)
2965{
2966 wbinvd();
2967}
2968
2772static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2773 struct drm_i915_fence_reg *fence,
2774 bool enable)
2775{
2776 struct drm_device *dev = obj->base.dev;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 int fence_reg = fence_number(dev_priv, fence);
2779
2969static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2970 struct drm_i915_fence_reg *fence,
2971 bool enable)
2972{
2973 struct drm_device *dev = obj->base.dev;
2974 struct drm_i915_private *dev_priv = dev->dev_private;
2975 int fence_reg = fence_number(dev_priv, fence);
2976
2977 /* In order to fully serialize access to the fenced region and
2978 * the update to the fence register we need to take extreme
2979 * measures on SNB+. In theory, the write to the fence register
2980 * flushes all memory transactions before, and coupled with the
2981 * mb() placed around the register write we serialise all memory
2982 * operations with respect to the changes in the tiler. Yet, on
2983 * SNB+ we need to take a step further and emit an explicit wbinvd()
2984 * on each processor in order to manually flush all memory
2985 * transactions before updating the fence register.
2986 */
2987 if (HAS_LLC(obj->base.dev))
2988 on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
2780 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
2781
2782 if (enable) {
2783 obj->fence_reg = fence_reg;
2784 fence->obj = obj;
2785 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2786 } else {
2787 obj->fence_reg = I915_FENCE_REG_NONE;
2788 fence->obj = NULL;
2789 list_del_init(&fence->lru_list);
2790 }
2791}
2792
2793static int
2794i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2795{
2989 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
2990
2991 if (enable) {
2992 obj->fence_reg = fence_reg;
2993 fence->obj = obj;
2994 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2995 } else {
2996 obj->fence_reg = I915_FENCE_REG_NONE;
2997 fence->obj = NULL;
2998 list_del_init(&fence->lru_list);
2999 }
3000}
3001
3002static int
3003i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
3004{
2796 int ret;
2797
2798 if (obj->fenced_gpu_access) {
2799 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2800 ret = i915_gem_flush_ring(obj->ring,
2801 0, obj->base.write_domain);
2802 if (ret)
2803 return ret;
2804 }
2805
2806 obj->fenced_gpu_access = false;
2807 }
2808
2809 if (obj->last_fenced_seqno) {
3005 if (obj->last_fenced_seqno) {
2810 ret = i915_wait_request(obj->ring,
2811 obj->last_fenced_seqno);
3006 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2812 if (ret)
2813 return ret;
2814
2815 obj->last_fenced_seqno = 0;
2816 }
2817
2818 /* Ensure that all CPU reads are completed before installing a fence
2819 * and all writes before removing the fence.
2820 */
2821 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2822 mb();
2823
3007 if (ret)
3008 return ret;
3009
3010 obj->last_fenced_seqno = 0;
3011 }
3012
3013 /* Ensure that all CPU reads are completed before installing a fence
3014 * and all writes before removing the fence.
3015 */
3016 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3017 mb();
3018
3019 obj->fenced_gpu_access = false;
2824 return 0;
2825}
2826
2827int
2828i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2829{
2830 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2831 int ret;

--- 103 unchanged lines hidden (view full) ---

2935 return 0;
2936
2937 i915_gem_object_update_fence(obj, reg, enable);
2938 obj->fence_dirty = false;
2939
2940 return 0;
2941}
2942
3020 return 0;
3021}
3022
3023int
3024i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3025{
3026 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3027 int ret;

--- 103 unchanged lines hidden (view full) ---

3131 return 0;
3132
3133 i915_gem_object_update_fence(obj, reg, enable);
3134 obj->fence_dirty = false;
3135
3136 return 0;
3137}
3138
3139static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3140 struct drm_mm_node *gtt_space,
3141 unsigned long cache_level)
3142{
3143 struct drm_mm_node *other;
3144
3145 /* On non-LLC machines we have to be careful when putting differing
3146 * types of snoopable memory together to avoid the prefetcher
3147 * crossing memory domains and dieing.
3148 */
3149 if (HAS_LLC(dev))
3150 return true;
3151
3152 if (gtt_space == NULL)
3153 return true;
3154
3155 if (list_empty(&gtt_space->node_list))
3156 return true;
3157
3158 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3159 if (other->allocated && !other->hole_follows && other->color != cache_level)
3160 return false;
3161
3162 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3163 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3164 return false;
3165
3166 return true;
3167}
3168
3169static void i915_gem_verify_gtt(struct drm_device *dev)
3170{
3171#if WATCH_GTT
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct drm_i915_gem_object *obj;
3174 int err = 0;
3175
3176 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
3177 if (obj->gtt_space == NULL) {
3178 DRM_ERROR("object found on GTT list with no space reserved\n");
3179 err++;
3180 continue;
3181 }
3182
3183 if (obj->cache_level != obj->gtt_space->color) {
3184 DRM_ERROR("object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3185 obj->gtt_space->start,
3186 obj->gtt_space->start + obj->gtt_space->size,
3187 obj->cache_level,
3188 obj->gtt_space->color);
3189 err++;
3190 continue;
3191 }
3192
3193 if (!i915_gem_valid_gtt_space(dev,
3194 obj->gtt_space,
3195 obj->cache_level)) {
3196 DRM_ERROR("invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3197 obj->gtt_space->start,
3198 obj->gtt_space->start + obj->gtt_space->size,
3199 obj->cache_level);
3200 err++;
3201 continue;
3202 }
3203 }
3204
3205 WARN_ON(err);
3206#endif
3207}
3208
2943/**
2944 * Finds free space in the GTT aperture and binds the object there.
2945 */
2946static int
2947i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2948 unsigned alignment,
3209/**
3210 * Finds free space in the GTT aperture and binds the object there.
3211 */
3212static int
3213i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3214 unsigned alignment,
2949 bool map_and_fenceable)
3215 bool map_and_fenceable,
3216 bool nonblocking)
2950{
2951 struct drm_device *dev = obj->base.dev;
2952 drm_i915_private_t *dev_priv = dev->dev_private;
3217{
3218 struct drm_device *dev = obj->base.dev;
3219 drm_i915_private_t *dev_priv = dev->dev_private;
2953 struct drm_mm_node *free_space;
3220 struct drm_mm_node *node;
2954 u32 size, fence_size, fence_alignment, unfenced_alignment;
2955 bool mappable, fenceable;
2956 int ret;
2957
2958 if (obj->madv != I915_MADV_WILLNEED) {
2959 DRM_ERROR("Attempting to bind a purgeable object\n");
2960 return -EINVAL;
2961 }

--- 23 unchanged lines hidden (view full) ---

2985 * before evicting everything in a vain attempt to find space.
2986 */
2987 if (obj->base.size >
2988 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2989 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2990 return -E2BIG;
2991 }
2992
3221 u32 size, fence_size, fence_alignment, unfenced_alignment;
3222 bool mappable, fenceable;
3223 int ret;
3224
3225 if (obj->madv != I915_MADV_WILLNEED) {
3226 DRM_ERROR("Attempting to bind a purgeable object\n");
3227 return -EINVAL;
3228 }

--- 23 unchanged lines hidden (view full) ---

3252 * before evicting everything in a vain attempt to find space.
3253 */
3254 if (obj->base.size >
3255 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
3256 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
3257 return -E2BIG;
3258 }
3259
3260 ret = i915_gem_object_get_pages(obj);
3261 if (ret)
3262 return ret;
3263
3264 i915_gem_object_pin_pages(obj);
3265
3266 node = malloc(sizeof(*node), DRM_I915_GEM, M_NOWAIT | M_ZERO);
3267 if (node == NULL) {
3268 i915_gem_object_unpin_pages(obj);
3269 return -ENOMEM;
3270 }
3271
2993 search_free:
2994 if (map_and_fenceable)
3272 search_free:
3273 if (map_and_fenceable)
2995 free_space = drm_mm_search_free_in_range(
2996 &dev_priv->mm.gtt_space, size, alignment, 0,
2997 dev_priv->mm.gtt_mappable_end, 0);
3274 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3275 size, alignment, obj->cache_level,
3276 0, dev_priv->mm.gtt_mappable_end);
2998 else
3277 else
2999 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
3000 size, alignment, 0);
3001 if (free_space != NULL) {
3002 if (map_and_fenceable)
3003 obj->gtt_space = drm_mm_get_block_range_generic(
3004 free_space, size, alignment, 0, 0,
3005 dev_priv->mm.gtt_mappable_end, 1);
3006 else
3007 obj->gtt_space = drm_mm_get_block_generic(free_space,
3008 size, alignment, 0, 1);
3009 }
3010 if (obj->gtt_space == NULL) {
3011 ret = i915_gem_evict_something(dev, size, alignment,
3012 map_and_fenceable);
3013 if (ret != 0)
3014 return ret;
3015 goto search_free;
3016 }
3017 ret = i915_gem_object_get_pages_gtt(obj, 0);
3278 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
3279 size, alignment, obj->cache_level);
3018 if (ret) {
3280 if (ret) {
3019 drm_mm_put_block(obj->gtt_space);
3020 obj->gtt_space = NULL;
3021 /*
3022 * i915_gem_object_get_pages_gtt() cannot return
3023 * ENOMEM, since we use vm_page_grab().
3024 */
3281 ret = i915_gem_evict_something(dev, size, alignment,
3282 obj->cache_level,
3283 map_and_fenceable,
3284 nonblocking);
3285 if (ret == 0)
3286 goto search_free;
3287
3288 i915_gem_object_unpin_pages(obj);
3289 free(node, DRM_I915_GEM);
3025 return ret;
3026 }
3290 return ret;
3291 }
3292 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3293 i915_gem_object_unpin_pages(obj);
3294 drm_mm_put_block(node);
3295 return -EINVAL;
3296 }
3027
3028 ret = i915_gem_gtt_prepare_object(obj);
3029 if (ret) {
3297
3298 ret = i915_gem_gtt_prepare_object(obj);
3299 if (ret) {
3030 i915_gem_object_put_pages_gtt(obj);
3031 drm_mm_put_block(obj->gtt_space);
3032 obj->gtt_space = NULL;
3033 if (i915_gem_evict_everything(dev, false))
3034 return ret;
3035 goto search_free;
3300 i915_gem_object_unpin_pages(obj);
3301 drm_mm_put_block(node);
3302 return ret;
3036 }
3037
3303 }
3304
3038 if (!dev_priv->mm.aliasing_ppgtt)
3039 i915_gem_gtt_bind_object(obj, obj->cache_level);
3040
3041 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
3305 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
3042 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3043
3306 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3307
3044 KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
3045 ("Object in gpu read domain"));
3046 KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
3047 ("Object in gpu write domain"));
3308 obj->gtt_space = node;
3309 obj->gtt_offset = node->start;
3048
3310
3049 obj->gtt_offset = obj->gtt_space->start;
3050
3051 fenceable =
3311 fenceable =
3052 obj->gtt_space->size == fence_size &&
3053 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
3312 node->size == fence_size &&
3313 (node->start & (fence_alignment - 1)) == 0;
3054
3055 mappable =
3056 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3057
3058 obj->map_and_fenceable = mappable && fenceable;
3059
3314
3315 mappable =
3316 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3317
3318 obj->map_and_fenceable = mappable && fenceable;
3319
3320 i915_gem_object_unpin_pages(obj);
3060 CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
3061 obj->base.size, map_and_fenceable);
3321 CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
3322 obj->base.size, map_and_fenceable);
3323 i915_gem_verify_gtt(dev);
3062 return 0;
3063}
3064
3065void
3066i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3067{
3068 /* If we don't have a page list set up, then we're not pinned
3069 * to GPU, and we can ignore the cache flush because it'll happen

--- 49 unchanged lines hidden (view full) ---

3119i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3120{
3121 uint32_t old_write_domain;
3122
3123 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3124 return;
3125
3126 i915_gem_clflush_object(obj);
3324 return 0;
3325}
3326
3327void
3328i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3329{
3330 /* If we don't have a page list set up, then we're not pinned
3331 * to GPU, and we can ignore the cache flush because it'll happen

--- 49 unchanged lines hidden (view full) ---

3381i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3382{
3383 uint32_t old_write_domain;
3384
3385 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3386 return;
3387
3388 i915_gem_clflush_object(obj);
3127 intel_gtt_chipset_flush();
3389 i915_gem_chipset_flush(obj->base.dev);
3128 old_write_domain = obj->base.write_domain;
3129 obj->base.write_domain = 0;
3130
3131 CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
3132 obj->base.read_domains, old_write_domain);
3133}
3134
3390 old_write_domain = obj->base.write_domain;
3391 obj->base.write_domain = 0;
3392
3393 CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
3394 obj->base.read_domains, old_write_domain);
3395}
3396
3135static int
3136i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
3137{
3138
3139 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
3140 return (0);
3141 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
3142}
3143
3144/**
3145 * Moves a single object to the GTT read, and possibly write domain.
3146 *
3147 * This function returns when the move is complete, including waiting on
3148 * flushes to occur.
3149 */
3150int
3151i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)

--- 4 unchanged lines hidden (view full) ---

3156
3157 /* Not valid to be called on unbound objects. */
3158 if (obj->gtt_space == NULL)
3159 return -EINVAL;
3160
3161 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3162 return 0;
3163
3397/**
3398 * Moves a single object to the GTT read, and possibly write domain.
3399 *
3400 * This function returns when the move is complete, including waiting on
3401 * flushes to occur.
3402 */
3403int
3404i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)

--- 4 unchanged lines hidden (view full) ---

3409
3410 /* Not valid to be called on unbound objects. */
3411 if (obj->gtt_space == NULL)
3412 return -EINVAL;
3413
3414 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3415 return 0;
3416
3164 ret = i915_gem_object_flush_gpu_write_domain(obj);
3417 ret = i915_gem_object_wait_rendering(obj, !write);
3165 if (ret)
3166 return ret;
3167
3418 if (ret)
3419 return ret;
3420
3168 if (obj->pending_gpu_write || write) {
3169 ret = i915_gem_object_wait_rendering(obj);
3170 if (ret)
3171 return (ret);
3172 }
3173
3174 i915_gem_object_flush_cpu_write_domain(obj);
3175
3176 old_write_domain = obj->base.write_domain;
3177 old_read_domains = obj->base.read_domains;
3178
3179 /* It should now be out of any other write domains, and we can update
3180 * the domain values for our changes.
3181 */
3421 i915_gem_object_flush_cpu_write_domain(obj);
3422
3423 old_write_domain = obj->base.write_domain;
3424 old_read_domains = obj->base.read_domains;
3425
3426 /* It should now be out of any other write domains, and we can update
3427 * the domain values for our changes.
3428 */
3182 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
3183 ("In GTT write domain"));
3429 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3184 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3185 if (write) {
3186 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3187 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3188 obj->dirty = 1;
3189 }
3190
3191 CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,

--- 16 unchanged lines hidden (view full) ---

3208 if (obj->cache_level == cache_level)
3209 return 0;
3210
3211 if (obj->pin_count) {
3212 DRM_DEBUG("can not change the cache level of pinned objects\n");
3213 return -EBUSY;
3214 }
3215
3430 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3431 if (write) {
3432 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3433 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3434 obj->dirty = 1;
3435 }
3436
3437 CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,

--- 16 unchanged lines hidden (view full) ---

3454 if (obj->cache_level == cache_level)
3455 return 0;
3456
3457 if (obj->pin_count) {
3458 DRM_DEBUG("can not change the cache level of pinned objects\n");
3459 return -EBUSY;
3460 }
3461
3462 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3463 ret = i915_gem_object_unbind(obj);
3464 if (ret)
3465 return ret;
3466 }
3467
3216 if (obj->gtt_space) {
3217 ret = i915_gem_object_finish_gpu(obj);
3218 if (ret)
3219 return ret;
3220
3221 i915_gem_object_finish_gtt(obj);
3222
3223 /* Before SandyBridge, you could not use tiling or fence
3224 * registers with snooped memory, so relinquish any fences
3225 * currently pointing to our region in the aperture.
3226 */
3468 if (obj->gtt_space) {
3469 ret = i915_gem_object_finish_gpu(obj);
3470 if (ret)
3471 return ret;
3472
3473 i915_gem_object_finish_gtt(obj);
3474
3475 /* Before SandyBridge, you could not use tiling or fence
3476 * registers with snooped memory, so relinquish any fences
3477 * currently pointing to our region in the aperture.
3478 */
3227 if (INTEL_INFO(obj->base.dev)->gen < 6) {
3479 if (INTEL_INFO(dev)->gen < 6) {
3228 ret = i915_gem_object_put_fence(obj);
3229 if (ret)
3230 return ret;
3231 }
3232
3233 if (obj->has_global_gtt_mapping)
3234 i915_gem_gtt_bind_object(obj, cache_level);
3235 if (obj->has_aliasing_ppgtt_mapping)
3236 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3237 obj, cache_level);
3480 ret = i915_gem_object_put_fence(obj);
3481 if (ret)
3482 return ret;
3483 }
3484
3485 if (obj->has_global_gtt_mapping)
3486 i915_gem_gtt_bind_object(obj, cache_level);
3487 if (obj->has_aliasing_ppgtt_mapping)
3488 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3489 obj, cache_level);
3490
3491 obj->gtt_space->color = cache_level;
3238 }
3239
3240 if (cache_level == I915_CACHE_NONE) {
3241 u32 old_read_domains, old_write_domain;
3242
3243 /* If we're coming from LLC cached, then we haven't
3244 * actually been tracking whether the data is in the
3245 * CPU cache or not, since we only allow one bit set
3246 * in obj->write_domain and have been skipping the clflushes.
3247 * Just set it to the CPU cache for now.
3248 */
3492 }
3493
3494 if (cache_level == I915_CACHE_NONE) {
3495 u32 old_read_domains, old_write_domain;
3496
3497 /* If we're coming from LLC cached, then we haven't
3498 * actually been tracking whether the data is in the
3499 * CPU cache or not, since we only allow one bit set
3500 * in obj->write_domain and have been skipping the clflushes.
3501 * Just set it to the CPU cache for now.
3502 */
3249 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
3250 ("obj %p in CPU write domain", obj));
3251 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
3252 ("obj %p in CPU read domain", obj));
3503 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3504 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3253
3254 old_read_domains = obj->base.read_domains;
3255 old_write_domain = obj->base.write_domain;
3256
3257 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3258 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3259
3260 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
3261 obj, old_read_domains, old_write_domain);
3262 }
3263
3264 obj->cache_level = cache_level;
3505
3506 old_read_domains = obj->base.read_domains;
3507 old_write_domain = obj->base.write_domain;
3508
3509 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3510 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3511
3512 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
3513 obj, old_read_domains, old_write_domain);
3514 }
3515
3516 obj->cache_level = cache_level;
3517 i915_gem_verify_gtt(dev);
3265 return 0;
3266}
3267
3518 return 0;
3519}
3520
3521int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3522 struct drm_file *file)
3523{
3524 struct drm_i915_gem_caching *args = data;
3525 struct drm_i915_gem_object *obj;
3526 int ret;
3527
3528 ret = i915_mutex_lock_interruptible(dev);
3529 if (ret)
3530 return ret;
3531
3532 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3533 if (&obj->base == NULL) {
3534 ret = -ENOENT;
3535 goto unlock;
3536 }
3537
3538 args->caching = obj->cache_level != I915_CACHE_NONE;
3539
3540 drm_gem_object_unreference(&obj->base);
3541unlock:
3542 DRM_UNLOCK(dev);
3543 return ret;
3544}
3545
3546int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3547 struct drm_file *file)
3548{
3549 struct drm_i915_gem_caching *args = data;
3550 struct drm_i915_gem_object *obj;
3551 enum i915_cache_level level;
3552 int ret;
3553
3554 switch (args->caching) {
3555 case I915_CACHING_NONE:
3556 level = I915_CACHE_NONE;
3557 break;
3558 case I915_CACHING_CACHED:
3559 level = I915_CACHE_LLC;
3560 break;
3561 default:
3562 return -EINVAL;
3563 }
3564
3565 ret = i915_mutex_lock_interruptible(dev);
3566 if (ret)
3567 return ret;
3568
3569 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3570 if (&obj->base == NULL) {
3571 ret = -ENOENT;
3572 goto unlock;
3573 }
3574
3575 ret = i915_gem_object_set_cache_level(obj, level);
3576
3577 drm_gem_object_unreference(&obj->base);
3578unlock:
3579 DRM_UNLOCK(dev);
3580 return ret;
3581}
3582
3268static bool is_pin_display(struct drm_i915_gem_object *obj)
3269{
3270 /* There are 3 sources that pin objects:
3271 * 1. The display engine (scanouts, sprites, cursors);
3272 * 2. Reservations for execbuffer;
3273 * 3. The user.
3274 *
3275 * We can ignore reservations as we hold the struct_mutex and
3276 * are only called outside of the reservation path. The user
3277 * can only increment pin_count once, and so if after
3278 * subtracting the potential reference by the user, any pin_count
3279 * remains, it must be due to another use by the display engine.
3280 */
3281 return obj->pin_count - !!obj->user_pin_count;
3282}
3283
3583static bool is_pin_display(struct drm_i915_gem_object *obj)
3584{
3585 /* There are 3 sources that pin objects:
3586 * 1. The display engine (scanouts, sprites, cursors);
3587 * 2. Reservations for execbuffer;
3588 * 3. The user.
3589 *
3590 * We can ignore reservations as we hold the struct_mutex and
3591 * are only called outside of the reservation path. The user
3592 * can only increment pin_count once, and so if after
3593 * subtracting the potential reference by the user, any pin_count
3594 * remains, it must be due to another use by the display engine.
3595 */
3596 return obj->pin_count - !!obj->user_pin_count;
3597}
3598
3599/*
3600 * Prepare buffer for display plane (scanout, cursors, etc).
3601 * Can be called from an uninterruptible phase (modesetting) and allows
3602 * any flushes to be pipelined (for pageflips).
3603 */
3284int
3285i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3286 u32 alignment,
3287 struct intel_ring_buffer *pipelined)
3288{
3289 u32 old_read_domains, old_write_domain;
3290 int ret;
3291
3604int
3605i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3606 u32 alignment,
3607 struct intel_ring_buffer *pipelined)
3608{
3609 u32 old_read_domains, old_write_domain;
3610 int ret;
3611
3292 ret = i915_gem_object_flush_gpu_write_domain(obj);
3293 if (ret)
3294 return ret;
3295
3296 if (pipelined != obj->ring) {
3297 ret = i915_gem_object_sync(obj, pipelined);
3298 if (ret)
3299 return ret;
3300 }
3301
3302 /* Mark the pin_display early so that we account for the
3303 * display coherency whilst setting up the cache domains.

--- 12 unchanged lines hidden (view full) ---

3316 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3317 if (ret)
3318 goto err_unpin_display;
3319
3320 /* As the user may map the buffer once pinned in the display plane
3321 * (e.g. libkms for the bootup splash), we have to ensure that we
3322 * always use map_and_fenceable for all scanout buffers.
3323 */
3612 if (pipelined != obj->ring) {
3613 ret = i915_gem_object_sync(obj, pipelined);
3614 if (ret)
3615 return ret;
3616 }
3617
3618 /* Mark the pin_display early so that we account for the
3619 * display coherency whilst setting up the cache domains.

--- 12 unchanged lines hidden (view full) ---

3632 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3633 if (ret)
3634 goto err_unpin_display;
3635
3636 /* As the user may map the buffer once pinned in the display plane
3637 * (e.g. libkms for the bootup splash), we have to ensure that we
3638 * always use map_and_fenceable for all scanout buffers.
3639 */
3324 ret = i915_gem_object_pin(obj, alignment, true);
3640 ret = i915_gem_object_pin(obj, alignment, true, false);
3325 if (ret)
3326 goto err_unpin_display;
3327
3328 i915_gem_object_flush_cpu_write_domain(obj);
3329
3330 old_write_domain = obj->base.write_domain;
3331 old_read_domains = obj->base.read_domains;
3332
3641 if (ret)
3642 goto err_unpin_display;
3643
3644 i915_gem_object_flush_cpu_write_domain(obj);
3645
3646 old_write_domain = obj->base.write_domain;
3647 old_read_domains = obj->base.read_domains;
3648
3333 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
3334 ("obj %p in GTT write domain", obj));
3649 /* It should now be out of any other write domains, and we can update
3650 * the domain values for our changes.
3651 */
3652 obj->base.write_domain = 0;
3335 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3336
3337 CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
3653 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3654
3655 CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
3338 obj, old_read_domains, obj->base.write_domain);
3656 obj, old_read_domains, old_write_domain);
3339
3340 return 0;
3341
3342err_unpin_display:
3343 obj->pin_display = is_pin_display(obj);
3344 return ret;
3345}
3346

--- 7 unchanged lines hidden (view full) ---

3354int
3355i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3356{
3357 int ret;
3358
3359 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3360 return 0;
3361
3657
3658 return 0;
3659
3660err_unpin_display:
3661 obj->pin_display = is_pin_display(obj);
3662 return ret;
3663}
3664

--- 7 unchanged lines hidden (view full) ---

3672int
3673i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3674{
3675 int ret;
3676
3677 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3678 return 0;
3679
3362 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3363 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3364 if (ret)
3365 return ret;
3366 }
3367
3368 ret = i915_gem_object_wait_rendering(obj);
3680 ret = i915_gem_object_wait_rendering(obj, false);
3369 if (ret)
3370 return ret;
3371
3372 /* Ensure that we invalidate the GPU's caches and TLBs. */
3373 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3374 return 0;
3375}
3376

--- 7 unchanged lines hidden (view full) ---

3384i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3385{
3386 uint32_t old_write_domain, old_read_domains;
3387 int ret;
3388
3389 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3390 return 0;
3391
3681 if (ret)
3682 return ret;
3683
3684 /* Ensure that we invalidate the GPU's caches and TLBs. */
3685 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3686 return 0;
3687}
3688

--- 7 unchanged lines hidden (view full) ---

3696i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3697{
3698 uint32_t old_write_domain, old_read_domains;
3699 int ret;
3700
3701 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3702 return 0;
3703
3392 ret = i915_gem_object_flush_gpu_write_domain(obj);
3704 ret = i915_gem_object_wait_rendering(obj, !write);
3393 if (ret)
3394 return ret;
3395
3705 if (ret)
3706 return ret;
3707
3396 if (write || obj->pending_gpu_write) {
3397 ret = i915_gem_object_wait_rendering(obj);
3398 if (ret)
3399 return ret;
3400 }
3401
3402 i915_gem_object_flush_gtt_write_domain(obj);
3403
3404 old_write_domain = obj->base.write_domain;
3405 old_read_domains = obj->base.read_domains;
3406
3407 /* Flush the CPU cache if it's still invalid. */
3408 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3409 i915_gem_clflush_object(obj);
3410
3411 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3412 }
3413
3414 /* It should now be out of any other write domains, and we can update
3415 * the domain values for our changes.
3416 */
3708 i915_gem_object_flush_gtt_write_domain(obj);
3709
3710 old_write_domain = obj->base.write_domain;
3711 old_read_domains = obj->base.read_domains;
3712
3713 /* Flush the CPU cache if it's still invalid. */
3714 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3715 i915_gem_clflush_object(obj);
3716
3717 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3718 }
3719
3720 /* It should now be out of any other write domains, and we can update
3721 * the domain values for our changes.
3722 */
3417 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
3418 ("In cpu write domain"));
3723 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3419
3420 /* If we're writing through the CPU, then the GPU read domains will
3421 * need to be invalidated at next use.
3422 */
3423 if (write) {
3424 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3425 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3426 }

--- 14 unchanged lines hidden (view full) ---

3441 * This should get us reasonable parallelism between CPU and GPU but also
3442 * relatively low latency when blocking on a particular request to finish.
3443 */
3444static int
3445i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3446{
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448 struct drm_i915_file_private *file_priv = file->driver_priv;
3724
3725 /* If we're writing through the CPU, then the GPU read domains will
3726 * need to be invalidated at next use.
3727 */
3728 if (write) {
3729 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3730 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3731 }

--- 14 unchanged lines hidden (view full) ---

3746 * This should get us reasonable parallelism between CPU and GPU but also
3747 * relatively low latency when blocking on a particular request to finish.
3748 */
3749static int
3750i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3751{
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 struct drm_i915_file_private *file_priv = file->driver_priv;
3449 unsigned long recent_enough = ticks - (20 * hz / 1000);
3754 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3450 struct drm_i915_gem_request *request;
3451 struct intel_ring_buffer *ring = NULL;
3452 u32 seqno = 0;
3453 int ret;
3454
3755 struct drm_i915_gem_request *request;
3756 struct intel_ring_buffer *ring = NULL;
3757 u32 seqno = 0;
3758 int ret;
3759
3455 if (atomic_load_acq_int(&dev_priv->mm.wedged))
3760 if (atomic_read(&dev_priv->mm.wedged))
3456 return -EIO;
3457
3761 return -EIO;
3762
3458 mtx_lock(&file_priv->mm.lck);
3763 mtx_lock(&file_priv->mm.lock);
3459 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3460 if (time_after_eq(request->emitted_jiffies, recent_enough))
3461 break;
3764 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3765 if (time_after_eq(request->emitted_jiffies, recent_enough))
3766 break;
3767
3462 ring = request->ring;
3463 seqno = request->seqno;
3464 }
3768 ring = request->ring;
3769 seqno = request->seqno;
3770 }
3465 mtx_unlock(&file_priv->mm.lck);
3771 mtx_unlock(&file_priv->mm.lock);
3772
3466 if (seqno == 0)
3467 return 0;
3468
3773 if (seqno == 0)
3774 return 0;
3775
3469 ret = __wait_seqno(ring, seqno, true);
3776 ret = __wait_seqno(ring, seqno, true, NULL);
3470 if (ret == 0)
3777 if (ret == 0)
3471 taskqueue_enqueue_timeout(dev_priv->tq,
3472 &dev_priv->mm.retire_task, 0);
3778 taskqueue_enqueue_timeout(dev_priv->wq,
3779 &dev_priv->mm.retire_work, 0);
3473
3474 return ret;
3475}
3476
3477int
3478i915_gem_object_pin(struct drm_i915_gem_object *obj,
3479 uint32_t alignment,
3780
3781 return ret;
3782}
3783
3784int
3785i915_gem_object_pin(struct drm_i915_gem_object *obj,
3786 uint32_t alignment,
3480 bool map_and_fenceable)
3787 bool map_and_fenceable,
3788 bool nonblocking)
3481{
3482 int ret;
3483
3789{
3790 int ret;
3791
3484 if (obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)
3792 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3485 return -EBUSY;
3486
3487 if (obj->gtt_space != NULL) {
3488 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3489 (map_and_fenceable && !obj->map_and_fenceable)) {
3793 return -EBUSY;
3794
3795 if (obj->gtt_space != NULL) {
3796 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3797 (map_and_fenceable && !obj->map_and_fenceable)) {
3490 DRM_DEBUG("bo is already pinned with incorrect alignment:"
3798 WARN(obj->pin_count,
3799 "bo is already pinned with incorrect alignment:"
3491 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3492 " obj->map_and_fenceable=%d\n",
3493 obj->gtt_offset, alignment,
3494 map_and_fenceable,
3495 obj->map_and_fenceable);
3496 ret = i915_gem_object_unbind(obj);
3497 if (ret)
3498 return ret;
3499 }
3500 }
3501
3502 if (obj->gtt_space == NULL) {
3800 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3801 " obj->map_and_fenceable=%d\n",
3802 obj->gtt_offset, alignment,
3803 map_and_fenceable,
3804 obj->map_and_fenceable);
3805 ret = i915_gem_object_unbind(obj);
3806 if (ret)
3807 return ret;
3808 }
3809 }
3810
3811 if (obj->gtt_space == NULL) {
3812 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3813
3503 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3814 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3504 map_and_fenceable);
3815 map_and_fenceable,
3816 nonblocking);
3505 if (ret)
3506 return ret;
3817 if (ret)
3818 return ret;
3819
3820 if (!dev_priv->mm.aliasing_ppgtt)
3821 i915_gem_gtt_bind_object(obj, obj->cache_level);
3507 }
3508
3509 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3510 i915_gem_gtt_bind_object(obj, obj->cache_level);
3511
3512 obj->pin_count++;
3513 obj->pin_mappable |= map_and_fenceable;
3514
3515 return 0;
3516}
3517
3518void
3519i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3520{
3822 }
3823
3824 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3825 i915_gem_gtt_bind_object(obj, obj->cache_level);
3826
3827 obj->pin_count++;
3828 obj->pin_mappable |= map_and_fenceable;
3829
3830 return 0;
3831}
3832
3833void
3834i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3835{
3836 BUG_ON(obj->pin_count == 0);
3837 BUG_ON(obj->gtt_space == NULL);
3521
3838
3522 KASSERT(obj->pin_count != 0, ("zero pin count"));
3523 KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
3524
3525 if (--obj->pin_count == 0)
3526 obj->pin_mappable = false;
3527}
3528
3529int
3530i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3531 struct drm_file *file)
3532{
3533 struct drm_i915_gem_pin *args = data;
3534 struct drm_i915_gem_object *obj;
3839 if (--obj->pin_count == 0)
3840 obj->pin_mappable = false;
3841}
3842
3843int
3844i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3845 struct drm_file *file)
3846{
3847 struct drm_i915_gem_pin *args = data;
3848 struct drm_i915_gem_object *obj;
3535 struct drm_gem_object *gobj;
3536 int ret;
3537
3538 ret = i915_mutex_lock_interruptible(dev);
3539 if (ret)
3540 return ret;
3541
3849 int ret;
3850
3851 ret = i915_mutex_lock_interruptible(dev);
3852 if (ret)
3853 return ret;
3854
3542 gobj = drm_gem_object_lookup(dev, file, args->handle);
3543 if (gobj == NULL) {
3855 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3856 if (&obj->base == NULL) {
3544 ret = -ENOENT;
3545 goto unlock;
3546 }
3857 ret = -ENOENT;
3858 goto unlock;
3859 }
3547 obj = to_intel_bo(gobj);
3548
3549 if (obj->madv != I915_MADV_WILLNEED) {
3550 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3551 ret = -EINVAL;
3552 goto out;
3553 }
3554
3555 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3556 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3557 args->handle);
3558 ret = -EINVAL;
3559 goto out;
3560 }
3561
3860
3861 if (obj->madv != I915_MADV_WILLNEED) {
3862 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3863 ret = -EINVAL;
3864 goto out;
3865 }
3866
3867 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3868 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3869 args->handle);
3870 ret = -EINVAL;
3871 goto out;
3872 }
3873
3562 obj->user_pin_count++;
3563 obj->pin_filp = file;
3564 if (obj->user_pin_count == 1) {
3565 ret = i915_gem_object_pin(obj, args->alignment, true);
3874 if (obj->user_pin_count == 0) {
3875 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3566 if (ret)
3567 goto out;
3568 }
3569
3876 if (ret)
3877 goto out;
3878 }
3879
3880 obj->user_pin_count++;
3881 obj->pin_filp = file;
3882
3570 /* XXX - flush the CPU caches for pinned objects
3571 * as the X server doesn't manage domains yet
3572 */
3573 i915_gem_object_flush_cpu_write_domain(obj);
3574 args->offset = obj->gtt_offset;
3575out:
3576 drm_gem_object_unreference(&obj->base);
3577unlock:

--- 51 unchanged lines hidden (view full) ---

3629 return ret;
3630
3631 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3632 if (&obj->base == NULL) {
3633 ret = -ENOENT;
3634 goto unlock;
3635 }
3636
3883 /* XXX - flush the CPU caches for pinned objects
3884 * as the X server doesn't manage domains yet
3885 */
3886 i915_gem_object_flush_cpu_write_domain(obj);
3887 args->offset = obj->gtt_offset;
3888out:
3889 drm_gem_object_unreference(&obj->base);
3890unlock:

--- 51 unchanged lines hidden (view full) ---

3942 return ret;
3943
3944 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3945 if (&obj->base == NULL) {
3946 ret = -ENOENT;
3947 goto unlock;
3948 }
3949
3637 args->busy = obj->active;
3638 if (args->busy) {
3639 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3640 ret = i915_gem_flush_ring(obj->ring,
3641 0, obj->base.write_domain);
3642 } else {
3643 ret = i915_gem_check_olr(obj->ring,
3644 obj->last_rendering_seqno);
3645 }
3950 /* Count all active objects as busy, even if they are currently not used
3951 * by the gpu. Users of this interface expect objects to eventually
3952 * become non-busy without any further actions, therefore emit any
3953 * necessary flushes here.
3954 */
3955 ret = i915_gem_object_flush_active(obj);
3646
3956
3647 i915_gem_retire_requests_ring(obj->ring);
3648 args->busy = obj->active;
3957 args->busy = obj->active;
3958 if (obj->ring) {
3959 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3960 args->busy |= intel_ring_flag(obj->ring) << 16;
3649 }
3650
3651 drm_gem_object_unreference(&obj->base);
3652unlock:
3653 DRM_UNLOCK(dev);
3654 return ret;
3655}
3656

--- 30 unchanged lines hidden (view full) ---

3687 goto unlock;
3688 }
3689
3690 if (obj->pin_count) {
3691 ret = -EINVAL;
3692 goto out;
3693 }
3694
3961 }
3962
3963 drm_gem_object_unreference(&obj->base);
3964unlock:
3965 DRM_UNLOCK(dev);
3966 return ret;
3967}
3968

--- 30 unchanged lines hidden (view full) ---

3999 goto unlock;
4000 }
4001
4002 if (obj->pin_count) {
4003 ret = -EINVAL;
4004 goto out;
4005 }
4006
3695 if (obj->madv != I915_MADV_PURGED_INTERNAL)
4007 if (obj->madv != __I915_MADV_PURGED)
3696 obj->madv = args->madv;
3697
3698 /* if the object is no longer attached, discard its backing storage */
4008 obj->madv = args->madv;
4009
4010 /* if the object is no longer attached, discard its backing storage */
3699 if (i915_gem_object_is_purgeable(obj) && obj->gtt_space == NULL)
4011 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3700 i915_gem_object_truncate(obj);
3701
4012 i915_gem_object_truncate(obj);
4013
3702 args->retained = obj->madv != I915_MADV_PURGED_INTERNAL;
4014 args->retained = obj->madv != __I915_MADV_PURGED;
3703
3704out:
3705 drm_gem_object_unreference(&obj->base);
3706unlock:
3707 DRM_UNLOCK(dev);
3708 return ret;
3709}
3710
4015
4016out:
4017 drm_gem_object_unreference(&obj->base);
4018unlock:
4019 DRM_UNLOCK(dev);
4020 return ret;
4021}
4022
4023void i915_gem_object_init(struct drm_i915_gem_object *obj,
4024 const struct drm_i915_gem_object_ops *ops)
4025{
4026 INIT_LIST_HEAD(&obj->mm_list);
4027 INIT_LIST_HEAD(&obj->gtt_list);
4028 INIT_LIST_HEAD(&obj->ring_list);
4029 INIT_LIST_HEAD(&obj->exec_list);
4030
4031 obj->ops = ops;
4032
4033 obj->fence_reg = I915_FENCE_REG_NONE;
4034 obj->madv = I915_MADV_WILLNEED;
4035 /* Avoid an unnecessary call to unbind on the first bind. */
4036 obj->map_and_fenceable = true;
4037
4038 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4039}
4040
4041static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4042 .get_pages = i915_gem_object_get_pages_gtt,
4043 .put_pages = i915_gem_object_put_pages_gtt,
4044};
4045
3711struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3712 size_t size)
3713{
4046struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4047 size_t size)
4048{
3714 struct drm_i915_private *dev_priv;
3715 struct drm_i915_gem_object *obj;
3716
4049 struct drm_i915_gem_object *obj;
4050
3717 dev_priv = dev->dev_private;
3718
3719 obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
4051 obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
4052 if (obj == NULL)
4053 return NULL;
3720
3721 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3722 free(obj, DRM_I915_GEM);
3723 return NULL;
3724 }
3725
4054
4055 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4056 free(obj, DRM_I915_GEM);
4057 return NULL;
4058 }
4059
4060#ifdef FREEBSD_WIP
4061 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4062 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4063 /* 965gm cannot relocate objects above 4GiB. */
4064 mask &= ~__GFP_HIGHMEM;
4065 mask |= __GFP_DMA32;
4066 }
4067
4068 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4069 mapping_set_gfp_mask(mapping, mask);
4070#endif /* FREEBSD_WIP */
4071
4072 i915_gem_object_init(obj, &i915_gem_object_ops);
4073
3726 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3727 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3728
3729 if (HAS_LLC(dev)) {
3730 /* On some devices, we can have the GPU use the LLC (the CPU
3731 * cache) for about a 10% performance improvement
3732 * compared to uncached. Graphics requests other than
3733 * display scanout are coherent with the CPU in
3734 * accessing this cache. This means in this mode we
3735 * don't need to clflush on the CPU side, and on the
3736 * GPU side we only need to flush internal caches to
3737 * get data visible to the CPU.
3738 *
3739 * However, we maintain the display planes as UC, and so
3740 * need to rebind when first used as such.
3741 */
3742 obj->cache_level = I915_CACHE_LLC;
3743 } else
3744 obj->cache_level = I915_CACHE_NONE;
4074 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4075 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4076
4077 if (HAS_LLC(dev)) {
4078 /* On some devices, we can have the GPU use the LLC (the CPU
4079 * cache) for about a 10% performance improvement
4080 * compared to uncached. Graphics requests other than
4081 * display scanout are coherent with the CPU in
4082 * accessing this cache. This means in this mode we
4083 * don't need to clflush on the CPU side, and on the
4084 * GPU side we only need to flush internal caches to
4085 * get data visible to the CPU.
4086 *
4087 * However, we maintain the display planes as UC, and so
4088 * need to rebind when first used as such.
4089 */
4090 obj->cache_level = I915_CACHE_LLC;
4091 } else
4092 obj->cache_level = I915_CACHE_NONE;
3745 obj->base.driver_private = NULL;
3746 obj->fence_reg = I915_FENCE_REG_NONE;
3747 INIT_LIST_HEAD(&obj->mm_list);
3748 INIT_LIST_HEAD(&obj->gtt_list);
3749 INIT_LIST_HEAD(&obj->ring_list);
3750 INIT_LIST_HEAD(&obj->exec_list);
3751 INIT_LIST_HEAD(&obj->gpu_write_list);
3752 obj->madv = I915_MADV_WILLNEED;
3753 /* Avoid an unnecessary call to unbind on the first bind. */
3754 obj->map_and_fenceable = true;
3755
4093
3756 i915_gem_info_add_obj(dev_priv, size);
3757
3758 return obj;
3759}
3760
3761int i915_gem_init_object(struct drm_gem_object *obj)
3762{
3763 printf("i915_gem_init_object called\n");
3764
3765 return 0;

--- 6 unchanged lines hidden (view full) ---

3772 drm_i915_private_t *dev_priv = dev->dev_private;
3773
3774 CTR1(KTR_DRM, "object_destroy_tail %p", obj);
3775
3776 if (obj->phys_obj)
3777 i915_gem_detach_phys_object(dev, obj);
3778
3779 obj->pin_count = 0;
4094 return obj;
4095}
4096
4097int i915_gem_init_object(struct drm_gem_object *obj)
4098{
4099 printf("i915_gem_init_object called\n");
4100
4101 return 0;

--- 6 unchanged lines hidden (view full) ---

4108 drm_i915_private_t *dev_priv = dev->dev_private;
4109
4110 CTR1(KTR_DRM, "object_destroy_tail %p", obj);
4111
4112 if (obj->phys_obj)
4113 i915_gem_detach_phys_object(dev, obj);
4114
4115 obj->pin_count = 0;
3780 if (i915_gem_object_unbind(obj) == -ERESTARTSYS) {
4116 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3781 bool was_interruptible;
3782
3783 was_interruptible = dev_priv->mm.interruptible;
3784 dev_priv->mm.interruptible = false;
3785
4117 bool was_interruptible;
4118
4119 was_interruptible = dev_priv->mm.interruptible;
4120 dev_priv->mm.interruptible = false;
4121
3786 if (i915_gem_object_unbind(obj))
3787 printf("i915_gem_free_object: unbind\n");
4122 WARN_ON(i915_gem_object_unbind(obj));
3788
3789 dev_priv->mm.interruptible = was_interruptible;
3790 }
3791
4123
4124 dev_priv->mm.interruptible = was_interruptible;
4125 }
4126
3792 drm_gem_free_mmap_offset(&obj->base);
4127 obj->pages_pin_count = 0;
4128 i915_gem_object_put_pages(obj);
4129 i915_gem_object_free_mmap_offset(obj);
4130
4131 BUG_ON(obj->pages);
4132
4133#ifdef FREEBSD_WIP
4134 if (obj->base.import_attach)
4135 drm_prime_gem_destroy(&obj->base, NULL);
4136#endif /* FREEBSD_WIP */
4137
3793 drm_gem_object_release(&obj->base);
3794 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3795
3796 free(obj->bit_17, DRM_I915_GEM);
3797 free(obj, DRM_I915_GEM);
3798}
3799
3800int

--- 12 unchanged lines hidden (view full) ---

3813 ret = i915_gpu_idle(dev);
3814 if (ret) {
3815 DRM_UNLOCK(dev);
3816 return ret;
3817 }
3818 i915_gem_retire_requests(dev);
3819
3820 /* Under UMS, be paranoid and evict. */
4138 drm_gem_object_release(&obj->base);
4139 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4140
4141 free(obj->bit_17, DRM_I915_GEM);
4142 free(obj, DRM_I915_GEM);
4143}
4144
4145int

--- 12 unchanged lines hidden (view full) ---

4158 ret = i915_gpu_idle(dev);
4159 if (ret) {
4160 DRM_UNLOCK(dev);
4161 return ret;
4162 }
4163 i915_gem_retire_requests(dev);
4164
4165 /* Under UMS, be paranoid and evict. */
3821 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3822 ret = i915_gem_evict_everything(dev, false);
3823 if (ret) {
3824 DRM_UNLOCK(dev);
3825 return ret;
3826 }
3827 }
4166 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4167 i915_gem_evict_everything(dev);
3828
3829 i915_gem_reset_fences(dev);
3830
3831 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3832 * We need to replace this with a semaphore, or something.
3833 * And not confound mm.suspended!
3834 */
3835 dev_priv->mm.suspended = 1;
3836 callout_stop(&dev_priv->hangcheck_timer);
3837
3838 i915_kernel_lost_context(dev);
3839 i915_gem_cleanup_ringbuffer(dev);
3840
3841 DRM_UNLOCK(dev);
3842
3843 /* Cancel the retire work handler, which should be idle now. */
4168
4169 i915_gem_reset_fences(dev);
4170
4171 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4172 * We need to replace this with a semaphore, or something.
4173 * And not confound mm.suspended!
4174 */
4175 dev_priv->mm.suspended = 1;
4176 callout_stop(&dev_priv->hangcheck_timer);
4177
4178 i915_kernel_lost_context(dev);
4179 i915_gem_cleanup_ringbuffer(dev);
4180
4181 DRM_UNLOCK(dev);
4182
4183 /* Cancel the retire work handler, which should be idle now. */
3844 taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
4184 taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->mm.retire_work, NULL);
3845
4185
3846 return ret;
4186 return 0;
3847}
3848
4187}
4188
4189void i915_gem_l3_remap(struct drm_device *dev)
4190{
4191 drm_i915_private_t *dev_priv = dev->dev_private;
4192 u32 misccpctl;
4193 int i;
4194
4195 if (!HAS_L3_GPU_CACHE(dev))
4196 return;
4197
4198 if (!dev_priv->l3_parity.remap_info)
4199 return;
4200
4201 misccpctl = I915_READ(GEN7_MISCCPCTL);
4202 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4203 POSTING_READ(GEN7_MISCCPCTL);
4204
4205 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4206 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4207 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4208 DRM_DEBUG("0x%x was already programmed to %x\n",
4209 GEN7_L3LOG_BASE + i, remap);
4210 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4211 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4212 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4213 }
4214
4215 /* Make sure all the writes land before disabling dop clock gating */
4216 POSTING_READ(GEN7_L3LOG_BASE);
4217
4218 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4219}
4220
3849void i915_gem_init_swizzling(struct drm_device *dev)
3850{
3851 drm_i915_private_t *dev_priv = dev->dev_private;
3852
3853 if (INTEL_INFO(dev)->gen < 5 ||
3854 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3855 return;
3856

--- 5 unchanged lines hidden (view full) ---

3862
3863 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3864 if (IS_GEN6(dev))
3865 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3866 else
3867 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3868}
3869
4221void i915_gem_init_swizzling(struct drm_device *dev)
4222{
4223 drm_i915_private_t *dev_priv = dev->dev_private;
4224
4225 if (INTEL_INFO(dev)->gen < 5 ||
4226 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4227 return;
4228

--- 5 unchanged lines hidden (view full) ---

4234
4235 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4236 if (IS_GEN6(dev))
4237 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4238 else
4239 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4240}
4241
4242static bool
4243intel_enable_blt(struct drm_device *dev)
4244{
4245 if (!HAS_BLT(dev))
4246 return false;
4247
4248 /* The blitter was dysfunctional on early prototypes */
4249 if (IS_GEN6(dev) && pci_get_revid(dev->dev) < 8) {
4250 DRM_INFO("BLT not supported on this pre-production hardware;"
4251 " graphics performance will be degraded.\n");
4252 return false;
4253 }
4254
4255 return true;
4256}
4257
3870int
3871i915_gem_init_hw(struct drm_device *dev)
3872{
3873 drm_i915_private_t *dev_priv = dev->dev_private;
3874 int ret;
3875
4258int
4259i915_gem_init_hw(struct drm_device *dev)
4260{
4261 drm_i915_private_t *dev_priv = dev->dev_private;
4262 int ret;
4263
4264#ifdef FREEBSD_WIP
4265 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4266 return -EIO;
4267#endif /* FREEBSD_WIP */
4268
4269 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4270 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4271
4272 i915_gem_l3_remap(dev);
4273
3876 i915_gem_init_swizzling(dev);
3877
3878 ret = intel_init_render_ring_buffer(dev);
3879 if (ret)
3880 return ret;
3881
3882 if (HAS_BSD(dev)) {
3883 ret = intel_init_bsd_ring_buffer(dev);
3884 if (ret)
3885 goto cleanup_render_ring;
3886 }
3887
4274 i915_gem_init_swizzling(dev);
4275
4276 ret = intel_init_render_ring_buffer(dev);
4277 if (ret)
4278 return ret;
4279
4280 if (HAS_BSD(dev)) {
4281 ret = intel_init_bsd_ring_buffer(dev);
4282 if (ret)
4283 goto cleanup_render_ring;
4284 }
4285
3888 if (HAS_BLT(dev)) {
4286 if (intel_enable_blt(dev)) {
3889 ret = intel_init_blt_ring_buffer(dev);
3890 if (ret)
3891 goto cleanup_bsd_ring;
3892 }
3893
3894 dev_priv->next_seqno = 1;
3895
3896 /*
3897 * XXX: There was some w/a described somewhere suggesting loading
3898 * contexts before PPGTT.
3899 */
3900 i915_gem_context_init(dev);
3901 i915_gem_init_ppgtt(dev);
3902
3903 return 0;
3904
3905cleanup_bsd_ring:
4287 ret = intel_init_blt_ring_buffer(dev);
4288 if (ret)
4289 goto cleanup_bsd_ring;
4290 }
4291
4292 dev_priv->next_seqno = 1;
4293
4294 /*
4295 * XXX: There was some w/a described somewhere suggesting loading
4296 * contexts before PPGTT.
4297 */
4298 i915_gem_context_init(dev);
4299 i915_gem_init_ppgtt(dev);
4300
4301 return 0;
4302
4303cleanup_bsd_ring:
3906 intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
4304 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3907cleanup_render_ring:
4305cleanup_render_ring:
3908 intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
4306 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3909 return ret;
3910}
3911
3912static bool
3913intel_enable_ppgtt(struct drm_device *dev)
3914{
3915 if (i915_enable_ppgtt >= 0)
3916 return i915_enable_ppgtt;
3917
4307 return ret;
4308}
4309
4310static bool
4311intel_enable_ppgtt(struct drm_device *dev)
4312{
4313 if (i915_enable_ppgtt >= 0)
4314 return i915_enable_ppgtt;
4315
4316#ifdef CONFIG_INTEL_IOMMU
3918 /* Disable ppgtt on SNB if VT-d is on. */
4317 /* Disable ppgtt on SNB if VT-d is on. */
3919 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
4318 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3920 return false;
4319 return false;
4320#endif
3921
3922 return true;
3923}
3924
3925int i915_gem_init(struct drm_device *dev)
3926{
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 unsigned long gtt_size, mappable_size;
3929 int ret;
3930
4321
4322 return true;
4323}
4324
4325int i915_gem_init(struct drm_device *dev)
4326{
4327 struct drm_i915_private *dev_priv = dev->dev_private;
4328 unsigned long gtt_size, mappable_size;
4329 int ret;
4330
3931 gtt_size = dev_priv->mm.gtt.gtt_total_entries << PAGE_SHIFT;
3932 mappable_size = dev_priv->mm.gtt.gtt_mappable_entries << PAGE_SHIFT;
4331 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
4332 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3933
3934 DRM_LOCK(dev);
3935 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3936 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3937 * aperture accordingly when using aliasing ppgtt. */
3938 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3939
3940 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);

--- 47 unchanged lines hidden (view full) ---

3988 struct drm_file *file_priv)
3989{
3990 drm_i915_private_t *dev_priv = dev->dev_private;
3991 int ret;
3992
3993 if (drm_core_check_feature(dev, DRIVER_MODESET))
3994 return 0;
3995
4333
4334 DRM_LOCK(dev);
4335 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
4336 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4337 * aperture accordingly when using aliasing ppgtt. */
4338 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4339
4340 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);

--- 47 unchanged lines hidden (view full) ---

4388 struct drm_file *file_priv)
4389{
4390 drm_i915_private_t *dev_priv = dev->dev_private;
4391 int ret;
4392
4393 if (drm_core_check_feature(dev, DRIVER_MODESET))
4394 return 0;
4395
3996 if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
4396 if (atomic_read(&dev_priv->mm.wedged)) {
3997 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4397 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3998 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
4398 atomic_set(&dev_priv->mm.wedged, 0);
3999 }
4000
4001 DRM_LOCK(dev);
4002 dev_priv->mm.suspended = 0;
4003
4004 ret = i915_gem_init_hw(dev);
4005 if (ret != 0) {
4006 DRM_UNLOCK(dev);
4007 return ret;
4008 }
4009
4399 }
4400
4401 DRM_LOCK(dev);
4402 dev_priv->mm.suspended = 0;
4403
4404 ret = i915_gem_init_hw(dev);
4405 if (ret != 0) {
4406 DRM_UNLOCK(dev);
4407 return ret;
4408 }
4409
4010 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
4011 KASSERT(list_empty(&dev_priv->mm.flushing_list), ("flushing list"));
4012 KASSERT(list_empty(&dev_priv->mm.inactive_list), ("inactive list"));
4410 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4013 DRM_UNLOCK(dev);
4014
4015 ret = drm_irq_install(dev);
4016 if (ret)
4017 goto cleanup_ringbuffer;
4018
4019 return 0;
4020

--- 30 unchanged lines hidden (view full) ---

4051 DRM_ERROR("failed to idle hardware: %d\n", ret);
4052}
4053
4054static void
4055init_ring_lists(struct intel_ring_buffer *ring)
4056{
4057 INIT_LIST_HEAD(&ring->active_list);
4058 INIT_LIST_HEAD(&ring->request_list);
4411 DRM_UNLOCK(dev);
4412
4413 ret = drm_irq_install(dev);
4414 if (ret)
4415 goto cleanup_ringbuffer;
4416
4417 return 0;
4418

--- 30 unchanged lines hidden (view full) ---

4449 DRM_ERROR("failed to idle hardware: %d\n", ret);
4450}
4451
4452static void
4453init_ring_lists(struct intel_ring_buffer *ring)
4454{
4455 INIT_LIST_HEAD(&ring->active_list);
4456 INIT_LIST_HEAD(&ring->request_list);
4059 INIT_LIST_HEAD(&ring->gpu_write_list);
4060}
4061
4062void
4063i915_gem_load(struct drm_device *dev)
4064{
4065 int i;
4066 drm_i915_private_t *dev_priv = dev->dev_private;
4067
4068 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4457}
4458
4459void
4460i915_gem_load(struct drm_device *dev)
4461{
4462 int i;
4463 drm_i915_private_t *dev_priv = dev->dev_private;
4464
4465 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4069 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4070 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4466 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4467 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4468 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4071 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4469 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4072 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
4073 for (i = 0; i < I915_NUM_RINGS; i++)
4470 for (i = 0; i < I915_NUM_RINGS; i++)
4074 init_ring_lists(&dev_priv->rings[i]);
4471 init_ring_lists(&dev_priv->ring[i]);
4075 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4076 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4472 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4473 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4077 TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
4078 i915_gem_retire_task_handler, dev_priv);
4079 dev_priv->error_completion = 0;
4474 TIMEOUT_TASK_INIT(dev_priv->wq, &dev_priv->mm.retire_work, 0,
4475 i915_gem_retire_work_handler, dev_priv);
4476 init_completion(&dev_priv->error_completion);
4080
4081 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4082 if (IS_GEN3(dev)) {
4083 I915_WRITE(MI_ARB_STATE,
4084 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4085 }
4086
4087 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;

--- 6 unchanged lines hidden (view full) ---

4094 dev_priv->num_fence_regs = 16;
4095 else
4096 dev_priv->num_fence_regs = 8;
4097
4098 /* Initialize fence registers to zero */
4099 i915_gem_reset_fences(dev);
4100
4101 i915_gem_detect_bit_6_swizzle(dev);
4477
4478 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4479 if (IS_GEN3(dev)) {
4480 I915_WRITE(MI_ARB_STATE,
4481 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4482 }
4483
4484 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;

--- 6 unchanged lines hidden (view full) ---

4491 dev_priv->num_fence_regs = 16;
4492 else
4493 dev_priv->num_fence_regs = 8;
4494
4495 /* Initialize fence registers to zero */
4496 i915_gem_reset_fences(dev);
4497
4498 i915_gem_detect_bit_6_swizzle(dev);
4499 DRM_INIT_WAITQUEUE(&dev_priv->pending_flip_queue);
4500
4102 dev_priv->mm.interruptible = true;
4103
4501 dev_priv->mm.interruptible = true;
4502
4104 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
4105 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
4503 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4504 i915_gem_inactive_shrink, dev, EVENTHANDLER_PRI_ANY);
4106}
4107
4505}
4506
4108void
4109i915_gem_unload(struct drm_device *dev)
4110{
4111 struct drm_i915_private *dev_priv;
4112
4113 dev_priv = dev->dev_private;
4114 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
4115}
4116
4117/*
4118 * Create a physically contiguous memory object for this object
4119 * e.g. for cursor + overlay regs
4120 */
4121static int i915_gem_init_phys_object(struct drm_device *dev,
4122 int id, int size, int align)
4123{
4124 drm_i915_private_t *dev_priv = dev->dev_private;
4125 struct drm_i915_gem_phys_object *phys_obj;
4126 int ret;
4127
4128 if (dev_priv->mm.phys_objs[id - 1] || !size)
4129 return 0;
4130
4131 phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object),
4132 DRM_I915_GEM, M_WAITOK | M_ZERO);
4507/*
4508 * Create a physically contiguous memory object for this object
4509 * e.g. for cursor + overlay regs
4510 */
4511static int i915_gem_init_phys_object(struct drm_device *dev,
4512 int id, int size, int align)
4513{
4514 drm_i915_private_t *dev_priv = dev->dev_private;
4515 struct drm_i915_gem_phys_object *phys_obj;
4516 int ret;
4517
4518 if (dev_priv->mm.phys_objs[id - 1] || !size)
4519 return 0;
4520
4521 phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object),
4522 DRM_I915_GEM, M_WAITOK | M_ZERO);
4523 if (!phys_obj)
4524 return -ENOMEM;
4133
4134 phys_obj->id = id;
4135
4136 phys_obj->handle = drm_pci_alloc(dev, size, align, BUS_SPACE_MAXADDR);
4137 if (!phys_obj->handle) {
4138 ret = -ENOMEM;
4139 goto kfree_obj;
4140 }
4525
4526 phys_obj->id = id;
4527
4528 phys_obj->handle = drm_pci_alloc(dev, size, align, BUS_SPACE_MAXADDR);
4529 if (!phys_obj->handle) {
4530 ret = -ENOMEM;
4531 goto kfree_obj;
4532 }
4533#ifdef CONFIG_X86
4141 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4142 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4534 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4535 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4536#endif
4143
4144 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4145
4146 return 0;
4147kfree_obj:
4148 free(phys_obj, DRM_I915_GEM);
4149 return ret;
4150}

--- 6 unchanged lines hidden (view full) ---

4157 if (!dev_priv->mm.phys_objs[id - 1])
4158 return;
4159
4160 phys_obj = dev_priv->mm.phys_objs[id - 1];
4161 if (phys_obj->cur_obj) {
4162 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4163 }
4164
4537
4538 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4539
4540 return 0;
4541kfree_obj:
4542 free(phys_obj, DRM_I915_GEM);
4543 return ret;
4544}

--- 6 unchanged lines hidden (view full) ---

4551 if (!dev_priv->mm.phys_objs[id - 1])
4552 return;
4553
4554 phys_obj = dev_priv->mm.phys_objs[id - 1];
4555 if (phys_obj->cur_obj) {
4556 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4557 }
4558
4559#ifdef FREEBSD_WIP
4560#ifdef CONFIG_X86
4561 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4562#endif
4563#endif /* FREEBSD_WIP */
4564
4165 drm_pci_free(dev, phys_obj->handle);
4166 free(phys_obj, DRM_I915_GEM);
4167 dev_priv->mm.phys_objs[id - 1] = NULL;
4168}
4169
4170void i915_gem_free_all_phys_object(struct drm_device *dev)
4171{
4172 int i;
4173
4174 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4175 i915_gem_free_phys_object(dev, i);
4176}
4177
4178void i915_gem_detach_phys_object(struct drm_device *dev,
4179 struct drm_i915_gem_object *obj)
4180{
4565 drm_pci_free(dev, phys_obj->handle);
4566 free(phys_obj, DRM_I915_GEM);
4567 dev_priv->mm.phys_objs[id - 1] = NULL;
4568}
4569
4570void i915_gem_free_all_phys_object(struct drm_device *dev)
4571{
4572 int i;
4573
4574 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4575 i915_gem_free_phys_object(dev, i);
4576}
4577
4578void i915_gem_detach_phys_object(struct drm_device *dev,
4579 struct drm_i915_gem_object *obj)
4580{
4181 vm_page_t page;
4182 struct sf_buf *sf;
4581 struct sf_buf *sf;
4183 char *vaddr, *dst;
4184 int i, page_count;
4582 char *vaddr;
4583 char *dst;
4584 int i;
4585 int page_count;
4185
4186 if (!obj->phys_obj)
4187 return;
4188 vaddr = obj->phys_obj->handle->vaddr;
4189
4190 page_count = obj->base.size / PAGE_SIZE;
4191 VM_OBJECT_WLOCK(obj->base.vm_obj);
4192 for (i = 0; i < page_count; i++) {
4586
4587 if (!obj->phys_obj)
4588 return;
4589 vaddr = obj->phys_obj->handle->vaddr;
4590
4591 page_count = obj->base.size / PAGE_SIZE;
4592 VM_OBJECT_WLOCK(obj->base.vm_obj);
4593 for (i = 0; i < page_count; i++) {
4193 page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4594 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4194 if (page == NULL)
4195 continue; /* XXX */
4196
4197 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4198 sf = sf_buf_alloc(page, 0);
4199 if (sf != NULL) {
4200 dst = (char *)sf_buf_kva(sf);
4201 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);

--- 5 unchanged lines hidden (view full) ---

4207 vm_page_reference(page);
4208 vm_page_lock(page);
4209 vm_page_dirty(page);
4210 vm_page_unwire(page, PQ_INACTIVE);
4211 vm_page_unlock(page);
4212 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4213 }
4214 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4595 if (page == NULL)
4596 continue; /* XXX */
4597
4598 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4599 sf = sf_buf_alloc(page, 0);
4600 if (sf != NULL) {
4601 dst = (char *)sf_buf_kva(sf);
4602 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);

--- 5 unchanged lines hidden (view full) ---

4608 vm_page_reference(page);
4609 vm_page_lock(page);
4610 vm_page_dirty(page);
4611 vm_page_unwire(page, PQ_INACTIVE);
4612 vm_page_unlock(page);
4613 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4614 }
4615 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4215 intel_gtt_chipset_flush();
4616 i915_gem_chipset_flush(dev);
4216
4217 obj->phys_obj->cur_obj = NULL;
4218 obj->phys_obj = NULL;
4219}
4220
4221int
4222i915_gem_attach_phys_object(struct drm_device *dev,
4223 struct drm_i915_gem_object *obj,
4224 int id,
4225 int align)
4226{
4227 drm_i915_private_t *dev_priv = dev->dev_private;
4617
4618 obj->phys_obj->cur_obj = NULL;
4619 obj->phys_obj = NULL;
4620}
4621
4622int
4623i915_gem_attach_phys_object(struct drm_device *dev,
4624 struct drm_i915_gem_object *obj,
4625 int id,
4626 int align)
4627{
4628 drm_i915_private_t *dev_priv = dev->dev_private;
4228 vm_page_t page;
4229 struct sf_buf *sf;
4230 char *dst, *src;
4231 int ret = 0;
4232 int page_count;
4233 int i;
4234
4235 if (id > I915_MAX_PHYS_OBJECT)
4236 return -EINVAL;

--- 18 unchanged lines hidden (view full) ---

4255 /* bind to the object */
4256 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4257 obj->phys_obj->cur_obj = obj;
4258
4259 page_count = obj->base.size / PAGE_SIZE;
4260
4261 VM_OBJECT_WLOCK(obj->base.vm_obj);
4262 for (i = 0; i < page_count; i++) {
4629 struct sf_buf *sf;
4630 char *dst, *src;
4631 int ret = 0;
4632 int page_count;
4633 int i;
4634
4635 if (id > I915_MAX_PHYS_OBJECT)
4636 return -EINVAL;

--- 18 unchanged lines hidden (view full) ---

4655 /* bind to the object */
4656 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4657 obj->phys_obj->cur_obj = obj;
4658
4659 page_count = obj->base.size / PAGE_SIZE;
4660
4661 VM_OBJECT_WLOCK(obj->base.vm_obj);
4662 for (i = 0; i < page_count; i++) {
4263 page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4663 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4264 if (page == NULL) {
4265 ret = -EIO;
4266 break;
4267 }
4268 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4269 sf = sf_buf_alloc(page, 0);
4270 src = (char *)sf_buf_kva(sf);
4271 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);

--- 43 unchanged lines hidden (view full) ---

4315void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4316{
4317 struct drm_i915_file_private *file_priv = file->driver_priv;
4318
4319 /* Clean up our request list when the client is going away, so that
4320 * later retire_requests won't dereference our soon-to-be-gone
4321 * file_priv.
4322 */
4664 if (page == NULL) {
4665 ret = -EIO;
4666 break;
4667 }
4668 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4669 sf = sf_buf_alloc(page, 0);
4670 src = (char *)sf_buf_kva(sf);
4671 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);

--- 43 unchanged lines hidden (view full) ---

4715void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4716{
4717 struct drm_i915_file_private *file_priv = file->driver_priv;
4718
4719 /* Clean up our request list when the client is going away, so that
4720 * later retire_requests won't dereference our soon-to-be-gone
4721 * file_priv.
4722 */
4323 mtx_lock(&file_priv->mm.lck);
4723 mtx_lock(&file_priv->mm.lock);
4324 while (!list_empty(&file_priv->mm.request_list)) {
4325 struct drm_i915_gem_request *request;
4326
4327 request = list_first_entry(&file_priv->mm.request_list,
4328 struct drm_i915_gem_request,
4329 client_list);
4330 list_del(&request->client_list);
4331 request->file_priv = NULL;
4332 }
4724 while (!list_empty(&file_priv->mm.request_list)) {
4725 struct drm_i915_gem_request *request;
4726
4727 request = list_first_entry(&file_priv->mm.request_list,
4728 struct drm_i915_gem_request,
4729 client_list);
4730 list_del(&request->client_list);
4731 request->file_priv = NULL;
4732 }
4333 mtx_unlock(&file_priv->mm.lck);
4733 mtx_unlock(&file_priv->mm.lock);
4334}
4335
4734}
4735
4736static void
4737i915_gem_inactive_shrink(void *arg)
4738{
4739 struct drm_device *dev = arg;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 int pass1, pass2;
4742
4743 if (!sx_try_xlock(&dev->dev_struct_lock)) {
4744 return;
4745 }
4746
4747 CTR0(KTR_DRM, "gem_lowmem");
4748
4749 pass1 = i915_gem_purge(dev_priv, -1);
4750 pass2 = __i915_gem_shrink(dev_priv, -1, false);
4751
4752 if (pass2 <= pass1 / 100)
4753 i915_gem_shrink_all(dev_priv);
4754
4755 DRM_UNLOCK(dev);
4756}
4757
4336static vm_page_t
4337i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex, bool *fresh)
4338{
4339 vm_page_t page;
4340 int rv;
4341
4342 VM_OBJECT_ASSERT_WLOCKED(object);
4343 page = vm_page_grab(object, pindex, VM_ALLOC_NORMAL);

--- 20 unchanged lines hidden (view full) ---

4364 }
4365 vm_page_lock(page);
4366 vm_page_wire(page);
4367 vm_page_unlock(page);
4368 vm_page_xunbusy(page);
4369 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
4370 return (page);
4371}
4758static vm_page_t
4759i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex, bool *fresh)
4760{
4761 vm_page_t page;
4762 int rv;
4763
4764 VM_OBJECT_ASSERT_WLOCKED(object);
4765 page = vm_page_grab(object, pindex, VM_ALLOC_NORMAL);

--- 20 unchanged lines hidden (view full) ---

4786 }
4787 vm_page_lock(page);
4788 vm_page_wire(page);
4789 vm_page_unlock(page);
4790 vm_page_xunbusy(page);
4791 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
4792 return (page);
4793}
4372
4373#undef __user
4374#undef __force
4375#undef __iomem
4376#undef __must_check
4377#undef to_user_ptr
4378#undef offset_in_page
4379#undef page_to_phys