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i915_gem.c (285988) i915_gem.c (287174)
1/*-
1/*
2 * Copyright �� 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:

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47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * SUCH DAMAGE.
52 */
53
54#include <sys/cdefs.h>
2 * Copyright �� 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:

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47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * SUCH DAMAGE.
52 */
53
54#include <sys/cdefs.h>
55__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 285988 2015-07-28 21:47:37Z dumbbell $");
55__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 287174 2015-08-26 21:35:16Z bapt $");
56
57#include <dev/drm2/drmP.h>
58#include <dev/drm2/drm.h>
59#include <dev/drm2/i915/i915_drm.h>
60#include <dev/drm2/i915/i915_drv.h>
61#include <dev/drm2/i915/intel_drv.h>
62#include <dev/drm2/i915/intel_ringbuffer.h>
63

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198 */
199 ret = -sx_xlock_sig(&dev->dev_struct_lock);
200 if (ret)
201 return ret;
202
203 return 0;
204}
205
56
57#include <dev/drm2/drmP.h>
58#include <dev/drm2/drm.h>
59#include <dev/drm2/i915/i915_drm.h>
60#include <dev/drm2/i915/i915_drv.h>
61#include <dev/drm2/i915/intel_drv.h>
62#include <dev/drm2/i915/intel_ringbuffer.h>
63

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198 */
199 ret = -sx_xlock_sig(&dev->dev_struct_lock);
200 if (ret)
201 return ret;
202
203 return 0;
204}
205
206static bool
206static inline bool
207i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
208{
207i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
208{
209
210 return !obj->active;
209 return obj->gtt_space && !obj->active;
211}
212
213int
214i915_gem_init_ioctl(struct drm_device *dev, void *data,
215 struct drm_file *file)
216{
217 struct drm_i915_gem_init *args = data;
218 drm_i915_private_t *dev_priv = dev->dev_private;

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1234 struct drm_file *file)
1235{
1236 struct drm_i915_gem_set_domain *args = data;
1237 struct drm_i915_gem_object *obj;
1238 uint32_t read_domains = args->read_domains;
1239 uint32_t write_domain = args->write_domain;
1240 int ret;
1241
210}
211
212int
213i915_gem_init_ioctl(struct drm_device *dev, void *data,
214 struct drm_file *file)
215{
216 struct drm_i915_gem_init *args = data;
217 drm_i915_private_t *dev_priv = dev->dev_private;

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1233 struct drm_file *file)
1234{
1235 struct drm_i915_gem_set_domain *args = data;
1236 struct drm_i915_gem_object *obj;
1237 uint32_t read_domains = args->read_domains;
1238 uint32_t write_domain = args->write_domain;
1239 int ret;
1240
1242 if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1243 (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1244 (write_domain != 0 && read_domains != write_domain))
1241 /* Only handle setting domains to types used by the CPU. */
1242 if (write_domain & I915_GEM_GPU_DOMAINS)
1245 return -EINVAL;
1246
1243 return -EINVAL;
1244
1245 if (read_domains & I915_GEM_GPU_DOMAINS)
1246 return -EINVAL;
1247
1248 /* Having something in the write domain implies it's in the read
1249 * domain, and only that read domain. Enforce that in the request.
1250 */
1251 if (write_domain != 0 && read_domains != write_domain)
1252 return -EINVAL;
1253
1247 ret = i915_mutex_lock_interruptible(dev);
1248 if (ret)
1249 return ret;
1250
1251 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252 if (&obj->base == NULL) {
1253 ret = -ENOENT;
1254 goto unlock;

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1681 * Return the required GTT alignment for an object, only taking into account
1682 * unfenced tiled surface requirements.
1683 */
1684uint32_t
1685i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1686 uint32_t size,
1687 int tiling_mode)
1688{
1254 ret = i915_mutex_lock_interruptible(dev);
1255 if (ret)
1256 return ret;
1257
1258 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1259 if (&obj->base == NULL) {
1260 ret = -ENOENT;
1261 goto unlock;

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1688 * Return the required GTT alignment for an object, only taking into account
1689 * unfenced tiled surface requirements.
1690 */
1691uint32_t
1692i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1693 uint32_t size,
1694 int tiling_mode)
1695{
1689 if (tiling_mode == I915_TILING_NONE)
1690 return 4096;
1691
1692 /*
1693 * Minimum alignment is 4k (GTT page size) for sane hw.
1694 */
1696 /*
1697 * Minimum alignment is 4k (GTT page size) for sane hw.
1698 */
1695 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
1699 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1700 tiling_mode == I915_TILING_NONE)
1696 return 4096;
1697
1698 /* Previous hardware however needs to be aligned to a power-of-two
1699 * tile height. The simplest method for determining this is to reuse
1700 * the power-of-tile object size.
1701 */
1702 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1703}

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3150 if (obj->gtt_space == NULL)
3151 return -EINVAL;
3152
3153 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3154 return 0;
3155
3156 ret = i915_gem_object_flush_gpu_write_domain(obj);
3157 if (ret)
1701 return 4096;
1702
1703 /* Previous hardware however needs to be aligned to a power-of-two
1704 * tile height. The simplest method for determining this is to reuse
1705 * the power-of-tile object size.
1706 */
1707 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1708}

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3155 if (obj->gtt_space == NULL)
3156 return -EINVAL;
3157
3158 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3159 return 0;
3160
3161 ret = i915_gem_object_flush_gpu_write_domain(obj);
3162 if (ret)
3158 return (ret);
3163 return ret;
3159
3160 if (obj->pending_gpu_write || write) {
3161 ret = i915_gem_object_wait_rendering(obj);
3162 if (ret)
3163 return (ret);
3164 }
3165
3166 i915_gem_object_flush_cpu_write_domain(obj);

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3361 if (ret)
3362 return ret;
3363
3364 /* Ensure that we invalidate the GPU's caches and TLBs. */
3365 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3366 return 0;
3367}
3368
3164
3165 if (obj->pending_gpu_write || write) {
3166 ret = i915_gem_object_wait_rendering(obj);
3167 if (ret)
3168 return (ret);
3169 }
3170
3171 i915_gem_object_flush_cpu_write_domain(obj);

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3366 if (ret)
3367 return ret;
3368
3369 /* Ensure that we invalidate the GPU's caches and TLBs. */
3370 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3371 return 0;
3372}
3373
3374/**
3375 * Moves a single object to the CPU read, and possibly write domain.
3376 *
3377 * This function returns when the move is complete, including waiting on
3378 * flushes to occur.
3379 */
3369int
3370i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3371{
3372 uint32_t old_write_domain, old_read_domains;
3373 int ret;
3374
3375 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3376 return 0;

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3639 DRM_UNLOCK(dev);
3640 return ret;
3641}
3642
3643int
3644i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3645 struct drm_file *file_priv)
3646{
3380int
3381i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3382{
3383 uint32_t old_write_domain, old_read_domains;
3384 int ret;
3385
3386 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3387 return 0;

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3650 DRM_UNLOCK(dev);
3651 return ret;
3652}
3653
3654int
3655i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3656 struct drm_file *file_priv)
3657{
3647
3648 return i915_gem_ring_throttle(dev, file_priv);
3649}
3650
3651int
3652i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3653 struct drm_file *file_priv)
3654{
3655 struct drm_i915_gem_madvise *args = data;

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4096i915_gem_unload(struct drm_device *dev)
4097{
4098 struct drm_i915_private *dev_priv;
4099
4100 dev_priv = dev->dev_private;
4101 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
4102}
4103
3658 return i915_gem_ring_throttle(dev, file_priv);
3659}
3660
3661int
3662i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3663 struct drm_file *file_priv)
3664{
3665 struct drm_i915_gem_madvise *args = data;

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4106i915_gem_unload(struct drm_device *dev)
4107{
4108 struct drm_i915_private *dev_priv;
4109
4110 dev_priv = dev->dev_private;
4111 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
4112}
4113
4114/*
4115 * Create a physically contiguous memory object for this object
4116 * e.g. for cursor + overlay regs
4117 */
4104static int i915_gem_init_phys_object(struct drm_device *dev,
4105 int id, int size, int align)
4106{
4107 drm_i915_private_t *dev_priv = dev->dev_private;
4108 struct drm_i915_gem_phys_object *phys_obj;
4109 int ret;
4110
4111 if (dev_priv->mm.phys_objs[id - 1] || !size)

--- 251 unchanged lines hidden --- 		4118static int i915_gem_init_phys_object(struct drm_device *dev,
4119 int id, int size, int align)
4120{
4121 drm_i915_private_t *dev_priv = dev->dev_private;
4122 struct drm_i915_gem_phys_object *phys_obj;
4123 int ret;
4124
4125 if (dev_priv->mm.phys_objs[id - 1] || !size)

--- 251 unchanged lines hidden ---