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i915_drv.c (290070) i915_drv.c (296548)
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
3 */
2 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
14 *
15 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
18 *
19 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32#include <sys/cdefs.h>
28 */
29
30#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 290070 2015-10-27 21:23:19Z dumbbell $");
31__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 296548 2016-03-08 20:33:02Z dumbbell $");
34
35#include <dev/drm2/drmP.h>
32
33#include <dev/drm2/drmP.h>
36#include <dev/drm2/drm.h>
37#include <dev/drm2/drm_mm.h>
38#include <dev/drm2/i915/i915_drm.h>
39#include <dev/drm2/i915/i915_drv.h>
40#include <dev/drm2/drm_pciids.h>
34#include <dev/drm2/drm_pciids.h>
41#include <dev/drm2/i915/intel_drv.h>
35#include <dev/drm2/i915/i915_drm.h>
36#include "dev/drm2/i915/i915_drv.h"
37#ifdef __linux__
38#include "dev/drm2/i915/i915_trace.h"
39#endif
40#include "dev/drm2/i915/intel_drv.h"
42
41
42#include <dev/drm2/drm_crtc_helper.h>
43
43#include "fb_if.h"
44
44#include "fb_if.h"
45
45int intel_iommu_enabled = 0;
46TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
47int intel_iommu_gfx_mapped = 0;
48TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
46static int i915_modeset __read_mostly = 1;
47TUNABLE_INT("drm.i915.modeset", &i915_modeset);
48module_param_named(modeset, i915_modeset, int, 0400);
49MODULE_PARM_DESC(modeset,
50 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
51 "1=on, -1=force vga console preference [default])");
49
52
50int i915_prefault_disable;
51TUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable);
52int i915_semaphores = -1;
53TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
54static int i915_try_reset = 1;
55TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
56unsigned int i915_lvds_downclock = 0;
57TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
58int i915_vbt_sdvo_panel_type = -1;
59TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
60unsigned int i915_powersave = 1;
53#ifdef __linux__
54unsigned int i915_fbpercrtc __always_unused = 0;
55module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
56#endif
57
58int i915_panel_ignore_lid __read_mostly = 1;
59TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
60module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
61MODULE_PARM_DESC(panel_ignore_lid,
62 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
63 "-1=force lid closed, -2=force lid open)");
64
65unsigned int i915_powersave __read_mostly = 1;
61TUNABLE_INT("drm.i915.powersave", &i915_powersave);
66TUNABLE_INT("drm.i915.powersave", &i915_powersave);
62int i915_enable_fbc = 0;
63TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
64int i915_enable_rc6 = 0;
67module_param_named(powersave, i915_powersave, int, 0600);
68MODULE_PARM_DESC(powersave,
69 "Enable powersavings, fbc, downclocking, etc. (default: true)");
70
71int i915_semaphores __read_mostly = -1;
72TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
73module_param_named(semaphores, i915_semaphores, int, 0600);
74MODULE_PARM_DESC(semaphores,
75 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
76
77int i915_enable_rc6 __read_mostly = -1;
65TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
78TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
66int i915_lvds_channel_mode;
79module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
80MODULE_PARM_DESC(i915_enable_rc6,
81 "Enable power-saving render C-state 6. "
82 "Different stages can be selected via bitmask values "
83 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
84 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
85 "default: -1 (use per-chip default)");
86
87int i915_enable_fbc __read_mostly = -1;
88TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
89module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
90MODULE_PARM_DESC(i915_enable_fbc,
91 "Enable frame buffer compression for power savings "
92 "(default: -1 (use per-chip default))");
93
94unsigned int i915_lvds_downclock __read_mostly = 0;
95TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
96module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
97MODULE_PARM_DESC(lvds_downclock,
98 "Use panel (LVDS/eDP) downclocking for power savings "
99 "(default: false)");
100
101int i915_lvds_channel_mode __read_mostly;
67TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
102TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
68int i915_panel_use_ssc = -1;
103module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
104MODULE_PARM_DESC(lvds_channel_mode,
105 "Specify LVDS channel mode "
106 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
107
108int i915_panel_use_ssc __read_mostly = -1;
69TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
109TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
70int i915_panel_ignore_lid = 0;
71TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
72int i915_panel_invert_brightness;
73TUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness);
74int i915_modeset = 1;
75TUNABLE_INT("drm.i915.modeset", &i915_modeset);
76int i915_enable_ppgtt = -1;
77TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
78int i915_enable_hangcheck = 1;
110module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
111MODULE_PARM_DESC(lvds_use_ssc,
112 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
113 "(default: auto from VBT)");
114
115int i915_vbt_sdvo_panel_type __read_mostly = -1;
116TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
117module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
118MODULE_PARM_DESC(vbt_sdvo_panel_type,
119 "Override/Ignore selection of SDVO panel mode in the VBT "
120 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
121
122static int i915_try_reset __read_mostly = true;
123TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
124module_param_named(reset, i915_try_reset, bool, 0600);
125MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
126
127int i915_enable_hangcheck __read_mostly = true;
79TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
128TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
80static int i915_enable_unsupported = 0;
81TUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported);
129module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
130MODULE_PARM_DESC(enable_hangcheck,
131 "Periodically check GPU activity for detecting hangs. "
132 "WARNING: Disabling this can cause system wide hangs. "
133 "(default: true)");
82
134
83/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
84static drm_pci_id_list_t i915_pciidlist[] = {
85 i915_PCI_IDS
86};
135int i915_enable_ppgtt __read_mostly = -1;
136TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
137module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
138MODULE_PARM_DESC(i915_enable_ppgtt,
139 "Enable PPGTT (default: true)");
87
140
141unsigned int i915_preliminary_hw_support __read_mostly = 0;
142TUNABLE_INT("drm.i915.enable_unsupported", &i915_preliminary_hw_support);
143module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
144MODULE_PARM_DESC(preliminary_hw_support,
145 "Enable preliminary hardware support. "
146 "Enable Haswell and ValleyView Support. "
147 "(default: false)");
148
149int intel_iommu_gfx_mapped = 0;
150TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
151
152static struct drm_driver driver;
153int intel_agp_enabled = 1; /* On FreeBSD, agp is a required dependency. */
154
88#define INTEL_VGA_DEVICE(id, info_) { \
89 .device = id, \
90 .info = info_, \
91}
92
93static const struct intel_device_info intel_i830_info = {
94 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
95 .has_overlay = 1, .overlay_needs_physical = 1,

--- 74 unchanged lines hidden (view full) ---

170 .need_gfx_hws = 1, .has_hotplug = 1,
171 .has_overlay = 1,
172};
173
174static const struct intel_device_info intel_ironlake_d_info = {
175 .gen = 5,
176 .need_gfx_hws = 1, .has_hotplug = 1,
177 .has_bsd_ring = 1,
155#define INTEL_VGA_DEVICE(id, info_) { \
156 .device = id, \
157 .info = info_, \
158}
159
160static const struct intel_device_info intel_i830_info = {
161 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
162 .has_overlay = 1, .overlay_needs_physical = 1,

--- 74 unchanged lines hidden (view full) ---

237 .need_gfx_hws = 1, .has_hotplug = 1,
238 .has_overlay = 1,
239};
240
241static const struct intel_device_info intel_ironlake_d_info = {
242 .gen = 5,
243 .need_gfx_hws = 1, .has_hotplug = 1,
244 .has_bsd_ring = 1,
178 .has_pch_split = 1,
179};
180
181static const struct intel_device_info intel_ironlake_m_info = {
182 .gen = 5, .is_mobile = 1,
183 .need_gfx_hws = 1, .has_hotplug = 1,
245};
246
247static const struct intel_device_info intel_ironlake_m_info = {
248 .gen = 5, .is_mobile = 1,
249 .need_gfx_hws = 1, .has_hotplug = 1,
184 .has_fbc = 0, /* disabled due to buggy hardware */
250 .has_fbc = 1,
185 .has_bsd_ring = 1,
251 .has_bsd_ring = 1,
186 .has_pch_split = 1,
187};
188
189static const struct intel_device_info intel_sandybridge_d_info = {
190 .gen = 6,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .has_bsd_ring = 1,
193 .has_blt_ring = 1,
194 .has_llc = 1,
252};
253
254static const struct intel_device_info intel_sandybridge_d_info = {
255 .gen = 6,
256 .need_gfx_hws = 1, .has_hotplug = 1,
257 .has_bsd_ring = 1,
258 .has_blt_ring = 1,
259 .has_llc = 1,
195 .has_pch_split = 1,
260 .has_force_wake = 1,
196};
197
198static const struct intel_device_info intel_sandybridge_m_info = {
199 .gen = 6, .is_mobile = 1,
200 .need_gfx_hws = 1, .has_hotplug = 1,
201 .has_fbc = 1,
202 .has_bsd_ring = 1,
203 .has_blt_ring = 1,
204 .has_llc = 1,
261};
262
263static const struct intel_device_info intel_sandybridge_m_info = {
264 .gen = 6, .is_mobile = 1,
265 .need_gfx_hws = 1, .has_hotplug = 1,
266 .has_fbc = 1,
267 .has_bsd_ring = 1,
268 .has_blt_ring = 1,
269 .has_llc = 1,
205 .has_pch_split = 1,
270 .has_force_wake = 1,
206};
207
208static const struct intel_device_info intel_ivybridge_d_info = {
209 .is_ivybridge = 1, .gen = 7,
210 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_bsd_ring = 1,
212 .has_blt_ring = 1,
213 .has_llc = 1,
271};
272
273static const struct intel_device_info intel_ivybridge_d_info = {
274 .is_ivybridge = 1, .gen = 7,
275 .need_gfx_hws = 1, .has_hotplug = 1,
276 .has_bsd_ring = 1,
277 .has_blt_ring = 1,
278 .has_llc = 1,
214 .has_pch_split = 1,
279 .has_force_wake = 1,
215};
216
217static const struct intel_device_info intel_ivybridge_m_info = {
218 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
219 .need_gfx_hws = 1, .has_hotplug = 1,
220 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
221 .has_bsd_ring = 1,
222 .has_blt_ring = 1,
223 .has_llc = 1,
280};
281
282static const struct intel_device_info intel_ivybridge_m_info = {
283 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
284 .need_gfx_hws = 1, .has_hotplug = 1,
285 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
286 .has_bsd_ring = 1,
287 .has_blt_ring = 1,
288 .has_llc = 1,
224 .has_pch_split = 1,
289 .has_force_wake = 1,
225};
226
227static const struct intel_device_info intel_valleyview_m_info = {
228 .gen = 7, .is_mobile = 1,
229 .need_gfx_hws = 1, .has_hotplug = 1,
230 .has_fbc = 0,
231 .has_bsd_ring = 1,
232 .has_blt_ring = 1,
233 .is_valleyview = 1,
290};
291
292static const struct intel_device_info intel_valleyview_m_info = {
293 .gen = 7, .is_mobile = 1,
294 .need_gfx_hws = 1, .has_hotplug = 1,
295 .has_fbc = 0,
296 .has_bsd_ring = 1,
297 .has_blt_ring = 1,
298 .is_valleyview = 1,
234 .not_supported = 1,
235};
236
237static const struct intel_device_info intel_valleyview_d_info = {
238 .gen = 7,
239 .need_gfx_hws = 1, .has_hotplug = 1,
240 .has_fbc = 0,
241 .has_bsd_ring = 1,
242 .has_blt_ring = 1,
243 .is_valleyview = 1,
299};
300
301static const struct intel_device_info intel_valleyview_d_info = {
302 .gen = 7,
303 .need_gfx_hws = 1, .has_hotplug = 1,
304 .has_fbc = 0,
305 .has_bsd_ring = 1,
306 .has_blt_ring = 1,
307 .is_valleyview = 1,
244 .not_supported = 1,
245};
246
247static const struct intel_device_info intel_haswell_d_info = {
248 .is_haswell = 1, .gen = 7,
249 .need_gfx_hws = 1, .has_hotplug = 1,
250 .has_bsd_ring = 1,
251 .has_blt_ring = 1,
252 .has_llc = 1,
308};
309
310static const struct intel_device_info intel_haswell_d_info = {
311 .is_haswell = 1, .gen = 7,
312 .need_gfx_hws = 1, .has_hotplug = 1,
313 .has_bsd_ring = 1,
314 .has_blt_ring = 1,
315 .has_llc = 1,
253 .has_pch_split = 1,
254 .not_supported = 1,
316 .has_force_wake = 1,
255};
256
257static const struct intel_device_info intel_haswell_m_info = {
258 .is_haswell = 1, .gen = 7, .is_mobile = 1,
259 .need_gfx_hws = 1, .has_hotplug = 1,
260 .has_bsd_ring = 1,
261 .has_blt_ring = 1,
262 .has_llc = 1,
317};
318
319static const struct intel_device_info intel_haswell_m_info = {
320 .is_haswell = 1, .gen = 7, .is_mobile = 1,
321 .need_gfx_hws = 1, .has_hotplug = 1,
322 .has_bsd_ring = 1,
323 .has_blt_ring = 1,
324 .has_llc = 1,
263 .has_pch_split = 1,
264 .not_supported = 1,
325 .has_force_wake = 1,
265};
266
326};
327
328/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
329static const drm_pci_id_list_t pciidlist[] = {
330 i915_PCI_IDS
331};
332
267static const struct intel_gfx_device_id {
268 int device;
269 const struct intel_device_info *info;
270} i915_infolist[] = { /* aka */
271 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
272 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
273 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
274 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),

--- 74 unchanged lines hidden (view full) ---

349 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
350 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
351 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
352 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
353 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
354 {0, 0}
355};
356
333static const struct intel_gfx_device_id {
334 int device;
335 const struct intel_device_info *info;
336} i915_infolist[] = { /* aka */
337 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
338 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
339 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
340 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),

--- 74 unchanged lines hidden (view full) ---

415 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
416 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
417 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
418 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
419 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
420 {0, 0}
421};
422
357#define PCI_VENDOR_INTEL 0x8086
358#define INTEL_PCH_DEVICE_ID_MASK 0xff00
359#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
360#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
361#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
362#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
423#if defined(CONFIG_DRM_I915_KMS)
424MODULE_DEVICE_TABLE(pci, pciidlist);
425#endif
363
364void intel_detect_pch(struct drm_device *dev)
365{
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 device_t pch;
426
427void intel_detect_pch(struct drm_device *dev)
428{
429 struct drm_i915_private *dev_priv = dev->dev_private;
430 device_t pch;
368 uint32_t id;
369
431
432 /*
433 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
434 * make graphics device passthrough work easy for VMM, that only
435 * need to expose ISA bridge to let driver know the real hardware
436 * underneath. This is a requirement from virtualization team.
437 */
370 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
438 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
371 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
372 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
373 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
374 dev_priv->pch_type = PCH_IBX;
375 dev_priv->num_pch_pll = 2;
376 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
377 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
378 dev_priv->pch_type = PCH_CPT;
379 dev_priv->num_pch_pll = 2;
380 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
381 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
382 /* PantherPoint is CPT compatible */
383 dev_priv->pch_type = PCH_CPT;
384 dev_priv->num_pch_pll = 2;
385 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
386 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
387 dev_priv->pch_type = PCH_LPT;
388 dev_priv->num_pch_pll = 0;
389 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
390 } else
391 DRM_DEBUG_KMS("No PCH detected\n");
392 KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
393 ("num_pch_pll %d\n", dev_priv->num_pch_pll));
394 } else
395 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
439 if (pch) {
440 if (pci_get_vendor(pch) == PCI_VENDOR_ID_INTEL) {
441 unsigned short id;
442 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
443 dev_priv->pch_id = id;
444
445 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
446 dev_priv->pch_type = PCH_IBX;
447 dev_priv->num_pch_pll = 2;
448 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
449 WARN_ON(!IS_GEN5(dev));
450 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
451 dev_priv->pch_type = PCH_CPT;
452 dev_priv->num_pch_pll = 2;
453 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
454 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
455 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
456 /* PantherPoint is CPT compatible */
457 dev_priv->pch_type = PCH_CPT;
458 dev_priv->num_pch_pll = 2;
459 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
460 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
461 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
462 dev_priv->pch_type = PCH_LPT;
463 dev_priv->num_pch_pll = 0;
464 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
465 WARN_ON(!IS_HASWELL(dev));
466 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
467 dev_priv->pch_type = PCH_LPT;
468 dev_priv->num_pch_pll = 0;
469 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
470 WARN_ON(!IS_HASWELL(dev));
471 }
472 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
473 }
474 }
396}
397
398bool i915_semaphore_is_enabled(struct drm_device *dev)
399{
400 if (INTEL_INFO(dev)->gen < 6)
401 return 0;
402
403 if (i915_semaphores >= 0)
404 return i915_semaphores;
405
475}
476
477bool i915_semaphore_is_enabled(struct drm_device *dev)
478{
479 if (INTEL_INFO(dev)->gen < 6)
480 return 0;
481
482 if (i915_semaphores >= 0)
483 return i915_semaphores;
484
485#ifdef CONFIG_INTEL_IOMMU
406 /* Enable semaphores on SNB when IO remapping is off */
407 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
408 return false;
486 /* Enable semaphores on SNB when IO remapping is off */
487 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
488 return false;
489#endif
409
410 return 1;
411}
412
413static int i915_drm_freeze(struct drm_device *dev)
414{
415 struct drm_i915_private *dev_priv = dev->dev_private;
416
417 drm_kms_helper_poll_disable(dev);
418
490
491 return 1;
492}
493
494static int i915_drm_freeze(struct drm_device *dev)
495{
496 struct drm_i915_private *dev_priv = dev->dev_private;
497
498 drm_kms_helper_poll_disable(dev);
499
419#if 0
500#ifdef __linux__
420 pci_save_state(dev->pdev);
421#endif
422
423 /* If KMS is active, we do the leavevt stuff here */
424 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
425 int error = i915_gem_idle(dev);
426 if (error) {
501 pci_save_state(dev->pdev);
502#endif
503
504 /* If KMS is active, we do the leavevt stuff here */
505 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
506 int error = i915_gem_idle(dev);
507 if (error) {
427 device_printf(dev->dev,
508 dev_err(dev->dev,
428 "GEM idle failed, resume might fail\n");
429 return error;
430 }
509 "GEM idle failed, resume might fail\n");
510 return error;
511 }
512
513 taskqueue_cancel_timeout(dev_priv->wq,
514 &dev_priv->rps.delayed_resume_work, NULL);
515
516 intel_modeset_disable(dev);
517
431 drm_irq_uninstall(dev);
432 }
433
434 i915_save_state(dev);
435
436 intel_opregion_fini(dev);
437
438 /* Modeset on resume, not lid events */
439 dev_priv->modeset_on_lid = 0;
440
518 drm_irq_uninstall(dev);
519 }
520
521 i915_save_state(dev);
522
523 intel_opregion_fini(dev);
524
525 /* Modeset on resume, not lid events */
526 dev_priv->modeset_on_lid = 0;
527
528 console_lock();
529 intel_fbdev_set_suspend(dev, 1);
530 console_unlock();
531
441 return 0;
442}
443
532 return 0;
533}
534
444static int i915_suspend(device_t kdev)
535int i915_suspend(struct drm_device *dev, pm_message_t state)
445{
536{
446 struct drm_device *dev;
447 int error;
448
537 int error;
538
449 dev = device_get_softc(kdev);
450 if (!dev || !dev->dev_private) {
539 if (!dev || !dev->dev_private) {
540 DRM_ERROR("dev: %p\n", dev);
451 DRM_ERROR("DRM not initialized, aborting suspend.\n");
541 DRM_ERROR("DRM not initialized, aborting suspend.\n");
452 return ENODEV;
542 return -ENODEV;
453 }
454
543 }
544
455 DRM_DEBUG_KMS("starting suspend\n");
545 if (state.event == PM_EVENT_PRETHAW)
546 return 0;
547
548
549 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
550 return 0;
551
456 error = i915_drm_freeze(dev);
457 if (error)
552 error = i915_drm_freeze(dev);
553 if (error)
458 return -error;
554 return error;
459
555
460 error = bus_generic_suspend(kdev);
461 DRM_DEBUG_KMS("finished suspend %d\n", error);
462 return (error);
556 if (state.event == PM_EVENT_SUSPEND) {
557#ifdef __linux__
558 /* Shut down the device */
559 pci_disable_device(dev->pdev);
560 pci_set_power_state(dev->pdev, PCI_D3hot);
561#endif
562 }
563
564 return 0;
463}
464
565}
566
465static int i915_drm_thaw(struct drm_device *dev)
567void intel_console_resume(void *arg, int pending)
466{
568{
569 struct drm_i915_private *dev_priv =
570 arg;
571 struct drm_device *dev = dev_priv->dev;
572
573 console_lock();
574 intel_fbdev_set_suspend(dev, 0);
575 console_unlock();
576}
577
578static int __i915_drm_thaw(struct drm_device *dev)
579{
467 struct drm_i915_private *dev_priv = dev->dev_private;
468 int error = 0;
469
580 struct drm_i915_private *dev_priv = dev->dev_private;
581 int error = 0;
582
470 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
471 DRM_LOCK(dev);
472 i915_gem_restore_gtt_mappings(dev);
473 DRM_UNLOCK(dev);
474 }
475
476 i915_restore_state(dev);
477 intel_opregion_setup(dev);
478
479 /* KMS EnterVT equivalent */
480 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
583 i915_restore_state(dev);
584 intel_opregion_setup(dev);
585
586 /* KMS EnterVT equivalent */
587 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
481 if (HAS_PCH_SPLIT(dev))
482 ironlake_init_pch_refclk(dev);
588 intel_init_pch_refclk(dev);
483
484 DRM_LOCK(dev);
485 dev_priv->mm.suspended = 0;
486
487 error = i915_gem_init_hw(dev);
488 DRM_UNLOCK(dev);
489
490 intel_modeset_init_hw(dev);
589
590 DRM_LOCK(dev);
591 dev_priv->mm.suspended = 0;
592
593 error = i915_gem_init_hw(dev);
594 DRM_UNLOCK(dev);
595
596 intel_modeset_init_hw(dev);
491 sx_xlock(&dev->mode_config.mutex);
492 drm_mode_config_reset(dev);
493 sx_xunlock(&dev->mode_config.mutex);
597 intel_modeset_setup_hw_state(dev, false);
494 drm_irq_install(dev);
598 drm_irq_install(dev);
495
496 sx_xlock(&dev->mode_config.mutex);
497 /* Resume the modeset for every activated CRTC */
498 drm_helper_resume_force_mode(dev);
499 sx_xunlock(&dev->mode_config.mutex);
500 }
501
502 intel_opregion_init(dev);
503
504 dev_priv->modeset_on_lid = 0;
505
599 }
600
601 intel_opregion_init(dev);
602
603 dev_priv->modeset_on_lid = 0;
604
605 /*
606 * The console lock can be pretty contented on resume due
607 * to all the printk activity. Try to keep it out of the hot
608 * path of resume if possible.
609 */
610 if (console_trylock()) {
611 intel_fbdev_set_suspend(dev, 0);
612 console_unlock();
613 } else {
614 taskqueue_enqueue(dev_priv->wq,
615 &dev_priv->console_resume_work);
616 }
617
506 return error;
507}
508
618 return error;
619}
620
509static int i915_resume(device_t kdev)
621#ifdef __linux__
622static int i915_drm_thaw(struct drm_device *dev)
510{
623{
511 struct drm_device *dev;
624 int error = 0;
625
626 intel_gt_reset(dev);
627
628 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
629 DRM_LOCK(dev);
630 i915_gem_restore_gtt_mappings(dev);
631 DRM_UNLOCK(dev);
632 }
633
634 __i915_drm_thaw(dev);
635
636 return error;
637}
638#endif
639
640int i915_resume(struct drm_device *dev)
641{
642 struct drm_i915_private *dev_priv = dev->dev_private;
512 int ret;
513
643 int ret;
644
514 dev = device_get_softc(kdev);
515 DRM_DEBUG_KMS("starting resume\n");
516#if 0
645 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
646 return 0;
647
648#ifdef __linux__
517 if (pci_enable_device(dev->pdev))
518 return -EIO;
519
520 pci_set_master(dev->pdev);
521#endif
522
649 if (pci_enable_device(dev->pdev))
650 return -EIO;
651
652 pci_set_master(dev->pdev);
653#endif
654
523 ret = i915_drm_thaw(dev);
655 intel_gt_reset(dev);
656
657 /*
658 * Platforms with opregion should have sane BIOS, older ones (gen3 and
659 * earlier) need this since the BIOS might clear all our scratch PTEs.
660 */
661 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
662 !dev_priv->opregion.header) {
663 DRM_LOCK(dev);
664 i915_gem_restore_gtt_mappings(dev);
665 DRM_UNLOCK(dev);
666 }
667
668 ret = __i915_drm_thaw(dev);
524 if (ret)
669 if (ret)
525 return -ret;
670 return ret;
526
527 drm_kms_helper_poll_enable(dev);
671
672 drm_kms_helper_poll_enable(dev);
528 ret = bus_generic_resume(kdev);
529 DRM_DEBUG_KMS("finished resume %d\n", ret);
530 return (ret);
673 return 0;
531}
532
533static int i8xx_do_reset(struct drm_device *dev)
534{
535 struct drm_i915_private *dev_priv = dev->dev_private;
536 int onems;
537
538 if (IS_I85X(dev))

--- 24 unchanged lines hidden (view full) ---

563 POSTING_READ(D_STATE);
564
565 return 0;
566}
567
568static int i965_reset_complete(struct drm_device *dev)
569{
570 u8 gdrst;
674}
675
676static int i8xx_do_reset(struct drm_device *dev)
677{
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 int onems;
680
681 if (IS_I85X(dev))

--- 24 unchanged lines hidden (view full) ---

706 POSTING_READ(D_STATE);
707
708 return 0;
709}
710
711static int i965_reset_complete(struct drm_device *dev)
712{
713 u8 gdrst;
571
572 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
714 pci_read_config_byte(dev->dev, I965_GDRST, &gdrst);
573 return (gdrst & GRDOM_RESET_ENABLE) == 0;
574}
575
576static int i965_do_reset(struct drm_device *dev)
577{
578 int ret;
579 u8 gdrst;
580
581 /*
582 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
583 * well as the reset bit (GR/bit 0). Setting the GR bit
584 * triggers the reset; when done, the hardware will clear it.
585 */
715 return (gdrst & GRDOM_RESET_ENABLE) == 0;
716}
717
718static int i965_do_reset(struct drm_device *dev)
719{
720 int ret;
721 u8 gdrst;
722
723 /*
724 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
725 * well as the reset bit (GR/bit 0). Setting the GR bit
726 * triggers the reset; when done, the hardware will clear it.
727 */
586 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
587 pci_write_config(dev->dev, I965_GDRST,
728 pci_read_config_byte(dev->dev, I965_GDRST, &gdrst);
729 pci_write_config_byte(dev->dev, I965_GDRST,
588 gdrst | GRDOM_RENDER |
730 gdrst | GRDOM_RENDER |
589 GRDOM_RESET_ENABLE, 1);
731 GRDOM_RESET_ENABLE);
590 ret = wait_for(i965_reset_complete(dev), 500);
591 if (ret)
592 return ret;
593
594 /* We can't reset render&media without also resetting display ... */
732 ret = wait_for(i965_reset_complete(dev), 500);
733 if (ret)
734 return ret;
735
736 /* We can't reset render&media without also resetting display ... */
595 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
596 pci_write_config(dev->dev, I965_GDRST,
737 pci_read_config_byte(dev->dev, I965_GDRST, &gdrst);
738 pci_write_config_byte(dev->dev, I965_GDRST,
597 gdrst | GRDOM_MEDIA |
739 gdrst | GRDOM_MEDIA |
598 GRDOM_RESET_ENABLE, 1);
740 GRDOM_RESET_ENABLE);
599
600 return wait_for(i965_reset_complete(dev), 500);
601}
602
603static int ironlake_do_reset(struct drm_device *dev)
604{
605 struct drm_i915_private *dev_priv = dev->dev_private;
606 u32 gdrst;

--- 27 unchanged lines hidden (view full) ---

634
635 /* GEN6_GDRST is not in the gt power well, no need to check
636 * for fifo space for the write or forcewake the chip for
637 * the read
638 */
639 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
640
641 /* Spin waiting for the device to ack the reset request */
741
742 return wait_for(i965_reset_complete(dev), 500);
743}
744
745static int ironlake_do_reset(struct drm_device *dev)
746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 u32 gdrst;

--- 27 unchanged lines hidden (view full) ---

776
777 /* GEN6_GDRST is not in the gt power well, no need to check
778 * for fifo space for the write or forcewake the chip for
779 * the read
780 */
781 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
782
783 /* Spin waiting for the device to ack the reset request */
784 /*
785 * NOTE Linux<->FreeBSD: We use _intel_wait_for() instead of
786 * wait_for(), because we want to set the 4th argument to 0.
787 * This allows us to use a struct mtx for dev_priv->gt_lock and
788 * avoid a LOR.
789 */
642 ret = _intel_wait_for(dev,
643 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
644 500, 0, "915rst");
645
646 /* If reset with a user forcewake, try to restore, otherwise turn it off */
647 if (dev_priv->forcewake_count)
790 ret = _intel_wait_for(dev,
791 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
792 500, 0, "915rst");
793
794 /* If reset with a user forcewake, try to restore, otherwise turn it off */
795 if (dev_priv->forcewake_count)
648 dev_priv->display.force_wake_get(dev_priv);
796 dev_priv->gt.force_wake_get(dev_priv);
649 else
797 else
650 dev_priv->display.force_wake_put(dev_priv);
798 dev_priv->gt.force_wake_put(dev_priv);
651
652 /* Restore fifo count */
653 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
654
655 mtx_unlock(&dev_priv->gt_lock);
656 return ret;
657}
658

--- 50 unchanged lines hidden (view full) ---

709int i915_reset(struct drm_device *dev)
710{
711 drm_i915_private_t *dev_priv = dev->dev_private;
712 int ret;
713
714 if (!i915_try_reset)
715 return 0;
716
799
800 /* Restore fifo count */
801 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
802
803 mtx_unlock(&dev_priv->gt_lock);
804 return ret;
805}
806

--- 50 unchanged lines hidden (view full) ---

857int i915_reset(struct drm_device *dev)
858{
859 drm_i915_private_t *dev_priv = dev->dev_private;
860 int ret;
861
862 if (!i915_try_reset)
863 return 0;
864
717 if (!sx_try_xlock(&dev->dev_struct_lock))
718 return (-EBUSY);
865 DRM_LOCK(dev);
719
866
720 dev_priv->stop_rings = 0;
721
722 i915_gem_reset(dev);
723
724 ret = -ENODEV;
867 i915_gem_reset(dev);
868
869 ret = -ENODEV;
725 if (time_second - dev_priv->last_gpu_reset < 5)
870 if (get_seconds() - dev_priv->last_gpu_reset < 5)
726 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
727 else
728 ret = intel_gpu_reset(dev);
729
871 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
872 else
873 ret = intel_gpu_reset(dev);
874
730 dev_priv->last_gpu_reset = time_second;
875 dev_priv->last_gpu_reset = get_seconds();
731 if (ret) {
732 DRM_ERROR("Failed to reset chip.\n");
733 DRM_UNLOCK(dev);
734 return ret;
735 }
736
737 /* Ok, now get things going again... */
738

--- 27 unchanged lines hidden (view full) ---

766 /*
767 * It would make sense to re-init all the other hw state, at
768 * least the rps/rc6/emon init done within modeset_init_hw. For
769 * some unknown reason, this blows up my ilk, so don't.
770 */
771
772 DRM_UNLOCK(dev);
773
876 if (ret) {
877 DRM_ERROR("Failed to reset chip.\n");
878 DRM_UNLOCK(dev);
879 return ret;
880 }
881
882 /* Ok, now get things going again... */
883

--- 27 unchanged lines hidden (view full) ---

911 /*
912 * It would make sense to re-init all the other hw state, at
913 * least the rps/rc6/emon init done within modeset_init_hw. For
914 * some unknown reason, this blows up my ilk, so don't.
915 */
916
917 DRM_UNLOCK(dev);
918
774 if (drm_core_check_feature(dev, DRIVER_MODESET))
775 intel_modeset_init_hw(dev);
776
777 drm_irq_uninstall(dev);
778 drm_irq_install(dev);
779 } else {
780 DRM_UNLOCK(dev);
781 }
782
783 return 0;
784}
785
786const struct intel_device_info *
787i915_get_device_id(int device)
788{
789 const struct intel_gfx_device_id *did;
790
791 for (did = &i915_infolist[0]; did->device != 0; did++) {
792 if (did->device != device)
793 continue;
919 drm_irq_uninstall(dev);
920 drm_irq_install(dev);
921 } else {
922 DRM_UNLOCK(dev);
923 }
924
925 return 0;
926}
927
928const struct intel_device_info *
929i915_get_device_id(int device)
930{
931 const struct intel_gfx_device_id *did;
932
933 for (did = &i915_infolist[0]; did->device != 0; did++) {
934 if (did->device != device)
935 continue;
794 if (did->info->not_supported && !i915_enable_unsupported)
795 return (NULL);
796 return (did->info);
797 }
798 return (NULL);
799}
800
801static int i915_probe(device_t kdev)
802{
803 const struct intel_device_info *intel_info =
804 i915_get_device_id(pci_get_device(kdev));
805
806 if (intel_info == NULL)
807 return (ENXIO);
936 return (did->info);
937 }
938 return (NULL);
939}
940
941static int i915_probe(device_t kdev)
942{
943 const struct intel_device_info *intel_info =
944 i915_get_device_id(pci_get_device(kdev));
945
946 if (intel_info == NULL)
947 return (ENXIO);
948 if (intel_info->is_valleyview)
949 if(!i915_preliminary_hw_support) {
950 DRM_ERROR("Preliminary hardware support disabled\n");
951 return (ENXIO);
952 }
808
953
809 return -drm_probe_helper(kdev, i915_pciidlist);
954 /* Only bind to function 0 of the device. Early generations
955 * used function 1 as a placeholder for multi-head. This causes
956 * us confusion instead, especially on the systems where both
957 * functions have the same PCI-ID!
958 */
959 if (pci_get_function(kdev))
960 return (ENXIO);
961
962 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
963 * implementation for gen3 (and only gen3) that used legacy drm maps
964 * (gasp!) to share buffers between X and the client. Hence we need to
965 * keep around the fake agp stuff for gen3, even when kms is enabled. */
966 if (intel_info->gen != 3) {
967 driver.driver_features &=
968 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
969 } else if (!intel_agp_enabled) {
970 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
971 return (ENXIO);
972 }
973
974 return -drm_probe_helper(kdev, pciidlist);
810}
811
975}
976
812static int i915_attach(device_t kdev)
977#ifdef __linux__
978static void
979i915_pci_remove(struct pci_dev *pdev)
813{
980{
981 struct drm_device *dev = pci_get_drvdata(pdev);
814
982
983 drm_put_dev(dev);
984}
985
986static int i915_pm_suspend(struct device *dev)
987{
988 struct pci_dev *pdev = to_pci_dev(dev);
989 struct drm_device *drm_dev = pci_get_drvdata(pdev);
990 int error;
991
992 if (!drm_dev || !drm_dev->dev_private) {
993 dev_err(dev, "DRM not initialized, aborting suspend.\n");
994 return -ENODEV;
995 }
996
997 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
998 return 0;
999
1000 error = i915_drm_freeze(drm_dev);
1001 if (error)
1002 return error;
1003
1004 pci_disable_device(pdev);
1005 pci_set_power_state(pdev, PCI_D3hot);
1006
1007 return 0;
1008}
1009
1010static int i915_pm_resume(struct device *dev)
1011{
1012 struct pci_dev *pdev = to_pci_dev(dev);
1013 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1014
1015 return i915_resume(drm_dev);
1016}
1017
1018static int i915_pm_freeze(struct device *dev)
1019{
1020 struct pci_dev *pdev = to_pci_dev(dev);
1021 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1022
1023 if (!drm_dev || !drm_dev->dev_private) {
1024 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1025 return -ENODEV;
1026 }
1027
1028 return i915_drm_freeze(drm_dev);
1029}
1030
1031static int i915_pm_thaw(struct device *dev)
1032{
1033 struct pci_dev *pdev = to_pci_dev(dev);
1034 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1035
1036 return i915_drm_thaw(drm_dev);
1037}
1038
1039static int i915_pm_poweroff(struct device *dev)
1040{
1041 struct pci_dev *pdev = to_pci_dev(dev);
1042 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1043
1044 return i915_drm_freeze(drm_dev);
1045}
1046
1047static const struct dev_pm_ops i915_pm_ops = {
1048 .suspend = i915_pm_suspend,
1049 .resume = i915_pm_resume,
1050 .freeze = i915_pm_freeze,
1051 .thaw = i915_pm_thaw,
1052 .poweroff = i915_pm_poweroff,
1053 .restore = i915_pm_resume,
1054};
1055
1056static const struct vm_operations_struct i915_gem_vm_ops = {
1057 .fault = i915_gem_fault,
1058 .open = drm_gem_vm_open,
1059 .close = drm_gem_vm_close,
1060};
1061
1062static const struct file_operations i915_driver_fops = {
1063 .owner = THIS_MODULE,
1064 .open = drm_open,
1065 .release = drm_release,
1066 .unlocked_ioctl = drm_ioctl,
1067 .mmap = drm_gem_mmap,
1068 .poll = drm_poll,
1069 .fasync = drm_fasync,
1070 .read = drm_read,
1071#ifdef CONFIG_COMPAT
1072 .compat_ioctl = i915_compat_ioctl,
1073#endif
1074 .llseek = noop_llseek,
1075};
1076#endif /* __linux__ */
1077
1078#ifdef COMPAT_FREEBSD32
1079extern struct drm_ioctl_desc i915_compat_ioctls[];
1080extern int i915_compat_ioctls_nr;
1081#endif
1082
1083static struct drm_driver driver = {
1084 /* Don't use MTRRs here; the Xserver or userspace app should
1085 * deal with them for Intel hardware.
1086 */
1087 .driver_features =
1088 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1089 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1090 .load = i915_driver_load,
1091 .unload = i915_driver_unload,
1092 .open = i915_driver_open,
1093 .lastclose = i915_driver_lastclose,
1094 .preclose = i915_driver_preclose,
1095 .postclose = i915_driver_postclose,
1096
1097 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1098 .suspend = i915_suspend,
1099 .resume = i915_resume,
1100
1101 .device_is_agp = i915_driver_device_is_agp,
1102 .master_create = i915_master_create,
1103 .master_destroy = i915_master_destroy,
1104#if defined(CONFIG_DEBUG_FS)
1105 .debugfs_init = i915_debugfs_init,
1106 .debugfs_cleanup = i915_debugfs_cleanup,
1107#endif
1108 .gem_init_object = i915_gem_init_object,
1109 .gem_free_object = i915_gem_free_object,
1110#if defined(__linux__)
1111 .gem_vm_ops = &i915_gem_vm_ops,
1112#elif defined(__FreeBSD__)
1113 .gem_pager_ops = &i915_gem_pager_ops,
1114#endif
1115
1116#ifdef FREEBSD_WIP
1117 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1118 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1119 .gem_prime_export = i915_gem_prime_export,
1120 .gem_prime_import = i915_gem_prime_import,
1121#endif /* FREEBSD_WIP */
1122
1123 .dumb_create = i915_gem_dumb_create,
1124 .dumb_map_offset = i915_gem_mmap_gtt,
1125 .dumb_destroy = i915_gem_dumb_destroy,
1126 .ioctls = i915_ioctls,
1127#ifdef COMPAT_FREEBSD32
1128 .compat_ioctls = i915_compat_ioctls,
1129 .num_compat_ioctls = &i915_compat_ioctls_nr,
1130#endif
1131#ifdef __linux__
1132 .fops = &i915_driver_fops,
1133#endif
1134#ifdef __FreeBSD__
1135 .sysctl_init = i915_sysctl_init,
1136 .sysctl_cleanup = i915_sysctl_cleanup,
1137#endif
1138 .name = DRIVER_NAME,
1139 .desc = DRIVER_DESC,
1140 .date = DRIVER_DATE,
1141 .major = DRIVER_MAJOR,
1142 .minor = DRIVER_MINOR,
1143 .patchlevel = DRIVER_PATCHLEVEL,
1144};
1145
1146#ifdef __linux__
1147static struct pci_driver i915_pci_driver = {
1148 .name = DRIVER_NAME,
1149 .id_table = pciidlist,
1150 .probe = i915_pci_probe,
1151 .remove = i915_pci_remove,
1152 .driver.pm = &i915_pm_ops,
1153};
1154#endif
1155
1156static int __init i915_attach(device_t kdev)
1157{
1158 driver.num_ioctls = i915_max_ioctl;
1159
1160 /*
1161 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1162 * explicitly disabled with the module pararmeter.
1163 *
1164 * Otherwise, just follow the parameter (defaulting to off).
1165 *
1166 * Allow optional vga_text_mode_force boot option to override
1167 * the default behavior.
1168 */
1169#if defined(CONFIG_DRM_I915_KMS)
1170 if (i915_modeset != 0)
1171 driver.driver_features |= DRIVER_MODESET;
1172#endif
815 if (i915_modeset == 1)
1173 if (i915_modeset == 1)
816 i915_driver_info.driver_features |= DRIVER_MODESET;
817 return (-drm_attach_helper(kdev, i915_pciidlist, &i915_driver_info));
1174 driver.driver_features |= DRIVER_MODESET;
1175
1176#ifdef CONFIG_VGA_CONSOLE
1177 if (vgacon_text_force() && i915_modeset == -1)
1178 driver.driver_features &= ~DRIVER_MODESET;
1179#endif
1180
1181 if (!(driver.driver_features & DRIVER_MODESET))
1182 driver.get_vblank_timestamp = NULL;
1183
1184 return (-drm_attach_helper(kdev, pciidlist, &driver));
818}
819
820static struct fb_info *
821i915_fb_helper_getinfo(device_t kdev)
822{
823 struct intel_fbdev *ifbdev;
824 drm_i915_private_t *dev_priv;
825 struct drm_device *dev;

--- 9 unchanged lines hidden (view full) ---

835
836 return (info);
837}
838
839static device_method_t i915_methods[] = {
840 /* Device interface */
841 DEVMETHOD(device_probe, i915_probe),
842 DEVMETHOD(device_attach, i915_attach),
1185}
1186
1187static struct fb_info *
1188i915_fb_helper_getinfo(device_t kdev)
1189{
1190 struct intel_fbdev *ifbdev;
1191 drm_i915_private_t *dev_priv;
1192 struct drm_device *dev;

--- 9 unchanged lines hidden (view full) ---

1202
1203 return (info);
1204}
1205
1206static device_method_t i915_methods[] = {
1207 /* Device interface */
1208 DEVMETHOD(device_probe, i915_probe),
1209 DEVMETHOD(device_attach, i915_attach),
843 DEVMETHOD(device_suspend, i915_suspend),
844 DEVMETHOD(device_resume, i915_resume),
1210 DEVMETHOD(device_suspend, drm_generic_suspend),
1211 DEVMETHOD(device_resume, drm_generic_resume),
845 DEVMETHOD(device_detach, drm_generic_detach),
846
847 /* Framebuffer service methods */
848 DEVMETHOD(fb_getinfo, i915_fb_helper_getinfo),
849
850 DEVMETHOD_END
851};
852
853static driver_t i915_driver = {
854 "drmn",
855 i915_methods,
856 sizeof(struct drm_device)
857};
858
1212 DEVMETHOD(device_detach, drm_generic_detach),
1213
1214 /* Framebuffer service methods */
1215 DEVMETHOD(fb_getinfo, i915_fb_helper_getinfo),
1216
1217 DEVMETHOD_END
1218};
1219
1220static driver_t i915_driver = {
1221 "drmn",
1222 i915_methods,
1223 sizeof(struct drm_device)
1224};
1225
1226MODULE_AUTHOR(DRIVER_AUTHOR);
1227MODULE_DESCRIPTION(DRIVER_DESC);
1228MODULE_LICENSE("GPL and additional rights");
1229
859extern devclass_t drm_devclass;
860DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
861 SI_ORDER_ANY);
862MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
863MODULE_DEPEND(i915kms, agp, 1, 1, 1);
864MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
865MODULE_DEPEND(i915kms, iic, 1, 1, 1);
866MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
867
868/* We give fast paths for the really cool registers */
869#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1230extern devclass_t drm_devclass;
1231DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
1232 SI_ORDER_ANY);
1233MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
1234MODULE_DEPEND(i915kms, agp, 1, 1, 1);
1235MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
1236MODULE_DEPEND(i915kms, iic, 1, 1, 1);
1237MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
1238
1239/* We give fast paths for the really cool registers */
1240#define NEEDS_FORCE_WAKE(dev_priv, reg) \
870 (((dev_priv)->info->gen >= 6) && \
1241 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
871 ((reg) < 0x40000) && \
1242 ((reg) < 0x40000) && \
872 ((reg) != FORCEWAKE)) && \
873 (!IS_VALLEYVIEW((dev_priv)->dev))
1243 ((reg) != FORCEWAKE))
874
1244
875void
876__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
1245static bool IS_DISPLAYREG(u32 reg)
877{
1246{
878 int count;
1247 /*
1248 * This should make it easier to transition modules over to the
1249 * new register block scheme, since we can do it incrementally.
1250 */
1251 if (reg >= VLV_DISPLAY_BASE)
1252 return false;
879
1253
880 count = 0;
881 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
882 DELAY(10);
1254 if (reg >= RENDER_RING_BASE &&
1255 reg < RENDER_RING_BASE + 0xff)
1256 return false;
1257 if (reg >= GEN6_BSD_RING_BASE &&
1258 reg < GEN6_BSD_RING_BASE + 0xff)
1259 return false;
1260 if (reg >= BLT_RING_BASE &&
1261 reg < BLT_RING_BASE + 0xff)
1262 return false;
883
1263
884 I915_WRITE_NOTRACE(FORCEWAKE, 1);
885 POSTING_READ(FORCEWAKE);
1264 if (reg == PGTBL_ER)
1265 return false;
886
1266
887 count = 0;
888 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
889 DELAY(10);
890}
1267 if (reg >= IPEIR_I965 &&
1268 reg < HWSTAM)
1269 return false;
891
1270
892void
893__gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
894{
895 int count;
1271 if (reg == MI_MODE)
1272 return false;
896
1273
897 count = 0;
898 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
899 DELAY(10);
1274 if (reg == GFX_MODE_GEN7)
1275 return false;
900
1276
901 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
902 POSTING_READ(FORCEWAKE_MT);
1277 if (reg == RENDER_HWS_PGA_GEN7 ||
1278 reg == BSD_HWS_PGA_GEN7 ||
1279 reg == BLT_HWS_PGA_GEN7)
1280 return false;
903
1281
904 count = 0;
905 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
906 DELAY(10);
907}
1282 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1283 reg == GEN6_BSD_RNCID)
1284 return false;
908
1285
909void
910gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
911{
1286 if (reg == GEN6_BLITTER_ECOSKPD)
1287 return false;
912
1288
913 mtx_lock(&dev_priv->gt_lock);
914 if (dev_priv->forcewake_count++ == 0)
915 dev_priv->display.force_wake_get(dev_priv);
916 mtx_unlock(&dev_priv->gt_lock);
917}
1289 if (reg >= 0x4000c &&
1290 reg <= 0x4002c)
1291 return false;
918
1292
919static void
920gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
921{
922 u32 gtfifodbg;
1293 if (reg >= 0x4f000 &&
1294 reg <= 0x4f08f)
1295 return false;
923
1296
924 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
925 if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
926 printf("MMIO read or write has been dropped %x\n", gtfifodbg);
927 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
928 }
929}
1297 if (reg >= 0x4f100 &&
1298 reg <= 0x4f11f)
1299 return false;
930
1300
931void
932__gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
933{
1301 if (reg >= VLV_MASTER_IER &&
1302 reg <= GEN6_PMIER)
1303 return false;
934
1304
935 I915_WRITE_NOTRACE(FORCEWAKE, 0);
936 /* The below doubles as a POSTING_READ */
937 gen6_gt_check_fifodbg(dev_priv);
938}
1305 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1306 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1307 return false;
939
1308
940void
941__gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
942{
1309 if (reg >= VLV_IIR_RW &&
1310 reg <= VLV_ISR)
1311 return false;
943
1312
944 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
945 /* The below doubles as a POSTING_READ */
946 gen6_gt_check_fifodbg(dev_priv);
947}
1313 if (reg == FORCEWAKE_VLV ||
1314 reg == FORCEWAKE_ACK_VLV)
1315 return false;
948
1316
949void
950gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
951{
1317 if (reg == GEN6_GDRST)
1318 return false;
952
1319
953 mtx_lock(&dev_priv->gt_lock);
954 if (--dev_priv->forcewake_count == 0)
955 dev_priv->display.force_wake_put(dev_priv);
956 mtx_unlock(&dev_priv->gt_lock);
957}
958
959int
960__gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
961{
962 int ret = 0;
963
964 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
965 int loop = 500;
966 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
967 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
968 DELAY(10);
969 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
970 }
971 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
972 printf("%s loop\n", __func__);
973 ++ret;
974 }
975 dev_priv->gt_fifo_count = fifo;
1320 switch (reg) {
1321 case _3D_CHICKEN3:
1322 case IVB_CHICKEN3:
1323 case GEN7_COMMON_SLICE_CHICKEN1:
1324 case GEN7_L3CNTLREG1:
1325 case GEN7_L3_CHICKEN_MODE_REGISTER:
1326 case GEN7_ROW_CHICKEN2:
1327 case GEN7_L3SQCREG4:
1328 case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
1329 case GEN7_HALF_SLICE_CHICKEN1:
1330 case GEN6_MBCTL:
1331 case GEN6_UCGCTL2:
1332 return false;
1333 default:
1334 break;
976 }
1335 }
977 dev_priv->gt_fifo_count--;
978
1336
979 return (ret);
1337 return true;
980}
981
1338}
1339
982void vlv_force_wake_get(struct drm_i915_private *dev_priv)
1340static void
1341ilk_dummy_write(struct drm_i915_private *dev_priv)
983{
1342{
984 int count;
985
986 count = 0;
987
988 /* Already awake? */
989 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
990 return;
991
992 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
993 POSTING_READ(FORCEWAKE_VLV);
994
995 count = 0;
996 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
997 DELAY(10);
1343 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1344 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1345 * harmless to write 0 into. */
1346 I915_WRITE_NOTRACE(MI_MODE, 0);
998}
999
1347}
1348
1000void vlv_force_wake_put(struct drm_i915_private *dev_priv)
1001{
1002 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
1003 /* FIXME: confirm VLV behavior with Punit folks */
1004 POSTING_READ(FORCEWAKE_VLV);
1005}
1006
1007#define __i915_read(x, y) \
1008u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1009 u##x val = 0; \
1349#define __i915_read(x, y) \
1350u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1351 u##x val = 0; \
1352 if (IS_GEN5(dev_priv->dev)) \
1353 ilk_dummy_write(dev_priv); \
1010 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1011 mtx_lock(&dev_priv->gt_lock); \
1012 if (dev_priv->forcewake_count == 0) \
1354 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1355 mtx_lock(&dev_priv->gt_lock); \
1356 if (dev_priv->forcewake_count == 0) \
1013 dev_priv->display.force_wake_get(dev_priv); \
1357 dev_priv->gt.force_wake_get(dev_priv); \
1014 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1015 if (dev_priv->forcewake_count == 0) \
1358 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1359 if (dev_priv->forcewake_count == 0) \
1016 dev_priv->display.force_wake_put(dev_priv); \
1360 dev_priv->gt.force_wake_put(dev_priv); \
1017 mtx_unlock(&dev_priv->gt_lock); \
1361 mtx_unlock(&dev_priv->gt_lock); \
1362 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1363 val = DRM_READ##x(dev_priv->mmio_map, reg + 0x180000); \
1018 } else { \
1019 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1020 } \
1021 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1022 return val; \
1023}
1024
1364 } else { \
1365 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1366 } \
1367 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1368 return val; \
1369}
1370
1025__i915_read(8, 8)
1026__i915_read(16, 16)
1027__i915_read(32, 32)
1028__i915_read(64, 64)
1371__i915_read(8, b)
1372__i915_read(16, w)
1373__i915_read(32, l)
1374__i915_read(64, q)
1029#undef __i915_read
1030
1031#define __i915_write(x, y) \
1032void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1033 u32 __fifo_ret = 0; \
1034 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1035 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1036 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1037 } \
1375#undef __i915_read
1376
1377#define __i915_write(x, y) \
1378void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1379 u32 __fifo_ret = 0; \
1380 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1381 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1382 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1383 } \
1038 DRM_WRITE##x(dev_priv->mmio_map, reg, val); \
1039 if (__predict_false(__fifo_ret)) { \
1384 if (IS_GEN5(dev_priv->dev)) \
1385 ilk_dummy_write(dev_priv); \
1386 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1387 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1388 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1389 } \
1390 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1391 DRM_WRITE##x(dev_priv->mmio_map, reg + 0x180000, val); \
1392 } else { \
1393 DRM_WRITE##x(dev_priv->mmio_map, reg, val); \
1394 } \
1395 if (unlikely(__fifo_ret)) { \
1040 gen6_gt_check_fifodbg(dev_priv); \
1041 } \
1396 gen6_gt_check_fifodbg(dev_priv); \
1397 } \
1398 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1399 DRM_ERROR("Unclaimed write to %x\n", reg); \
1400 DRM_WRITE32(dev_priv->mmio_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1401 } \
1042}
1402}
1043__i915_write(8, 8)
1044__i915_write(16, 16)
1045__i915_write(32, 32)
1046__i915_write(64, 64)
1403__i915_write(8, b)
1404__i915_write(16, w)
1405__i915_write(32, l)
1406__i915_write(64, q)
1047#undef __i915_write
1407#undef __i915_write
1408
1409static const struct register_whitelist {
1410 uint64_t offset;
1411 uint32_t size;
1412 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1413} whitelist[] = {
1414 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1415};
1416
1417int i915_reg_read_ioctl(struct drm_device *dev,
1418 void *data, struct drm_file *file)
1419{
1420 struct drm_i915_private *dev_priv = dev->dev_private;
1421 struct drm_i915_reg_read *reg = data;
1422 struct register_whitelist const *entry = whitelist;
1423 int i;
1424
1425 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1426 if (entry->offset == reg->offset &&
1427 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1428 break;
1429 }
1430
1431 if (i == ARRAY_SIZE(whitelist))
1432 return -EINVAL;
1433
1434 switch (entry->size) {
1435 case 8:
1436 reg->val = I915_READ64(reg->offset);
1437 break;
1438 case 4:
1439 reg->val = I915_READ(reg->offset);
1440 break;
1441 case 2:
1442 reg->val = I915_READ16(reg->offset);
1443 break;
1444 case 1:
1445 reg->val = I915_READ8(reg->offset);
1446 break;
1447 default:
1448 WARN_ON(1);
1449 return -EINVAL;
1450 }
1451
1452 return 0;
1453}