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i915_drv.c (288952) i915_drv.c (290070)
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 16 unchanged lines hidden (view full) ---

25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32#include <sys/cdefs.h>
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 16 unchanged lines hidden (view full) ---

25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 288952 2015-10-06 20:58:45Z adrian $");
33__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 290070 2015-10-27 21:23:19Z dumbbell $");
34
35#include <dev/drm2/drmP.h>
36#include <dev/drm2/drm.h>
37#include <dev/drm2/drm_mm.h>
38#include <dev/drm2/i915/i915_drm.h>
39#include <dev/drm2/i915/i915_drv.h>
40#include <dev/drm2/drm_pciids.h>
41#include <dev/drm2/i915/intel_drv.h>
42
43#include "fb_if.h"
44
34
35#include <dev/drm2/drmP.h>
36#include <dev/drm2/drm.h>
37#include <dev/drm2/drm_mm.h>
38#include <dev/drm2/i915/i915_drm.h>
39#include <dev/drm2/i915/i915_drv.h>
40#include <dev/drm2/drm_pciids.h>
41#include <dev/drm2/i915/intel_drv.h>
42
43#include "fb_if.h"
44
45int intel_iommu_enabled = 0;
46TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
47int intel_iommu_gfx_mapped = 0;
48TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
49
50int i915_prefault_disable;
51TUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable);
52int i915_semaphores = -1;
53TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
54static int i915_try_reset = 1;
55TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
56unsigned int i915_lvds_downclock = 0;
57TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
58int i915_vbt_sdvo_panel_type = -1;
59TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
60unsigned int i915_powersave = 1;
61TUNABLE_INT("drm.i915.powersave", &i915_powersave);
62int i915_enable_fbc = 0;
63TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
64int i915_enable_rc6 = 0;
65TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
66int i915_lvds_channel_mode;
67TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
68int i915_panel_use_ssc = -1;
69TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
70int i915_panel_ignore_lid = 0;
71TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
72int i915_panel_invert_brightness;
73TUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness);
74int i915_modeset = 1;
75TUNABLE_INT("drm.i915.modeset", &i915_modeset);
76int i915_enable_ppgtt = -1;
77TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
78int i915_enable_hangcheck = 1;
79TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
80static int i915_enable_unsupported = 0;
81TUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported);
82
45/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
46static drm_pci_id_list_t i915_pciidlist[] = {
47 i915_PCI_IDS
48};
49
50#define INTEL_VGA_DEVICE(id, info_) { \
51 .device = id, \
52 .info = info_, \

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224 .has_llc = 1,
225 .has_pch_split = 1,
226 .not_supported = 1,
227};
228
229static const struct intel_gfx_device_id {
230 int device;
231 const struct intel_device_info *info;
83/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
84static drm_pci_id_list_t i915_pciidlist[] = {
85 i915_PCI_IDS
86};
87
88#define INTEL_VGA_DEVICE(id, info_) { \
89 .device = id, \
90 .info = info_, \

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262 .has_llc = 1,
263 .has_pch_split = 1,
264 .not_supported = 1,
265};
266
267static const struct intel_gfx_device_id {
268 int device;
269 const struct intel_device_info *info;
232} pciidlist[] = { /* aka */
270} i915_infolist[] = { /* aka */
233 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
234 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
235 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
236 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
237 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
238 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
239 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
240 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */

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311 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
312 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
313 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
314 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
315 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
316 {0, 0}
317};
318
271 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
272 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
273 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
274 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
275 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
276 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
277 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
278 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */

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349 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
350 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
351 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
352 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
353 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
354 {0, 0}
355};
356
319static int i915_enable_unsupported;
357#define PCI_VENDOR_INTEL 0x8086
358#define INTEL_PCH_DEVICE_ID_MASK 0xff00
359#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
360#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
361#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
362#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
320
363
364void intel_detect_pch(struct drm_device *dev)
365{
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 device_t pch;
368 uint32_t id;
369
370 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
371 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
372 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
373 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
374 dev_priv->pch_type = PCH_IBX;
375 dev_priv->num_pch_pll = 2;
376 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
377 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
378 dev_priv->pch_type = PCH_CPT;
379 dev_priv->num_pch_pll = 2;
380 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
381 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
382 /* PantherPoint is CPT compatible */
383 dev_priv->pch_type = PCH_CPT;
384 dev_priv->num_pch_pll = 2;
385 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
386 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
387 dev_priv->pch_type = PCH_LPT;
388 dev_priv->num_pch_pll = 0;
389 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
390 } else
391 DRM_DEBUG_KMS("No PCH detected\n");
392 KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
393 ("num_pch_pll %d\n", dev_priv->num_pch_pll));
394 } else
395 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
396}
397
398bool i915_semaphore_is_enabled(struct drm_device *dev)
399{
400 if (INTEL_INFO(dev)->gen < 6)
401 return 0;
402
403 if (i915_semaphores >= 0)
404 return i915_semaphores;
405
406 /* Enable semaphores on SNB when IO remapping is off */
407 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
408 return false;
409
410 return 1;
411}
412
321static int i915_drm_freeze(struct drm_device *dev)
322{
323 struct drm_i915_private *dev_priv = dev->dev_private;
324
325 drm_kms_helper_poll_disable(dev);
326
327#if 0
328 pci_save_state(dev->pdev);

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350}
351
352static int i915_suspend(device_t kdev)
353{
354 struct drm_device *dev;
355 int error;
356
357 dev = device_get_softc(kdev);
413static int i915_drm_freeze(struct drm_device *dev)
414{
415 struct drm_i915_private *dev_priv = dev->dev_private;
416
417 drm_kms_helper_poll_disable(dev);
418
419#if 0
420 pci_save_state(dev->pdev);

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442}
443
444static int i915_suspend(device_t kdev)
445{
446 struct drm_device *dev;
447 int error;
448
449 dev = device_get_softc(kdev);
358 if (dev == NULL || dev->dev_private == NULL) {
450 if (!dev || !dev->dev_private) {
359 DRM_ERROR("DRM not initialized, aborting suspend.\n");
360 return ENODEV;
361 }
362
363 DRM_DEBUG_KMS("starting suspend\n");
364 error = i915_drm_freeze(dev);
365 if (error)
451 DRM_ERROR("DRM not initialized, aborting suspend.\n");
452 return ENODEV;
453 }
454
455 DRM_DEBUG_KMS("starting suspend\n");
456 error = i915_drm_freeze(dev);
457 if (error)
366 return (-error);
458 return -error;
367
368 error = bus_generic_suspend(kdev);
369 DRM_DEBUG_KMS("finished suspend %d\n", error);
370 return (error);
371}
372
373static int i915_drm_thaw(struct drm_device *dev)
374{

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424#if 0
425 if (pci_enable_device(dev->pdev))
426 return -EIO;
427
428 pci_set_master(dev->pdev);
429#endif
430
431 ret = i915_drm_thaw(dev);
459
460 error = bus_generic_suspend(kdev);
461 DRM_DEBUG_KMS("finished suspend %d\n", error);
462 return (error);
463}
464
465static int i915_drm_thaw(struct drm_device *dev)
466{

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516#if 0
517 if (pci_enable_device(dev->pdev))
518 return -EIO;
519
520 pci_set_master(dev->pdev);
521#endif
522
523 ret = i915_drm_thaw(dev);
432 if (ret != 0)
433 return (-ret);
524 if (ret)
525 return -ret;
434
435 drm_kms_helper_poll_enable(dev);
436 ret = bus_generic_resume(kdev);
437 DRM_DEBUG_KMS("finished resume %d\n", ret);
438 return (ret);
439}
440
526
527 drm_kms_helper_poll_enable(dev);
528 ret = bus_generic_resume(kdev);
529 DRM_DEBUG_KMS("finished resume %d\n", ret);
530 return (ret);
531}
532
441static int
442i915_probe(device_t kdev)
443{
444 const struct intel_device_info *info;
445 int error;
446
447 error = drm_probe_helper(kdev, i915_pciidlist);
448 if (error != 0)
449 return (-error);
450 info = i915_get_device_id(pci_get_device(kdev));
451 if (info == NULL)
452 return (ENXIO);
453 return (0);
454}
455
456int i915_modeset;
457
458static int
459i915_attach(device_t kdev)
460{
461
462 if (i915_modeset == 1)
463 i915_driver_info.driver_features |= DRIVER_MODESET;
464 return (-drm_attach_helper(kdev, i915_pciidlist, &i915_driver_info));
465}
466
467static struct fb_info *
468i915_fb_helper_getinfo(device_t kdev)
469{
470 struct intel_fbdev *ifbdev;
471 drm_i915_private_t *dev_priv;
472 struct drm_device *dev;
473 struct fb_info *info;
474
475 dev = device_get_softc(kdev);
476 dev_priv = dev->dev_private;
477 ifbdev = dev_priv->fbdev;
478 if (ifbdev == NULL)
479 return (NULL);
480
481 info = ifbdev->helper.fbdev;
482
483 return (info);
484}
485
486const struct intel_device_info *
487i915_get_device_id(int device)
488{
489 const struct intel_gfx_device_id *did;
490
491 for (did = &pciidlist[0]; did->device != 0; did++) {
492 if (did->device != device)
493 continue;
494 if (did->info->not_supported && !i915_enable_unsupported)
495 return (NULL);
496 return (did->info);
497 }
498 return (NULL);
499}
500
501static device_method_t i915_methods[] = {
502 /* Device interface */
503 DEVMETHOD(device_probe, i915_probe),
504 DEVMETHOD(device_attach, i915_attach),
505 DEVMETHOD(device_suspend, i915_suspend),
506 DEVMETHOD(device_resume, i915_resume),
507 DEVMETHOD(device_detach, drm_generic_detach),
508
509 /* Framebuffer service methods */
510 DEVMETHOD(fb_getinfo, i915_fb_helper_getinfo),
511
512 DEVMETHOD_END
513};
514
515static driver_t i915_driver = {
516 "drmn",
517 i915_methods,
518 sizeof(struct drm_device)
519};
520
521extern devclass_t drm_devclass;
522DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
523 SI_ORDER_ANY);
524MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
525MODULE_DEPEND(i915kms, agp, 1, 1, 1);
526MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
527MODULE_DEPEND(i915kms, iic, 1, 1, 1);
528MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
529
530int intel_iommu_enabled = 0;
531TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
532int intel_iommu_gfx_mapped = 0;
533TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
534
535int i915_prefault_disable;
536TUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable);
537int i915_semaphores = -1;
538TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
539static int i915_try_reset = 1;
540TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
541unsigned int i915_lvds_downclock = 0;
542TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
543int i915_vbt_sdvo_panel_type = -1;
544TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
545unsigned int i915_powersave = 1;
546TUNABLE_INT("drm.i915.powersave", &i915_powersave);
547int i915_enable_fbc = 0;
548TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
549int i915_enable_rc6 = 0;
550TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
551int i915_lvds_channel_mode;
552TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
553int i915_panel_use_ssc = -1;
554TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
555int i915_panel_ignore_lid = 0;
556TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
557int i915_panel_invert_brightness;
558TUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness);
559int i915_modeset = 1;
560TUNABLE_INT("drm.i915.modeset", &i915_modeset);
561int i915_enable_ppgtt = -1;
562TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
563int i915_enable_hangcheck = 1;
564TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
565TUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported);
566
567#define PCI_VENDOR_INTEL 0x8086
568#define INTEL_PCH_DEVICE_ID_MASK 0xff00
569#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
570#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
571#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
572#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
573
574void intel_detect_pch(struct drm_device *dev)
575{
576 struct drm_i915_private *dev_priv;
577 device_t pch;
578 uint32_t id;
579
580 dev_priv = dev->dev_private;
581 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
582 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
583 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
584 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
585 dev_priv->pch_type = PCH_IBX;
586 dev_priv->num_pch_pll = 2;
587 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
588 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
589 dev_priv->pch_type = PCH_CPT;
590 dev_priv->num_pch_pll = 2;
591 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
592 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
593 /* PantherPoint is CPT compatible */
594 dev_priv->pch_type = PCH_CPT;
595 dev_priv->num_pch_pll = 2;
596 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
597 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
598 dev_priv->pch_type = PCH_LPT;
599 dev_priv->num_pch_pll = 0;
600 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
601 } else
602 DRM_DEBUG_KMS("No PCH detected\n");
603 KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
604 ("num_pch_pll %d\n", dev_priv->num_pch_pll));
605 } else
606 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
607}
608
609bool i915_semaphore_is_enabled(struct drm_device *dev)
610{
611 if (INTEL_INFO(dev)->gen < 6)
612 return 0;
613
614 if (i915_semaphores >= 0)
615 return i915_semaphores;
616
617 /* Enable semaphores on SNB when IO remapping is off */
618 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
619 return false;
620
621 return 1;
622}
623
624void
625__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
626{
627 int count;
628
629 count = 0;
630 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
631 DELAY(10);
632
633 I915_WRITE_NOTRACE(FORCEWAKE, 1);
634 POSTING_READ(FORCEWAKE);
635
636 count = 0;
637 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
638 DELAY(10);
639}
640
641void
642__gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
643{
644 int count;
645
646 count = 0;
647 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
648 DELAY(10);
649
650 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
651 POSTING_READ(FORCEWAKE_MT);
652
653 count = 0;
654 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
655 DELAY(10);
656}
657
658void
659gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
660{
661
662 mtx_lock(&dev_priv->gt_lock);
663 if (dev_priv->forcewake_count++ == 0)
664 dev_priv->display.force_wake_get(dev_priv);
665 mtx_unlock(&dev_priv->gt_lock);
666}
667
668static void
669gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
670{
671 u32 gtfifodbg;
672
673 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
674 if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
675 printf("MMIO read or write has been dropped %x\n", gtfifodbg);
676 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
677 }
678}
679
680void
681__gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
682{
683
684 I915_WRITE_NOTRACE(FORCEWAKE, 0);
685 /* The below doubles as a POSTING_READ */
686 gen6_gt_check_fifodbg(dev_priv);
687}
688
689void
690__gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
691{
692
693 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
694 /* The below doubles as a POSTING_READ */
695 gen6_gt_check_fifodbg(dev_priv);
696}
697
698void
699gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
700{
701
702 mtx_lock(&dev_priv->gt_lock);
703 if (--dev_priv->forcewake_count == 0)
704 dev_priv->display.force_wake_put(dev_priv);
705 mtx_unlock(&dev_priv->gt_lock);
706}
707
708int
709__gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
710{
711 int ret = 0;
712
713 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
714 int loop = 500;
715 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
716 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
717 DELAY(10);
718 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
719 }
720 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
721 printf("%s loop\n", __func__);
722 ++ret;
723 }
724 dev_priv->gt_fifo_count = fifo;
725 }
726 dev_priv->gt_fifo_count--;
727
728 return (ret);
729}
730
731void vlv_force_wake_get(struct drm_i915_private *dev_priv)
732{
733 int count;
734
735 count = 0;
736
737 /* Already awake? */
738 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
739 return;
740
741 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
742 POSTING_READ(FORCEWAKE_VLV);
743
744 count = 0;
745 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
746 DELAY(10);
747}
748
749void vlv_force_wake_put(struct drm_i915_private *dev_priv)
750{
751 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
752 /* FIXME: confirm VLV behavior with Punit folks */
753 POSTING_READ(FORCEWAKE_VLV);
754}
755
756static int i8xx_do_reset(struct drm_device *dev)
757{
758 struct drm_i915_private *dev_priv = dev->dev_private;
759 int onems;
760
761 if (IS_I85X(dev))
762 return -ENODEV;
763

--- 39 unchanged lines hidden (view full) ---

803
804 /*
805 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
806 * well as the reset bit (GR/bit 0). Setting the GR bit
807 * triggers the reset; when done, the hardware will clear it.
808 */
809 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
810 pci_write_config(dev->dev, I965_GDRST,
533static int i8xx_do_reset(struct drm_device *dev)
534{
535 struct drm_i915_private *dev_priv = dev->dev_private;
536 int onems;
537
538 if (IS_I85X(dev))
539 return -ENODEV;
540

--- 39 unchanged lines hidden (view full) ---

580
581 /*
582 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
583 * well as the reset bit (GR/bit 0). Setting the GR bit
584 * triggers the reset; when done, the hardware will clear it.
585 */
586 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
587 pci_write_config(dev->dev, I965_GDRST,
811 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE, 1);
812
588 gdrst | GRDOM_RENDER |
589 GRDOM_RESET_ENABLE, 1);
813 ret = wait_for(i965_reset_complete(dev), 500);
814 if (ret)
815 return ret;
816
817 /* We can't reset render&media without also resetting display ... */
818 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
819 pci_write_config(dev->dev, I965_GDRST,
590 ret = wait_for(i965_reset_complete(dev), 500);
591 if (ret)
592 return ret;
593
594 /* We can't reset render&media without also resetting display ... */
595 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
596 pci_write_config(dev->dev, I965_GDRST,
820 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE, 1);
597 gdrst | GRDOM_MEDIA |
598 GRDOM_RESET_ENABLE, 1);
821
822 return wait_for(i965_reset_complete(dev), 500);
823}
824
825static int ironlake_do_reset(struct drm_device *dev)
826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 u32 gdrst;

--- 32 unchanged lines hidden (view full) ---

861 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
862
863 /* Spin waiting for the device to ack the reset request */
864 ret = _intel_wait_for(dev,
865 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
866 500, 0, "915rst");
867
868 /* If reset with a user forcewake, try to restore, otherwise turn it off */
599
600 return wait_for(i965_reset_complete(dev), 500);
601}
602
603static int ironlake_do_reset(struct drm_device *dev)
604{
605 struct drm_i915_private *dev_priv = dev->dev_private;
606 u32 gdrst;

--- 32 unchanged lines hidden (view full) ---

639 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
640
641 /* Spin waiting for the device to ack the reset request */
642 ret = _intel_wait_for(dev,
643 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
644 500, 0, "915rst");
645
646 /* If reset with a user forcewake, try to restore, otherwise turn it off */
869 if (dev_priv->forcewake_count)
870 dev_priv->display.force_wake_get(dev_priv);
647 if (dev_priv->forcewake_count)
648 dev_priv->display.force_wake_get(dev_priv);
871 else
872 dev_priv->display.force_wake_put(dev_priv);
873
874 /* Restore fifo count */
875 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
876
877 mtx_unlock(&dev_priv->gt_lock);
649 else
650 dev_priv->display.force_wake_put(dev_priv);
651
652 /* Restore fifo count */
653 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
654
655 mtx_unlock(&dev_priv->gt_lock);
878 return (ret);
656 return ret;
879}
880
881int intel_gpu_reset(struct drm_device *dev)
882{
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 int ret = -ENODEV;
885
886 switch (INTEL_INFO(dev)->gen) {

--- 98 unchanged lines hidden (view full) ---

985 i915_gem_context_init(dev);
986 i915_gem_init_ppgtt(dev);
987
988 /*
989 * It would make sense to re-init all the other hw state, at
990 * least the rps/rc6/emon init done within modeset_init_hw. For
991 * some unknown reason, this blows up my ilk, so don't.
992 */
657}
658
659int intel_gpu_reset(struct drm_device *dev)
660{
661 struct drm_i915_private *dev_priv = dev->dev_private;
662 int ret = -ENODEV;
663
664 switch (INTEL_INFO(dev)->gen) {

--- 98 unchanged lines hidden (view full) ---

763 i915_gem_context_init(dev);
764 i915_gem_init_ppgtt(dev);
765
766 /*
767 * It would make sense to re-init all the other hw state, at
768 * least the rps/rc6/emon init done within modeset_init_hw. For
769 * some unknown reason, this blows up my ilk, so don't.
770 */
771
993 DRM_UNLOCK(dev);
994
995 if (drm_core_check_feature(dev, DRIVER_MODESET))
996 intel_modeset_init_hw(dev);
997
998 drm_irq_uninstall(dev);
999 drm_irq_install(dev);
1000 } else {
1001 DRM_UNLOCK(dev);
1002 }
1003
1004 return 0;
1005}
1006
772 DRM_UNLOCK(dev);
773
774 if (drm_core_check_feature(dev, DRIVER_MODESET))
775 intel_modeset_init_hw(dev);
776
777 drm_irq_uninstall(dev);
778 drm_irq_install(dev);
779 } else {
780 DRM_UNLOCK(dev);
781 }
782
783 return 0;
784}
785
786const struct intel_device_info *
787i915_get_device_id(int device)
788{
789 const struct intel_gfx_device_id *did;
790
791 for (did = &i915_infolist[0]; did->device != 0; did++) {
792 if (did->device != device)
793 continue;
794 if (did->info->not_supported && !i915_enable_unsupported)
795 return (NULL);
796 return (did->info);
797 }
798 return (NULL);
799}
800
801static int i915_probe(device_t kdev)
802{
803 const struct intel_device_info *intel_info =
804 i915_get_device_id(pci_get_device(kdev));
805
806 if (intel_info == NULL)
807 return (ENXIO);
808
809 return -drm_probe_helper(kdev, i915_pciidlist);
810}
811
812static int i915_attach(device_t kdev)
813{
814
815 if (i915_modeset == 1)
816 i915_driver_info.driver_features |= DRIVER_MODESET;
817 return (-drm_attach_helper(kdev, i915_pciidlist, &i915_driver_info));
818}
819
820static struct fb_info *
821i915_fb_helper_getinfo(device_t kdev)
822{
823 struct intel_fbdev *ifbdev;
824 drm_i915_private_t *dev_priv;
825 struct drm_device *dev;
826 struct fb_info *info;
827
828 dev = device_get_softc(kdev);
829 dev_priv = dev->dev_private;
830 ifbdev = dev_priv->fbdev;
831 if (ifbdev == NULL)
832 return (NULL);
833
834 info = ifbdev->helper.fbdev;
835
836 return (info);
837}
838
839static device_method_t i915_methods[] = {
840 /* Device interface */
841 DEVMETHOD(device_probe, i915_probe),
842 DEVMETHOD(device_attach, i915_attach),
843 DEVMETHOD(device_suspend, i915_suspend),
844 DEVMETHOD(device_resume, i915_resume),
845 DEVMETHOD(device_detach, drm_generic_detach),
846
847 /* Framebuffer service methods */
848 DEVMETHOD(fb_getinfo, i915_fb_helper_getinfo),
849
850 DEVMETHOD_END
851};
852
853static driver_t i915_driver = {
854 "drmn",
855 i915_methods,
856 sizeof(struct drm_device)
857};
858
859extern devclass_t drm_devclass;
860DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
861 SI_ORDER_ANY);
862MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
863MODULE_DEPEND(i915kms, agp, 1, 1, 1);
864MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
865MODULE_DEPEND(i915kms, iic, 1, 1, 1);
866MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
867
1007/* We give fast paths for the really cool registers */
1008#define NEEDS_FORCE_WAKE(dev_priv, reg) \
868/* We give fast paths for the really cool registers */
869#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1009 (((dev_priv)->info->gen >= 6) && \
1010 ((reg) < 0x40000) && \
1011 ((reg) != FORCEWAKE)) && \
1012 (!IS_VALLEYVIEW((dev_priv)->dev))
870 (((dev_priv)->info->gen >= 6) && \
871 ((reg) < 0x40000) && \
872 ((reg) != FORCEWAKE)) && \
873 (!IS_VALLEYVIEW((dev_priv)->dev))
1013
874
875void
876__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
877{
878 int count;
879
880 count = 0;
881 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
882 DELAY(10);
883
884 I915_WRITE_NOTRACE(FORCEWAKE, 1);
885 POSTING_READ(FORCEWAKE);
886
887 count = 0;
888 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
889 DELAY(10);
890}
891
892void
893__gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
894{
895 int count;
896
897 count = 0;
898 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
899 DELAY(10);
900
901 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
902 POSTING_READ(FORCEWAKE_MT);
903
904 count = 0;
905 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
906 DELAY(10);
907}
908
909void
910gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
911{
912
913 mtx_lock(&dev_priv->gt_lock);
914 if (dev_priv->forcewake_count++ == 0)
915 dev_priv->display.force_wake_get(dev_priv);
916 mtx_unlock(&dev_priv->gt_lock);
917}
918
919static void
920gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
921{
922 u32 gtfifodbg;
923
924 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
925 if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
926 printf("MMIO read or write has been dropped %x\n", gtfifodbg);
927 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
928 }
929}
930
931void
932__gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
933{
934
935 I915_WRITE_NOTRACE(FORCEWAKE, 0);
936 /* The below doubles as a POSTING_READ */
937 gen6_gt_check_fifodbg(dev_priv);
938}
939
940void
941__gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
942{
943
944 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
945 /* The below doubles as a POSTING_READ */
946 gen6_gt_check_fifodbg(dev_priv);
947}
948
949void
950gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
951{
952
953 mtx_lock(&dev_priv->gt_lock);
954 if (--dev_priv->forcewake_count == 0)
955 dev_priv->display.force_wake_put(dev_priv);
956 mtx_unlock(&dev_priv->gt_lock);
957}
958
959int
960__gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
961{
962 int ret = 0;
963
964 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
965 int loop = 500;
966 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
967 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
968 DELAY(10);
969 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
970 }
971 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
972 printf("%s loop\n", __func__);
973 ++ret;
974 }
975 dev_priv->gt_fifo_count = fifo;
976 }
977 dev_priv->gt_fifo_count--;
978
979 return (ret);
980}
981
982void vlv_force_wake_get(struct drm_i915_private *dev_priv)
983{
984 int count;
985
986 count = 0;
987
988 /* Already awake? */
989 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
990 return;
991
992 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
993 POSTING_READ(FORCEWAKE_VLV);
994
995 count = 0;
996 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
997 DELAY(10);
998}
999
1000void vlv_force_wake_put(struct drm_i915_private *dev_priv)
1001{
1002 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
1003 /* FIXME: confirm VLV behavior with Punit folks */
1004 POSTING_READ(FORCEWAKE_VLV);
1005}
1006
1014#define __i915_read(x, y) \
1015u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1016 u##x val = 0; \
1017 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1018 mtx_lock(&dev_priv->gt_lock); \
1019 if (dev_priv->forcewake_count == 0) \
1020 dev_priv->display.force_wake_get(dev_priv); \
1007#define __i915_read(x, y) \
1008u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1009 u##x val = 0; \
1010 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1011 mtx_lock(&dev_priv->gt_lock); \
1012 if (dev_priv->forcewake_count == 0) \
1013 dev_priv->display.force_wake_get(dev_priv); \
1021 val = DRM_READ##y(dev_priv->mmio_map, reg); \
1014 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1022 if (dev_priv->forcewake_count == 0) \
1023 dev_priv->display.force_wake_put(dev_priv); \
1024 mtx_unlock(&dev_priv->gt_lock); \
1025 } else { \
1015 if (dev_priv->forcewake_count == 0) \
1016 dev_priv->display.force_wake_put(dev_priv); \
1017 mtx_unlock(&dev_priv->gt_lock); \
1018 } else { \
1026 val = DRM_READ##y(dev_priv->mmio_map, reg); \
1019 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1027 } \
1028 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1029 return val; \
1030}
1031
1032__i915_read(8, 8)
1033__i915_read(16, 16)
1034__i915_read(32, 32)
1035__i915_read(64, 64)
1036#undef __i915_read
1037
1038#define __i915_write(x, y) \
1039void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1040 u32 __fifo_ret = 0; \
1041 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1042 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1043 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1044 } \
1020 } \
1021 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1022 return val; \
1023}
1024
1025__i915_read(8, 8)
1026__i915_read(16, 16)
1027__i915_read(32, 32)
1028__i915_read(64, 64)
1029#undef __i915_read
1030
1031#define __i915_write(x, y) \
1032void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1033 u32 __fifo_ret = 0; \
1034 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1035 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1036 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1037 } \
1045 DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
1038 DRM_WRITE##x(dev_priv->mmio_map, reg, val); \
1046 if (__predict_false(__fifo_ret)) { \
1047 gen6_gt_check_fifodbg(dev_priv); \
1048 } \
1049}
1050__i915_write(8, 8)
1051__i915_write(16, 16)
1052__i915_write(32, 32)
1053__i915_write(64, 64)
1054#undef __i915_write
1039 if (__predict_false(__fifo_ret)) { \
1040 gen6_gt_check_fifodbg(dev_priv); \
1041 } \
1042}
1043__i915_write(8, 8)
1044__i915_write(16, 16)
1045__i915_write(32, 32)
1046__i915_write(64, 64)
1047#undef __i915_write