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i915_drv.c (280183) i915_drv.c (287173)
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 16 unchanged lines hidden (view full) ---

25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32#include <sys/cdefs.h>
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 16 unchanged lines hidden (view full) ---

25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 280183 2015-03-17 18:50:33Z dumbbell $");
33__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 287173 2015-08-26 21:33:43Z bapt $");
34
35#include <dev/drm2/drmP.h>
36#include <dev/drm2/drm.h>
37#include <dev/drm2/drm_mm.h>
38#include <dev/drm2/i915/i915_drm.h>
39#include <dev/drm2/i915/i915_drv.h>
40#include <dev/drm2/drm_pciids.h>
41#include <dev/drm2/i915/intel_drv.h>
42
43#include "fb_if.h"
44
45/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
46static drm_pci_id_list_t i915_pciidlist[] = {
47 i915_PCI_IDS
48};
49
34
35#include <dev/drm2/drmP.h>
36#include <dev/drm2/drm.h>
37#include <dev/drm2/drm_mm.h>
38#include <dev/drm2/i915/i915_drm.h>
39#include <dev/drm2/i915/i915_drv.h>
40#include <dev/drm2/drm_pciids.h>
41#include <dev/drm2/i915/intel_drv.h>
42
43#include "fb_if.h"
44
45/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
46static drm_pci_id_list_t i915_pciidlist[] = {
47 i915_PCI_IDS
48};
49
50#define INTEL_VGA_DEVICE(id, info_) { \
51 .device = id, \
52 .info = info_, \
53}
54
50static const struct intel_device_info intel_i830_info = {
51 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
52 .has_overlay = 1, .overlay_needs_physical = 1,
53};
54
55static const struct intel_device_info intel_845g_info = {
56 .gen = 2,
57 .has_overlay = 1, .overlay_needs_physical = 1,

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176 .need_gfx_hws = 1, .has_hotplug = 1,
177 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
178 .has_bsd_ring = 1,
179 .has_blt_ring = 1,
180 .has_llc = 1,
181 .has_pch_split = 1,
182};
183
55static const struct intel_device_info intel_i830_info = {
56 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
57 .has_overlay = 1, .overlay_needs_physical = 1,
58};
59
60static const struct intel_device_info intel_845g_info = {
61 .gen = 2,
62 .has_overlay = 1, .overlay_needs_physical = 1,

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181 .need_gfx_hws = 1, .has_hotplug = 1,
182 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
183 .has_bsd_ring = 1,
184 .has_blt_ring = 1,
185 .has_llc = 1,
186 .has_pch_split = 1,
187};
188
184#if 0
185static const struct intel_device_info intel_valleyview_m_info = {
186 .gen = 7, .is_mobile = 1,
187 .need_gfx_hws = 1, .has_hotplug = 1,
188 .has_fbc = 0,
189 .has_bsd_ring = 1,
190 .has_blt_ring = 1,
191 .is_valleyview = 1,
192};
193
194static const struct intel_device_info intel_valleyview_d_info = {
195 .gen = 7,
196 .need_gfx_hws = 1, .has_hotplug = 1,
197 .has_fbc = 0,
198 .has_bsd_ring = 1,
199 .has_blt_ring = 1,
200 .is_valleyview = 1,
201};
189static const struct intel_device_info intel_valleyview_m_info = {
190 .gen = 7, .is_mobile = 1,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .has_fbc = 0,
193 .has_bsd_ring = 1,
194 .has_blt_ring = 1,
195 .is_valleyview = 1,
196};
197
198static const struct intel_device_info intel_valleyview_d_info = {
199 .gen = 7,
200 .need_gfx_hws = 1, .has_hotplug = 1,
201 .has_fbc = 0,
202 .has_bsd_ring = 1,
203 .has_blt_ring = 1,
204 .is_valleyview = 1,
205};
202#endif
203
204static const struct intel_device_info intel_haswell_d_info = {
205 .is_haswell = 1, .gen = 7,
206 .need_gfx_hws = 1, .has_hotplug = 1,
207 .has_bsd_ring = 1,
208 .has_blt_ring = 1,
209 .has_llc = 1,
210 .has_pch_split = 1,

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216 .need_gfx_hws = 1, .has_hotplug = 1,
217 .has_bsd_ring = 1,
218 .has_blt_ring = 1,
219 .has_llc = 1,
220 .has_pch_split = 1,
221 .not_supported = 1,
222};
223
206
207static const struct intel_device_info intel_haswell_d_info = {
208 .is_haswell = 1, .gen = 7,
209 .need_gfx_hws = 1, .has_hotplug = 1,
210 .has_bsd_ring = 1,
211 .has_blt_ring = 1,
212 .has_llc = 1,
213 .has_pch_split = 1,

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219 .need_gfx_hws = 1, .has_hotplug = 1,
220 .has_bsd_ring = 1,
221 .has_blt_ring = 1,
222 .has_llc = 1,
223 .has_pch_split = 1,
224 .not_supported = 1,
225};
226
224#define INTEL_VGA_DEVICE(id, info_) { \
225 .device = id, \
226 .info = info_, \
227}
228
229static const struct intel_gfx_device_id {
230 int device;
231 const struct intel_device_info *info;
227static const struct intel_gfx_device_id {
228 int device;
229 const struct intel_device_info *info;
232} pciidlist[] = { /* aka */
233 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
234 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
235 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
230} pciidlist[] = { /* aka */
231 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
232 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
233 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
236 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
234 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
237 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
238 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
239 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
240 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
241 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
242 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
243 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
244 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
245 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
246 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
247 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
248 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
249 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
250 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
251 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
252 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
253 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
254 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
255 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
256 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
257 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
258 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
259 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),
235 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
236 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
237 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
238 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
239 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
240 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
241 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
242 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
243 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
244 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
245 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
246 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
247 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
248 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
249 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
250 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
251 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
252 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
253 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
254 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
255 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
256 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
257 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
260 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
261 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
262 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
263 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
264 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
265 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
266 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
267 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
268 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
269 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
270 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
271 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
272 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
273 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
274 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
275 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
276 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
277 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
278 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
258 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
259 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
260 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
261 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
262 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
263 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
264 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
265 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
266 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
267 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
268 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
269 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
270 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
271 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
272 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
273 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
274 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
275 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
276 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
277 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
279 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
280 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
278 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
279 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
280 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
281 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
282 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
281 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
282 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
283 INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
283 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
284 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
285 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
286 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
287 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
288 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
289 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
290 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
291 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
292 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
293 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
294 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
295 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
296 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
297 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
298 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
299 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
300 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
301 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
302 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
303 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
304 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
305 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
306 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
307 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
308 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
309 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
310 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
311 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
312 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
313 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
284 {0, 0}
285};
286
287static int i915_enable_unsupported;
288
289static int i915_drm_freeze(struct drm_device *dev)
290{
314 {0, 0}
315};
316
317static int i915_enable_unsupported;
318
319static int i915_drm_freeze(struct drm_device *dev)
320{
291 struct drm_i915_private *dev_priv;
292 int error;
321 struct drm_i915_private *dev_priv = dev->dev_private;
293
322
294 dev_priv = dev->dev_private;
295 drm_kms_helper_poll_disable(dev);
296
297#if 0
298 pci_save_state(dev->pdev);
299#endif
300
301 /* If KMS is active, we do the leavevt stuff here */
302 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
323 drm_kms_helper_poll_disable(dev);
324
325#if 0
326 pci_save_state(dev->pdev);
327#endif
328
329 /* If KMS is active, we do the leavevt stuff here */
330 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
303 error = i915_gem_idle(dev);
331 int error = i915_gem_idle(dev);
304 if (error) {
305 device_printf(dev->dev,
332 if (error) {
333 device_printf(dev->dev,
306 "GEM idle failed, resume might fail\n");
307 return (error);
334 "GEM idle failed, resume might fail\n");
335 return error;
308 }
309 drm_irq_uninstall(dev);
310 }
311
312 i915_save_state(dev);
313
314 intel_opregion_fini(dev);
315
316 /* Modeset on resume, not lid events */
317 dev_priv->modeset_on_lid = 0;
318
319 return 0;
320}
321
336 }
337 drm_irq_uninstall(dev);
338 }
339
340 i915_save_state(dev);
341
342 intel_opregion_fini(dev);
343
344 /* Modeset on resume, not lid events */
345 dev_priv->modeset_on_lid = 0;
346
347 return 0;
348}
349
322static int
323i915_suspend(device_t kdev)
350static int i915_suspend(device_t kdev)
324{
325 struct drm_device *dev;
326 int error;
327
328 dev = device_get_softc(kdev);
329 if (dev == NULL || dev->dev_private == NULL) {
330 DRM_ERROR("DRM not initialized, aborting suspend.\n");
331 return ENODEV;

--- 48 unchanged lines hidden (view full) ---

380
381 intel_opregion_init(dev);
382
383 dev_priv->modeset_on_lid = 0;
384
385 return error;
386}
387
351{
352 struct drm_device *dev;
353 int error;
354
355 dev = device_get_softc(kdev);
356 if (dev == NULL || dev->dev_private == NULL) {
357 DRM_ERROR("DRM not initialized, aborting suspend.\n");
358 return ENODEV;

--- 48 unchanged lines hidden (view full) ---

407
408 intel_opregion_init(dev);
409
410 dev_priv->modeset_on_lid = 0;
411
412 return error;
413}
414
388static int
389i915_resume(device_t kdev)
415static int i915_resume(device_t kdev)
390{
391 struct drm_device *dev;
392 int ret;
393
394 dev = device_get_softc(kdev);
395 DRM_DEBUG_KMS("starting resume\n");
396#if 0
397 if (pci_enable_device(dev->pdev))

--- 322 unchanged lines hidden (view full) ---

720
721void vlv_force_wake_put(struct drm_i915_private *dev_priv)
722{
723 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
724 /* FIXME: confirm VLV behavior with Punit folks */
725 POSTING_READ(FORCEWAKE_VLV);
726}
727
416{
417 struct drm_device *dev;
418 int ret;
419
420 dev = device_get_softc(kdev);
421 DRM_DEBUG_KMS("starting resume\n");
422#if 0
423 if (pci_enable_device(dev->pdev))

--- 322 unchanged lines hidden (view full) ---

746
747void vlv_force_wake_put(struct drm_i915_private *dev_priv)
748{
749 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
750 /* FIXME: confirm VLV behavior with Punit folks */
751 POSTING_READ(FORCEWAKE_VLV);
752}
753
728static int
729i8xx_do_reset(struct drm_device *dev)
754static int i8xx_do_reset(struct drm_device *dev)
730{
731 struct drm_i915_private *dev_priv = dev->dev_private;
732 int onems;
733
734 if (IS_I85X(dev))
735 return -ENODEV;
736
737 onems = hz / 1000;

--- 18 unchanged lines hidden (view full) ---

756 pause("i8xxrst2", onems);
757
758 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
759 POSTING_READ(D_STATE);
760
761 return 0;
762}
763
755{
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 int onems;
758
759 if (IS_I85X(dev))
760 return -ENODEV;
761
762 onems = hz / 1000;

--- 18 unchanged lines hidden (view full) ---

781 pause("i8xxrst2", onems);
782
783 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
784 POSTING_READ(D_STATE);
785
786 return 0;
787}
788
764static int
765i965_reset_complete(struct drm_device *dev)
789static int i965_reset_complete(struct drm_device *dev)
766{
767 u8 gdrst;
768
769 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
770 return (gdrst & GRDOM_RESET_ENABLE) == 0;
771}
772
790{
791 u8 gdrst;
792
793 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
794 return (gdrst & GRDOM_RESET_ENABLE) == 0;
795}
796
773static int
774i965_do_reset(struct drm_device *dev)
797static int i965_do_reset(struct drm_device *dev)
775{
776 int ret;
777 u8 gdrst;
778
779 /*
780 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
781 * well as the reset bit (GR/bit 0). Setting the GR bit
782 * triggers the reset; when done, the hardware will clear it.

--- 5 unchanged lines hidden (view full) ---

788 ret = wait_for(i965_reset_complete(dev), 500);
789 if (ret)
790 return ret;
791
792 /* We can't reset render&media without also resetting display ... */
793 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
794 pci_write_config(dev->dev, I965_GDRST,
795 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE, 1);
798{
799 int ret;
800 u8 gdrst;
801
802 /*
803 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
804 * well as the reset bit (GR/bit 0). Setting the GR bit
805 * triggers the reset; when done, the hardware will clear it.

--- 5 unchanged lines hidden (view full) ---

811 ret = wait_for(i965_reset_complete(dev), 500);
812 if (ret)
813 return ret;
814
815 /* We can't reset render&media without also resetting display ... */
816 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
817 pci_write_config(dev->dev, I965_GDRST,
818 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE, 1);
796
797 return wait_for(i965_reset_complete(dev), 500);
819
820 return wait_for(i965_reset_complete(dev), 500);
798}
799
821}
822
800static int
801ironlake_do_reset(struct drm_device *dev)
823static int ironlake_do_reset(struct drm_device *dev)
802{
824{
803 struct drm_i915_private *dev_priv;
825 struct drm_i915_private *dev_priv = dev->dev_private;
804 u32 gdrst;
805 int ret;
806
826 u32 gdrst;
827 int ret;
828
807 dev_priv = dev->dev_private;
808 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
809 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
810 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
811 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
812 if (ret)
813 return ret;
814
815 /* We can't reset render&media without also resetting display ... */
816 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
817 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
818 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
829 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
830 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
831 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
832 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
833 if (ret)
834 return ret;
835
836 /* We can't reset render&media without also resetting display ... */
837 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
838 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
839 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
819 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
840 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
820}
821
841}
842
822static int
823gen6_do_reset(struct drm_device *dev)
843static int gen6_do_reset(struct drm_device *dev)
824{
844{
825 struct drm_i915_private *dev_priv;
826 int ret;
845 struct drm_i915_private *dev_priv = dev->dev_private;
846 int ret;
827
847
828 dev_priv = dev->dev_private;
829
830 /* Hold gt_lock across reset to prevent any register access
831 * with forcewake not set correctly
832 */
833 mtx_lock(&dev_priv->gt_lock);
834
835 /* Reset the chip */
836
837 /* GEN6_GDRST is not in the gt power well, no need to check

--- 15 unchanged lines hidden (view full) ---

853
854 /* Restore fifo count */
855 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
856
857 mtx_unlock(&dev_priv->gt_lock);
858 return (ret);
859}
860
848 /* Hold gt_lock across reset to prevent any register access
849 * with forcewake not set correctly
850 */
851 mtx_lock(&dev_priv->gt_lock);
852
853 /* Reset the chip */
854
855 /* GEN6_GDRST is not in the gt power well, no need to check

--- 15 unchanged lines hidden (view full) ---

871
872 /* Restore fifo count */
873 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
874
875 mtx_unlock(&dev_priv->gt_lock);
876 return (ret);
877}
878
861int
862intel_gpu_reset(struct drm_device *dev)
879int intel_gpu_reset(struct drm_device *dev)
863{
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 int ret = -ENODEV;
866
867 switch (INTEL_INFO(dev)->gen) {
868 case 7:
869 case 6:
870 ret = gen6_do_reset(dev);

--- 18 unchanged lines hidden (view full) ---

889 "error for simulated gpu hangs\n");
890 ret = 0;
891 }
892 }
893
894 return ret;
895}
896
880{
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 int ret = -ENODEV;
883
884 switch (INTEL_INFO(dev)->gen) {
885 case 7:
886 case 6:
887 ret = gen6_do_reset(dev);

--- 18 unchanged lines hidden (view full) ---

906 "error for simulated gpu hangs\n");
907 ret = 0;
908 }
909 }
910
911 return ret;
912}
913
914/**
915 * i915_reset - reset chip after a hang
916 * @dev: drm device to reset
917 *
918 * Reset the chip. Useful if a hang is detected. Returns zero on successful
919 * reset or otherwise an error code.
920 *
921 * Procedure is fairly simple:
922 * - reset the chip using the reset reg
923 * - re-init context state
924 * - re-init hardware status page
925 * - re-init ring buffer
926 * - re-init interrupt state
927 * - re-init display
928 */
897int i915_reset(struct drm_device *dev)
898{
899 drm_i915_private_t *dev_priv = dev->dev_private;
900 int ret;
901
902 if (!i915_try_reset)
929int i915_reset(struct drm_device *dev)
930{
931 drm_i915_private_t *dev_priv = dev->dev_private;
932 int ret;
933
934 if (!i915_try_reset)
903 return (0);
935 return 0;
904
905 if (!sx_try_xlock(&dev->dev_struct_lock))
906 return (-EBUSY);
907
908 dev_priv->stop_rings = 0;
909
910 i915_gem_reset(dev);
911
912 ret = -ENODEV;
913 if (time_second - dev_priv->last_gpu_reset < 5)
914 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
915 else
916 ret = intel_gpu_reset(dev);
917
918 dev_priv->last_gpu_reset = time_second;
919 if (ret) {
920 DRM_ERROR("Failed to reset chip.\n");
921 DRM_UNLOCK(dev);
936
937 if (!sx_try_xlock(&dev->dev_struct_lock))
938 return (-EBUSY);
939
940 dev_priv->stop_rings = 0;
941
942 i915_gem_reset(dev);
943
944 ret = -ENODEV;
945 if (time_second - dev_priv->last_gpu_reset < 5)
946 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
947 else
948 ret = intel_gpu_reset(dev);
949
950 dev_priv->last_gpu_reset = time_second;
951 if (ret) {
952 DRM_ERROR("Failed to reset chip.\n");
953 DRM_UNLOCK(dev);
922 return (ret);
954 return ret;
923 }
924
955 }
956
957 /* Ok, now get things going again... */
958
959 /*
960 * Everything depends on having the GTT running, so we need to start
961 * there. Fortunately we don't need to do this unless we reset the
962 * chip at a PCI level.
963 *
964 * Next we need to restore the context, but we don't use those
965 * yet either...
966 *
967 * Ring buffer needs to be re-initialized in the KMS case, or if X
968 * was running at the time of the reset (i.e. we weren't VT
969 * switched away).
970 */
925 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
971 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
926 !dev_priv->mm.suspended) {
972 !dev_priv->mm.suspended) {
927 struct intel_ring_buffer *ring;
928 int i;
929
930 dev_priv->mm.suspended = 0;
931
932 i915_gem_init_swizzling(dev);
933
934 for_each_ring(ring, dev_priv, i)
935 ring->init(ring);
936
937 i915_gem_context_init(dev);
938 i915_gem_init_ppgtt(dev);
939
973 struct intel_ring_buffer *ring;
974 int i;
975
976 dev_priv->mm.suspended = 0;
977
978 i915_gem_init_swizzling(dev);
979
980 for_each_ring(ring, dev_priv, i)
981 ring->init(ring);
982
983 i915_gem_context_init(dev);
984 i915_gem_init_ppgtt(dev);
985
986 /*
987 * It would make sense to re-init all the other hw state, at
988 * least the rps/rc6/emon init done within modeset_init_hw. For
989 * some unknown reason, this blows up my ilk, so don't.
990 */
940 DRM_UNLOCK(dev);
941
942 if (drm_core_check_feature(dev, DRIVER_MODESET))
943 intel_modeset_init_hw(dev);
944
945 drm_irq_uninstall(dev);
946 drm_irq_install(dev);
991 DRM_UNLOCK(dev);
992
993 if (drm_core_check_feature(dev, DRIVER_MODESET))
994 intel_modeset_init_hw(dev);
995
996 drm_irq_uninstall(dev);
997 drm_irq_install(dev);
947 } else
998 } else {
948 DRM_UNLOCK(dev);
999 DRM_UNLOCK(dev);
1000 }
949
1001
950 return (0);
1002 return 0;
951}
952
953/* We give fast paths for the really cool registers */
954#define NEEDS_FORCE_WAKE(dev_priv, reg) \
955 (((dev_priv)->info->gen >= 6) && \
956 ((reg) < 0x40000) && \
957 ((reg) != FORCEWAKE)) && \
958 (!IS_VALLEYVIEW((dev_priv)->dev))

--- 42 unchanged lines hidden --- 		1003}
1004
1005/* We give fast paths for the really cool registers */
1006#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1007 (((dev_priv)->info->gen >= 6) && \
1008 ((reg) < 0x40000) && \
1009 ((reg) != FORCEWAKE)) && \
1010 (!IS_VALLEYVIEW((dev_priv)->dev))

--- 42 unchanged lines hidden ---