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i915_drv.c (271705) i915_drv.c (277487)
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 16 unchanged lines hidden (view full) ---

25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32#include <sys/cdefs.h>
1/* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4/*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 16 unchanged lines hidden (view full) ---

25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 271705 2014-09-17 08:28:50Z dumbbell $");
33__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.c 277487 2015-01-21 16:10:37Z kib $");
34
35#include <dev/drm2/drmP.h>
36#include <dev/drm2/drm.h>
37#include <dev/drm2/drm_mm.h>
38#include <dev/drm2/i915/i915_drm.h>
39#include <dev/drm2/i915/i915_drv.h>
40#include <dev/drm2/drm_pciids.h>
41#include <dev/drm2/i915/intel_drv.h>

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127 .need_gfx_hws = 1, .has_hotplug = 1,
128 .has_overlay = 1,
129};
130
131static const struct intel_device_info intel_ironlake_d_info = {
132 .gen = 5,
133 .need_gfx_hws = 1, .has_hotplug = 1,
134 .has_bsd_ring = 1,
34
35#include <dev/drm2/drmP.h>
36#include <dev/drm2/drm.h>
37#include <dev/drm2/drm_mm.h>
38#include <dev/drm2/i915/i915_drm.h>
39#include <dev/drm2/i915/i915_drv.h>
40#include <dev/drm2/drm_pciids.h>
41#include <dev/drm2/i915/intel_drv.h>

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127 .need_gfx_hws = 1, .has_hotplug = 1,
128 .has_overlay = 1,
129};
130
131static const struct intel_device_info intel_ironlake_d_info = {
132 .gen = 5,
133 .need_gfx_hws = 1, .has_hotplug = 1,
134 .has_bsd_ring = 1,
135 .has_pch_split = 1,
135};
136
137static const struct intel_device_info intel_ironlake_m_info = {
138 .gen = 5, .is_mobile = 1,
139 .need_gfx_hws = 1, .has_hotplug = 1,
140 .has_fbc = 0, /* disabled due to buggy hardware */
141 .has_bsd_ring = 1,
136};
137
138static const struct intel_device_info intel_ironlake_m_info = {
139 .gen = 5, .is_mobile = 1,
140 .need_gfx_hws = 1, .has_hotplug = 1,
141 .has_fbc = 0, /* disabled due to buggy hardware */
142 .has_bsd_ring = 1,
143 .has_pch_split = 1,
142};
143
144static const struct intel_device_info intel_sandybridge_d_info = {
145 .gen = 6,
146 .need_gfx_hws = 1, .has_hotplug = 1,
147 .has_bsd_ring = 1,
148 .has_blt_ring = 1,
149 .has_llc = 1,
144};
145
146static const struct intel_device_info intel_sandybridge_d_info = {
147 .gen = 6,
148 .need_gfx_hws = 1, .has_hotplug = 1,
149 .has_bsd_ring = 1,
150 .has_blt_ring = 1,
151 .has_llc = 1,
152 .has_pch_split = 1,
150};
151
152static const struct intel_device_info intel_sandybridge_m_info = {
153 .gen = 6, .is_mobile = 1,
154 .need_gfx_hws = 1, .has_hotplug = 1,
155 .has_fbc = 1,
156 .has_bsd_ring = 1,
157 .has_blt_ring = 1,
158 .has_llc = 1,
153};
154
155static const struct intel_device_info intel_sandybridge_m_info = {
156 .gen = 6, .is_mobile = 1,
157 .need_gfx_hws = 1, .has_hotplug = 1,
158 .has_fbc = 1,
159 .has_bsd_ring = 1,
160 .has_blt_ring = 1,
161 .has_llc = 1,
162 .has_pch_split = 1,
159};
160
161static const struct intel_device_info intel_ivybridge_d_info = {
162 .is_ivybridge = 1, .gen = 7,
163 .need_gfx_hws = 1, .has_hotplug = 1,
164 .has_bsd_ring = 1,
165 .has_blt_ring = 1,
166 .has_llc = 1,
163};
164
165static const struct intel_device_info intel_ivybridge_d_info = {
166 .is_ivybridge = 1, .gen = 7,
167 .need_gfx_hws = 1, .has_hotplug = 1,
168 .has_bsd_ring = 1,
169 .has_blt_ring = 1,
170 .has_llc = 1,
171 .has_pch_split = 1,
167};
168
169static const struct intel_device_info intel_ivybridge_m_info = {
170 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
171 .need_gfx_hws = 1, .has_hotplug = 1,
172 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
173 .has_bsd_ring = 1,
174 .has_blt_ring = 1,
175 .has_llc = 1,
172};
173
174static const struct intel_device_info intel_ivybridge_m_info = {
175 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
176 .need_gfx_hws = 1, .has_hotplug = 1,
177 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
178 .has_bsd_ring = 1,
179 .has_blt_ring = 1,
180 .has_llc = 1,
181 .has_pch_split = 1,
176};
177
182};
183
184#if 0
185static const struct intel_device_info intel_valleyview_m_info = {
186 .gen = 7, .is_mobile = 1,
187 .need_gfx_hws = 1, .has_hotplug = 1,
188 .has_fbc = 0,
189 .has_bsd_ring = 1,
190 .has_blt_ring = 1,
191 .is_valleyview = 1,
192};
193
194static const struct intel_device_info intel_valleyview_d_info = {
195 .gen = 7,
196 .need_gfx_hws = 1, .has_hotplug = 1,
197 .has_fbc = 0,
198 .has_bsd_ring = 1,
199 .has_blt_ring = 1,
200 .is_valleyview = 1,
201};
202#endif
203
204static const struct intel_device_info intel_haswell_d_info = {
205 .is_haswell = 1, .gen = 7,
206 .need_gfx_hws = 1, .has_hotplug = 1,
207 .has_bsd_ring = 1,
208 .has_blt_ring = 1,
209 .has_llc = 1,
210 .has_pch_split = 1,
211};
212
213static const struct intel_device_info intel_haswell_m_info = {
214 .is_haswell = 1, .gen = 7, .is_mobile = 1,
215 .need_gfx_hws = 1, .has_hotplug = 1,
216 .has_bsd_ring = 1,
217 .has_blt_ring = 1,
218 .has_llc = 1,
219 .has_pch_split = 1,
220};
221
178#define INTEL_VGA_DEVICE(id, info_) { \
179 .device = id, \
180 .info = info_, \
181}
182
183static const struct intel_gfx_device_id {
184 int device;
185 const struct intel_device_info *info;

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223 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
224 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
225 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
226 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
227 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
228 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
229 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
230 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
222#define INTEL_VGA_DEVICE(id, info_) { \
223 .device = id, \
224 .info = info_, \
225}
226
227static const struct intel_gfx_device_id {
228 int device;
229 const struct intel_device_info *info;

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267 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
268 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
269 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
270 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
271 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
272 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
273 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
274 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
275 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
276 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
277 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
278 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
279 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
280 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
281 INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
231 {0, 0}
232};
233
234static int i915_drm_freeze(struct drm_device *dev)
235{
236 struct drm_i915_private *dev_priv;
237 int error;
238

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299 i915_gem_restore_gtt_mappings(dev);
300 }
301
302 i915_restore_state(dev);
303 intel_opregion_setup(dev);
304
305 /* KMS EnterVT equivalent */
306 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
282 {0, 0}
283};
284
285static int i915_drm_freeze(struct drm_device *dev)
286{
287 struct drm_i915_private *dev_priv;
288 int error;
289

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350 i915_gem_restore_gtt_mappings(dev);
351 }
352
353 i915_restore_state(dev);
354 intel_opregion_setup(dev);
355
356 /* KMS EnterVT equivalent */
357 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
307 dev_priv->mm.suspended = 0;
308
309 error = i915_gem_init_hw(dev);
310
311 if (HAS_PCH_SPLIT(dev))
312 ironlake_init_pch_refclk(dev);
313
358 if (HAS_PCH_SPLIT(dev))
359 ironlake_init_pch_refclk(dev);
360
361 dev_priv->mm.suspended = 0;
362
363 error = i915_gem_init_hw(dev);
314 DRM_UNLOCK(dev);
364 DRM_UNLOCK(dev);
365
366 intel_modeset_init_hw(dev);
315 sx_xlock(&dev->mode_config.mutex);
316 drm_mode_config_reset(dev);
317 sx_xunlock(&dev->mode_config.mutex);
318 drm_irq_install(dev);
319
320 sx_xlock(&dev->mode_config.mutex);
321 /* Resume the modeset for every activated CRTC */
322 drm_helper_resume_force_mode(dev);
323 sx_xunlock(&dev->mode_config.mutex);
367 sx_xlock(&dev->mode_config.mutex);
368 drm_mode_config_reset(dev);
369 sx_xunlock(&dev->mode_config.mutex);
370 drm_irq_install(dev);
371
372 sx_xlock(&dev->mode_config.mutex);
373 /* Resume the modeset for every activated CRTC */
374 drm_helper_resume_force_mode(dev);
375 sx_xunlock(&dev->mode_config.mutex);
324
325 if (IS_IRONLAKE_M(dev))
326 ironlake_enable_rc6(dev);
327 DRM_LOCK(dev);
328 }
329
330 intel_opregion_init(dev);
331
332 dev_priv->modeset_on_lid = 0;
333
334 DRM_UNLOCK(dev);

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440MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
441MODULE_DEPEND(i915kms, agp, 1, 1, 1);
442MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
443MODULE_DEPEND(i915kms, iic, 1, 1, 1);
444MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
445
446int intel_iommu_enabled = 0;
447TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
376 DRM_LOCK(dev);
377 }
378
379 intel_opregion_init(dev);
380
381 dev_priv->modeset_on_lid = 0;
382
383 DRM_UNLOCK(dev);

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489MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
490MODULE_DEPEND(i915kms, agp, 1, 1, 1);
491MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
492MODULE_DEPEND(i915kms, iic, 1, 1, 1);
493MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
494
495int intel_iommu_enabled = 0;
496TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
497int intel_iommu_gfx_mapped = 0;
498TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
448
499
500int i915_prefault_disable;
501TUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable);
449int i915_semaphores = -1;
450TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
451static int i915_try_reset = 1;
452TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
453unsigned int i915_lvds_downclock = 0;
454TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
455int i915_vbt_sdvo_panel_type = -1;
456TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
457unsigned int i915_powersave = 1;
458TUNABLE_INT("drm.i915.powersave", &i915_powersave);
459int i915_enable_fbc = 0;
460TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
461int i915_enable_rc6 = 0;
462TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
502int i915_semaphores = -1;
503TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
504static int i915_try_reset = 1;
505TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
506unsigned int i915_lvds_downclock = 0;
507TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
508int i915_vbt_sdvo_panel_type = -1;
509TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
510unsigned int i915_powersave = 1;
511TUNABLE_INT("drm.i915.powersave", &i915_powersave);
512int i915_enable_fbc = 0;
513TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
514int i915_enable_rc6 = 0;
515TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
516int i915_lvds_channel_mode;
517TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
463int i915_panel_use_ssc = -1;
464TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
465int i915_panel_ignore_lid = 0;
466TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
518int i915_panel_use_ssc = -1;
519TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
520int i915_panel_ignore_lid = 0;
521TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
522int i915_panel_invert_brightness;
523TUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness);
467int i915_modeset = 1;
468TUNABLE_INT("drm.i915.modeset", &i915_modeset);
469int i915_enable_ppgtt = -1;
470TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
471int i915_enable_hangcheck = 1;
472TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
473
474#define PCI_VENDOR_INTEL 0x8086
475#define INTEL_PCH_DEVICE_ID_MASK 0xff00
476#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
477#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
478#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
524int i915_modeset = 1;
525TUNABLE_INT("drm.i915.modeset", &i915_modeset);
526int i915_enable_ppgtt = -1;
527TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
528int i915_enable_hangcheck = 1;
529TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
530
531#define PCI_VENDOR_INTEL 0x8086
532#define INTEL_PCH_DEVICE_ID_MASK 0xff00
533#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
534#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
535#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
536#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
479
537
480void
481intel_detect_pch(struct drm_device *dev)
538void intel_detect_pch(struct drm_device *dev)
482{
483 struct drm_i915_private *dev_priv;
484 device_t pch;
485 uint32_t id;
486
487 dev_priv = dev->dev_private;
488 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
489 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
490 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
491 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
492 dev_priv->pch_type = PCH_IBX;
539{
540 struct drm_i915_private *dev_priv;
541 device_t pch;
542 uint32_t id;
543
544 dev_priv = dev->dev_private;
545 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
546 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
547 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
548 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
549 dev_priv->pch_type = PCH_IBX;
550 dev_priv->num_pch_pll = 2;
493 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
494 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
495 dev_priv->pch_type = PCH_CPT;
551 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
552 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
553 dev_priv->pch_type = PCH_CPT;
554 dev_priv->num_pch_pll = 2;
496 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
497 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
498 /* PantherPoint is CPT compatible */
499 dev_priv->pch_type = PCH_CPT;
555 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
556 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
557 /* PantherPoint is CPT compatible */
558 dev_priv->pch_type = PCH_CPT;
559 dev_priv->num_pch_pll = 2;
500 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
560 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
561 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
562 dev_priv->pch_type = PCH_LPT;
563 dev_priv->num_pch_pll = 0;
564 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
501 } else
502 DRM_DEBUG_KMS("No PCH detected\n");
565 } else
566 DRM_DEBUG_KMS("No PCH detected\n");
567 KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
568 ("num_pch_pll %d\n", dev_priv->num_pch_pll));
503 } else
504 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
505}
506
569 } else
570 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
571}
572
573bool i915_semaphore_is_enabled(struct drm_device *dev)
574{
575 if (INTEL_INFO(dev)->gen < 6)
576 return 0;
577
578 if (i915_semaphores >= 0)
579 return i915_semaphores;
580
581 /* Enable semaphores on SNB when IO remapping is off */
582 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
583 return false;
584
585 return 1;
586}
587
507void
508__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
509{
510 int count;
511
512 count = 0;
513 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
514 DELAY(10);

--- 10 unchanged lines hidden (view full) ---

525__gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
526{
527 int count;
528
529 count = 0;
530 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
531 DELAY(10);
532
588void
589__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
590{
591 int count;
592
593 count = 0;
594 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
595 DELAY(10);

--- 10 unchanged lines hidden (view full) ---

606__gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
607{
608 int count;
609
610 count = 0;
611 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
612 DELAY(10);
613
533 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
614 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
534 POSTING_READ(FORCEWAKE_MT);
535
536 count = 0;
537 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
538 DELAY(10);
539}
540
541void

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568 /* The below doubles as a POSTING_READ */
569 gen6_gt_check_fifodbg(dev_priv);
570}
571
572void
573__gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
574{
575
615 POSTING_READ(FORCEWAKE_MT);
616
617 count = 0;
618 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
619 DELAY(10);
620}
621
622void

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649 /* The below doubles as a POSTING_READ */
650 gen6_gt_check_fifodbg(dev_priv);
651}
652
653void
654__gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
655{
656
576 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
657 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
577 /* The below doubles as a POSTING_READ */
578 gen6_gt_check_fifodbg(dev_priv);
579}
580
581void
582gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
583{
584

--- 21 unchanged lines hidden (view full) ---

606 }
607 dev_priv->gt_fifo_count = fifo;
608 }
609 dev_priv->gt_fifo_count--;
610
611 return (ret);
612}
613
658 /* The below doubles as a POSTING_READ */
659 gen6_gt_check_fifodbg(dev_priv);
660}
661
662void
663gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
664{
665

--- 21 unchanged lines hidden (view full) ---

687 }
688 dev_priv->gt_fifo_count = fifo;
689 }
690 dev_priv->gt_fifo_count--;
691
692 return (ret);
693}
694
695void vlv_force_wake_get(struct drm_i915_private *dev_priv)
696{
697 int count;
698
699 count = 0;
700
701 /* Already awake? */
702 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
703 return;
704
705 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
706 POSTING_READ(FORCEWAKE_VLV);
707
708 count = 0;
709 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
710 DELAY(10);
711}
712
713void vlv_force_wake_put(struct drm_i915_private *dev_priv)
714{
715 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
716 /* FIXME: confirm VLV behavior with Punit folks */
717 POSTING_READ(FORCEWAKE_VLV);
718}
719
614static int
615i8xx_do_reset(struct drm_device *dev)
616{
617 struct drm_i915_private *dev_priv = dev->dev_private;
618 int onems;
619
620 if (IS_I85X(dev))
621 return -ENODEV;

--- 26 unchanged lines hidden (view full) ---

648}
649
650static int
651i965_reset_complete(struct drm_device *dev)
652{
653 u8 gdrst;
654
655 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
720static int
721i8xx_do_reset(struct drm_device *dev)
722{
723 struct drm_i915_private *dev_priv = dev->dev_private;
724 int onems;
725
726 if (IS_I85X(dev))
727 return -ENODEV;

--- 26 unchanged lines hidden (view full) ---

754}
755
756static int
757i965_reset_complete(struct drm_device *dev)
758{
759 u8 gdrst;
760
761 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
656 return (gdrst & 0x1);
762 return (gdrst & GRDOM_RESET_ENABLE) == 0;
657}
658
659static int
660i965_do_reset(struct drm_device *dev)
661{
763}
764
765static int
766i965_do_reset(struct drm_device *dev)
767{
768 int ret;
662 u8 gdrst;
663
664 /*
665 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
666 * well as the reset bit (GR/bit 0). Setting the GR bit
667 * triggers the reset; when done, the hardware will clear it.
668 */
669 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
670 pci_write_config(dev->device, I965_GDRST,
671 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE, 1);
672
769 u8 gdrst;
770
771 /*
772 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
773 * well as the reset bit (GR/bit 0). Setting the GR bit
774 * triggers the reset; when done, the hardware will clear it.
775 */
776 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
777 pci_write_config(dev->device, I965_GDRST,
778 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE, 1);
779
673 return (_intel_wait_for(dev, i965_reset_complete(dev), 500, 1,
674 "915rst"));
780 ret = wait_for(i965_reset_complete(dev), 500);
781 if (ret)
782 return ret;
783
784 /* We can't reset render&media without also resetting display ... */
785 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
786 pci_write_config(dev->device, I965_GDRST,
787 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE, 1);
788
789 return wait_for(i965_reset_complete(dev), 500);
675}
676
677static int
678ironlake_do_reset(struct drm_device *dev)
679{
680 struct drm_i915_private *dev_priv;
681 u32 gdrst;
790}
791
792static int
793ironlake_do_reset(struct drm_device *dev)
794{
795 struct drm_i915_private *dev_priv;
796 u32 gdrst;
797 int ret;
682
683 dev_priv = dev->dev_private;
684 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
685 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
798
799 dev_priv = dev->dev_private;
800 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
801 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
686 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
687 return (_intel_wait_for(dev,
688 (I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1) != 0,
689 500, 1, "915rst"));
802 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
803 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
804 if (ret)
805 return ret;
806
807 /* We can't reset render&media without also resetting display ... */
808 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
809 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
810 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
811 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
690}
691
692static int
693gen6_do_reset(struct drm_device *dev)
694{
695 struct drm_i915_private *dev_priv;
696 int ret;
697

--- 10 unchanged lines hidden (view full) ---

708 * for fifo space for the write or forcewake the chip for
709 * the read
710 */
711 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
712
713 /* Spin waiting for the device to ack the reset request */
714 ret = _intel_wait_for(dev,
715 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
812}
813
814static int
815gen6_do_reset(struct drm_device *dev)
816{
817 struct drm_i915_private *dev_priv;
818 int ret;
819

--- 10 unchanged lines hidden (view full) ---

830 * for fifo space for the write or forcewake the chip for
831 * the read
832 */
833 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
834
835 /* Spin waiting for the device to ack the reset request */
836 ret = _intel_wait_for(dev,
837 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
716 500, 1, "915rst");
838 500, 0, "915rst");
717
718 /* If reset with a user forcewake, try to restore, otherwise turn it off */
719 if (dev_priv->forcewake_count)
720 dev_priv->display.force_wake_get(dev_priv);
721 else
722 dev_priv->display.force_wake_put(dev_priv);
723
724 /* Restore fifo count */
725 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
726
727 mtx_unlock(&dev_priv->gt_lock);
728 return (ret);
729}
730
839
840 /* If reset with a user forcewake, try to restore, otherwise turn it off */
841 if (dev_priv->forcewake_count)
842 dev_priv->display.force_wake_get(dev_priv);
843 else
844 dev_priv->display.force_wake_put(dev_priv);
845
846 /* Restore fifo count */
847 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
848
849 mtx_unlock(&dev_priv->gt_lock);
850 return (ret);
851}
852
731int intel_gpu_reset(struct drm_device *dev)
853int
854intel_gpu_reset(struct drm_device *dev)
732{
733 struct drm_i915_private *dev_priv = dev->dev_private;
734 int ret = -ENODEV;
735
736 switch (INTEL_INFO(dev)->gen) {
737 case 7:
738 case 6:
739 ret = gen6_do_reset(dev);

--- 18 unchanged lines hidden (view full) ---

758 "error for simulated gpu hangs\n");
759 ret = 0;
760 }
761 }
762
763 return ret;
764}
765
855{
856 struct drm_i915_private *dev_priv = dev->dev_private;
857 int ret = -ENODEV;
858
859 switch (INTEL_INFO(dev)->gen) {
860 case 7:
861 case 6:
862 ret = gen6_do_reset(dev);

--- 18 unchanged lines hidden (view full) ---

881 "error for simulated gpu hangs\n");
882 ret = 0;
883 }
884 }
885
886 return ret;
887}
888
766int
767i915_reset(struct drm_device *dev)
889int i915_reset(struct drm_device *dev)
768{
769 drm_i915_private_t *dev_priv = dev->dev_private;
890{
891 drm_i915_private_t *dev_priv = dev->dev_private;
770 /*
771 * We really should only reset the display subsystem if we actually
772 * need to
773 */
774 bool need_display = true;
775 int ret;
776
777 if (!i915_try_reset)
778 return (0);
779
780 if (!sx_try_xlock(&dev->dev_struct_lock))
781 return (-EBUSY);
782
892 int ret;
893
894 if (!i915_try_reset)
895 return (0);
896
897 if (!sx_try_xlock(&dev->dev_struct_lock))
898 return (-EBUSY);
899
900 dev_priv->stop_rings = 0;
901
783 i915_gem_reset(dev);
784
785 ret = -ENODEV;
902 i915_gem_reset(dev);
903
904 ret = -ENODEV;
786 if (time_second - dev_priv->last_gpu_reset < 5) {
905 if (time_second - dev_priv->last_gpu_reset < 5)
787 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
906 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
788 } else
907 else
789 ret = intel_gpu_reset(dev);
790
791 dev_priv->last_gpu_reset = time_second;
792 if (ret) {
793 DRM_ERROR("Failed to reset chip.\n");
794 DRM_UNLOCK(dev);
795 return (ret);
796 }
797
798 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
799 !dev_priv->mm.suspended) {
908 ret = intel_gpu_reset(dev);
909
910 dev_priv->last_gpu_reset = time_second;
911 if (ret) {
912 DRM_ERROR("Failed to reset chip.\n");
913 DRM_UNLOCK(dev);
914 return (ret);
915 }
916
917 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
918 !dev_priv->mm.suspended) {
919 struct intel_ring_buffer *ring;
920 int i;
921
800 dev_priv->mm.suspended = 0;
801
802 i915_gem_init_swizzling(dev);
803
922 dev_priv->mm.suspended = 0;
923
924 i915_gem_init_swizzling(dev);
925
804 dev_priv->rings[RCS].init(&dev_priv->rings[RCS]);
805 if (HAS_BSD(dev))
806 dev_priv->rings[VCS].init(&dev_priv->rings[VCS]);
807 if (HAS_BLT(dev))
808 dev_priv->rings[BCS].init(&dev_priv->rings[BCS]);
926 for_each_ring(ring, dev_priv, i)
927 ring->init(ring);
809
810 i915_gem_context_init(dev);
811 i915_gem_init_ppgtt(dev);
812
928
929 i915_gem_context_init(dev);
930 i915_gem_init_ppgtt(dev);
931
932 DRM_UNLOCK(dev);
933
934 if (drm_core_check_feature(dev, DRIVER_MODESET))
935 intel_modeset_init_hw(dev);
936
937 DRM_LOCK(dev);
813 drm_irq_uninstall(dev);
938 drm_irq_uninstall(dev);
814 drm_mode_config_reset(dev);
815 DRM_UNLOCK(dev);
816 drm_irq_install(dev);
939 DRM_UNLOCK(dev);
940 drm_irq_install(dev);
817 DRM_LOCK(dev);
818 }
819 DRM_UNLOCK(dev);
941 } else
942 DRM_UNLOCK(dev);
820
943
821 if (need_display) {
822 sx_xlock(&dev->mode_config.mutex);
823 drm_helper_resume_force_mode(dev);
824 sx_xunlock(&dev->mode_config.mutex);
825 }
826
827 return (0);
828}
829
944 return (0);
945}
946
947/* We give fast paths for the really cool registers */
948#define NEEDS_FORCE_WAKE(dev_priv, reg) \
949 (((dev_priv)->info->gen >= 6) && \
950 ((reg) < 0x40000) && \
951 ((reg) != FORCEWAKE)) && \
952 (!IS_VALLEYVIEW((dev_priv)->dev))
953
830#define __i915_read(x, y) \
831u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
832 u##x val = 0; \
833 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
834 mtx_lock(&dev_priv->gt_lock); \
835 if (dev_priv->forcewake_count == 0) \
836 dev_priv->display.force_wake_get(dev_priv); \
837 val = DRM_READ##y(dev_priv->mmio_map, reg); \

--- 33 unchanged lines hidden --- 		954#define __i915_read(x, y) \
955u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
956 u##x val = 0; \
957 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
958 mtx_lock(&dev_priv->gt_lock); \
959 if (dev_priv->forcewake_count == 0) \
960 dev_priv->display.force_wake_get(dev_priv); \
961 val = DRM_READ##y(dev_priv->mmio_map, reg); \

--- 33 unchanged lines hidden ---