Deleted Added
sdiff udiff text old ( 152909 ) new ( 182080 )
full compact
mga_state.c (152909) mga_state.c (182080)
1/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
3 */
4/*-
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *

--- 20 unchanged lines hidden (view full) ---

29 * Jeff Hartmann <jhartmann@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 *
32 * Rewritten by:
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36#include <sys/cdefs.h>
1/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
3 */
4/*-
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *

--- 20 unchanged lines hidden (view full) ---

29 * Jeff Hartmann <jhartmann@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 *
32 * Rewritten by:
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36#include <sys/cdefs.h>
37__FBSDID("$FreeBSD: head/sys/dev/drm/mga_state.c 152909 2005-11-28 23:13:57Z anholt $");
37__FBSDID("$FreeBSD: head/sys/dev/drm/mga_state.c 182080 2008-08-23 20:59:12Z rnoland $");
38
39#include "dev/drm/drmP.h"
40#include "dev/drm/drm.h"
41#include "dev/drm/mga_drm.h"
42#include "dev/drm/mga_drv.h"
43
44/* ================================================================
45 * DMA hardware state programming functions
46 */
47
48static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
38
39#include "dev/drm/drmP.h"
40#include "dev/drm/drm.h"
41#include "dev/drm/mga_drm.h"
42#include "dev/drm/mga_drv.h"
43
44/* ================================================================
45 * DMA hardware state programming functions
46 */
47
48static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
49 drm_clip_rect_t * box)
49 struct drm_clip_rect * box)
50{
51 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
52 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
53 unsigned int pitch = dev_priv->front_pitch;
54 DMA_LOCALS;
55
56 BEGIN_DMA(2);
57
58 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
59 */
60 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
61 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
62 MGA_LEN + MGA_EXEC, 0x80000000,
63 MGA_DWGCTL, ctx->dwgctl,
64 MGA_LEN + MGA_EXEC, 0x80000000);
65 }
66 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
67 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
50{
51 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
52 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
53 unsigned int pitch = dev_priv->front_pitch;
54 DMA_LOCALS;
55
56 BEGIN_DMA(2);
57
58 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
59 */
60 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
61 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
62 MGA_LEN + MGA_EXEC, 0x80000000,
63 MGA_DWGCTL, ctx->dwgctl,
64 MGA_LEN + MGA_EXEC, 0x80000000);
65 }
66 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
67 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
68 MGA_YTOP, box->y1 * pitch,
69 MGA_YBOT, (box->y2 - 1) * pitch);
68 MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
70
71 ADVANCE_DMA();
72}
73
74static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
75{
76 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
77 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
78 DMA_LOCALS;
79
80 BEGIN_DMA(3);
81
82 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
83 MGA_MACCESS, ctx->maccess,
69
70 ADVANCE_DMA();
71}
72
73static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
74{
75 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
76 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
77 DMA_LOCALS;
78
79 BEGIN_DMA(3);
80
81 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
82 MGA_MACCESS, ctx->maccess,
84 MGA_PLNWT, ctx->plnwt,
85 MGA_DWGCTL, ctx->dwgctl);
83 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
86
87 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
88 MGA_FOGCOL, ctx->fogcolor,
84
85 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
86 MGA_FOGCOL, ctx->fogcolor,
89 MGA_WFLAG, ctx->wflag,
90 MGA_ZORG, dev_priv->depth_offset);
87 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
91
92 DMA_BLOCK(MGA_FCOL, ctx->fcol,
93 MGA_DMAPAD, 0x00000000,
88
89 DMA_BLOCK(MGA_FCOL, ctx->fcol,
90 MGA_DMAPAD, 0x00000000,
94 MGA_DMAPAD, 0x00000000,
95 MGA_DMAPAD, 0x00000000);
91 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
96
97 ADVANCE_DMA();
98}
99
100static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
101{
102 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
103 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;

--- 56 unchanged lines hidden (view full) ---

160}
161
162static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
163{
164 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
165 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
166 DMA_LOCALS;
167
92
93 ADVANCE_DMA();
94}
95
96static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
97{
98 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
99 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;

--- 56 unchanged lines hidden (view full) ---

156}
157
158static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
159{
160 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
161 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
162 DMA_LOCALS;
163
168/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
169/* tex->texctl, tex->texctl2); */
164/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
165/* tex->texctl, tex->texctl2); */
170
171 BEGIN_DMA(6);
172
173 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
174 MGA_TEXCTL, tex->texctl,
175 MGA_TEXFILTER, tex->texfilter,
176 MGA_TEXBORDERCOL, tex->texbordercol);
177

--- 26 unchanged lines hidden (view full) ---

204}
205
206static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
207{
208 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
209 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
210 DMA_LOCALS;
211
166
167 BEGIN_DMA(6);
168
169 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
170 MGA_TEXCTL, tex->texctl,
171 MGA_TEXFILTER, tex->texfilter,
172 MGA_TEXBORDERCOL, tex->texbordercol);
173

--- 26 unchanged lines hidden (view full) ---

200}
201
202static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
203{
204 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
205 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
206 DMA_LOCALS;
207
212/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
213/* tex->texctl, tex->texctl2); */
208/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
209/* tex->texctl, tex->texctl2); */
214
215 BEGIN_DMA(5);
216
217 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
218 MGA_MAP1_ENABLE |
219 MGA_G400_TC2_MAGIC),
220 MGA_TEXCTL, tex->texctl,
221 MGA_TEXFILTER, tex->texfilter,

--- 52 unchanged lines hidden (view full) ---

274}
275
276static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
277{
278 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
279 unsigned int pipe = sarea_priv->warp_pipe;
280 DMA_LOCALS;
281
210
211 BEGIN_DMA(5);
212
213 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
214 MGA_MAP1_ENABLE |
215 MGA_G400_TC2_MAGIC),
216 MGA_TEXCTL, tex->texctl,
217 MGA_TEXFILTER, tex->texfilter,

--- 52 unchanged lines hidden (view full) ---

270}
271
272static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
273{
274 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
275 unsigned int pipe = sarea_priv->warp_pipe;
276 DMA_LOCALS;
277
282/* printk("mga_g400_emit_pipe %x\n", pipe); */
278/* printk("mga_g400_emit_pipe %x\n", pipe); */
283
284 BEGIN_DMA(10);
285
286 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
287 MGA_DMAPAD, 0x00000000,
288 MGA_DMAPAD, 0x00000000,
289 MGA_DMAPAD, 0x00000000);
290

--- 123 unchanged lines hidden (view full) ---

414 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
415
416 if (ctx->dstorg != dev_priv->front_offset &&
417 ctx->dstorg != dev_priv->back_offset) {
418 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
419 ctx->dstorg, dev_priv->front_offset,
420 dev_priv->back_offset);
421 ctx->dstorg = 0;
279
280 BEGIN_DMA(10);
281
282 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
283 MGA_DMAPAD, 0x00000000,
284 MGA_DMAPAD, 0x00000000,
285 MGA_DMAPAD, 0x00000000);
286

--- 123 unchanged lines hidden (view full) ---

410 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
411
412 if (ctx->dstorg != dev_priv->front_offset &&
413 ctx->dstorg != dev_priv->back_offset) {
414 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
415 ctx->dstorg, dev_priv->front_offset,
416 dev_priv->back_offset);
417 ctx->dstorg = 0;
422 return DRM_ERR(EINVAL);
418 return -EINVAL;
423 }
424
425 return 0;
426}
427
428/* Disallow texture reads from PCI space.
429 */
430static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
431{
432 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
433 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
434 unsigned int org;
435
436 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
437
438 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
439 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
440 tex->texorg = 0;
419 }
420
421 return 0;
422}
423
424/* Disallow texture reads from PCI space.
425 */
426static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
427{
428 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
429 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
430 unsigned int org;
431
432 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
433
434 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
435 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
436 tex->texorg = 0;
441 return DRM_ERR(EINVAL);
437 return -EINVAL;
442 }
443
444 return 0;
445}
446
447static int mga_verify_state(drm_mga_private_t * dev_priv)
448{
449 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;

--- 25 unchanged lines hidden (view full) ---

475
476static int mga_verify_iload(drm_mga_private_t * dev_priv,
477 unsigned int dstorg, unsigned int length)
478{
479 if (dstorg < dev_priv->texture_offset ||
480 dstorg + length > (dev_priv->texture_offset +
481 dev_priv->texture_size)) {
482 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
438 }
439
440 return 0;
441}
442
443static int mga_verify_state(drm_mga_private_t * dev_priv)
444{
445 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;

--- 25 unchanged lines hidden (view full) ---

471
472static int mga_verify_iload(drm_mga_private_t * dev_priv,
473 unsigned int dstorg, unsigned int length)
474{
475 if (dstorg < dev_priv->texture_offset ||
476 dstorg + length > (dev_priv->texture_offset +
477 dev_priv->texture_size)) {
478 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
483 return DRM_ERR(EINVAL);
479 return -EINVAL;
484 }
485
486 if (length & MGA_ILOAD_MASK) {
487 DRM_ERROR("*** bad iload length: 0x%x\n",
488 length & MGA_ILOAD_MASK);
480 }
481
482 if (length & MGA_ILOAD_MASK) {
483 DRM_ERROR("*** bad iload length: 0x%x\n",
484 length & MGA_ILOAD_MASK);
489 return DRM_ERR(EINVAL);
485 return -EINVAL;
490 }
491
492 return 0;
493}
494
495static int mga_verify_blit(drm_mga_private_t * dev_priv,
496 unsigned int srcorg, unsigned int dstorg)
497{
498 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
499 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
500 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
486 }
487
488 return 0;
489}
490
491static int mga_verify_blit(drm_mga_private_t * dev_priv,
492 unsigned int srcorg, unsigned int dstorg)
493{
494 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
495 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
496 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
501 return DRM_ERR(EINVAL);
497 return -EINVAL;
502 }
503 return 0;
504}
505
506/* ================================================================
507 *
508 */
509
498 }
499 return 0;
500}
501
502/* ================================================================
503 *
504 */
505
510static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear)
506static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear)
511{
512 drm_mga_private_t *dev_priv = dev->dev_private;
513 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
514 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
507{
508 drm_mga_private_t *dev_priv = dev->dev_private;
509 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
510 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
515 drm_clip_rect_t *pbox = sarea_priv->boxes;
511 struct drm_clip_rect *pbox = sarea_priv->boxes;
516 int nbox = sarea_priv->nbox;
517 int i;
518 DMA_LOCALS;
519 DRM_DEBUG("\n");
520
521 BEGIN_DMA(1);
522
523 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
524 MGA_DMAPAD, 0x00000000,
525 MGA_DWGSYNC, 0x00007100,
526 MGA_DWGSYNC, 0x00007000);
527
528 ADVANCE_DMA();
529
530 for (i = 0; i < nbox; i++) {
512 int nbox = sarea_priv->nbox;
513 int i;
514 DMA_LOCALS;
515 DRM_DEBUG("\n");
516
517 BEGIN_DMA(1);
518
519 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
520 MGA_DMAPAD, 0x00000000,
521 MGA_DWGSYNC, 0x00007100,
522 MGA_DWGSYNC, 0x00007000);
523
524 ADVANCE_DMA();
525
526 for (i = 0; i < nbox; i++) {
531 drm_clip_rect_t *box = &pbox[i];
527 struct drm_clip_rect *box = &pbox[i];
532 u32 height = box->y2 - box->y1;
533
534 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
535 box->x1, box->y1, box->x2, box->y2);
536
537 if (clear->flags & MGA_FRONT) {
538 BEGIN_DMA(2);
539

--- 52 unchanged lines hidden (view full) ---

592 MGA_PLNWT, ctx->plnwt,
593 MGA_DWGCTL, ctx->dwgctl);
594
595 ADVANCE_DMA();
596
597 FLUSH_DMA();
598}
599
528 u32 height = box->y2 - box->y1;
529
530 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
531 box->x1, box->y1, box->x2, box->y2);
532
533 if (clear->flags & MGA_FRONT) {
534 BEGIN_DMA(2);
535

--- 52 unchanged lines hidden (view full) ---

588 MGA_PLNWT, ctx->plnwt,
589 MGA_DWGCTL, ctx->dwgctl);
590
591 ADVANCE_DMA();
592
593 FLUSH_DMA();
594}
595
600static void mga_dma_dispatch_swap(drm_device_t * dev)
596static void mga_dma_dispatch_swap(struct drm_device * dev)
601{
602 drm_mga_private_t *dev_priv = dev->dev_private;
603 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
604 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
597{
598 drm_mga_private_t *dev_priv = dev->dev_private;
599 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
600 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
605 drm_clip_rect_t *pbox = sarea_priv->boxes;
601 struct drm_clip_rect *pbox = sarea_priv->boxes;
606 int nbox = sarea_priv->nbox;
607 int i;
608 DMA_LOCALS;
609 DRM_DEBUG("\n");
610
611 sarea_priv->last_frame.head = dev_priv->prim.tail;
612 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
613

--- 10 unchanged lines hidden (view full) ---

624 MGA_AR5, dev_priv->front_pitch);
625
626 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
627 MGA_DMAPAD, 0x00000000,
628 MGA_PLNWT, 0xffffffff,
629 MGA_DWGCTL, MGA_DWGCTL_COPY);
630
631 for (i = 0; i < nbox; i++) {
602 int nbox = sarea_priv->nbox;
603 int i;
604 DMA_LOCALS;
605 DRM_DEBUG("\n");
606
607 sarea_priv->last_frame.head = dev_priv->prim.tail;
608 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
609

--- 10 unchanged lines hidden (view full) ---

620 MGA_AR5, dev_priv->front_pitch);
621
622 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
623 MGA_DMAPAD, 0x00000000,
624 MGA_PLNWT, 0xffffffff,
625 MGA_DWGCTL, MGA_DWGCTL_COPY);
626
627 for (i = 0; i < nbox; i++) {
632 drm_clip_rect_t *box = &pbox[i];
628 struct drm_clip_rect *box = &pbox[i];
633 u32 height = box->y2 - box->y1;
634 u32 start = box->y1 * dev_priv->front_pitch;
635
636 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
637 box->x1, box->y1, box->x2, box->y2);
638
639 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
640 MGA_AR3, start + box->x1,

--- 5 unchanged lines hidden (view full) ---

646 MGA_PLNWT, ctx->plnwt,
647 MGA_SRCORG, dev_priv->front_offset,
648 MGA_DWGCTL, ctx->dwgctl);
649
650 ADVANCE_DMA();
651
652 FLUSH_DMA();
653
629 u32 height = box->y2 - box->y1;
630 u32 start = box->y1 * dev_priv->front_pitch;
631
632 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
633 box->x1, box->y1, box->x2, box->y2);
634
635 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
636 MGA_AR3, start + box->x1,

--- 5 unchanged lines hidden (view full) ---

642 MGA_PLNWT, ctx->plnwt,
643 MGA_SRCORG, dev_priv->front_offset,
644 MGA_DWGCTL, ctx->dwgctl);
645
646 ADVANCE_DMA();
647
648 FLUSH_DMA();
649
654 DRM_DEBUG("%s... done.\n", __FUNCTION__);
650 DRM_DEBUG("... done.\n");
655}
656
651}
652
657static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
653static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
658{
659 drm_mga_private_t *dev_priv = dev->dev_private;
660 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
661 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
662 u32 address = (u32) buf->bus_address;
663 u32 length = (u32) buf->used;
664 int i = 0;
665 DMA_LOCALS;
654{
655 drm_mga_private_t *dev_priv = dev->dev_private;
656 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
657 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
658 u32 address = (u32) buf->bus_address;
659 u32 length = (u32) buf->used;
660 int i = 0;
661 DMA_LOCALS;
666 DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
662 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
667
668 if (buf->used) {
669 buf_priv->dispatched = 1;
670
671 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
672
673 do {
674 if (i < sarea_priv->nbox) {

--- 21 unchanged lines hidden (view full) ---

696 buf_priv->dispatched = 0;
697
698 mga_freelist_put(dev, buf);
699 }
700
701 FLUSH_DMA();
702}
703
663
664 if (buf->used) {
665 buf_priv->dispatched = 1;
666
667 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
668
669 do {
670 if (i < sarea_priv->nbox) {

--- 21 unchanged lines hidden (view full) ---

692 buf_priv->dispatched = 0;
693
694 mga_freelist_put(dev, buf);
695 }
696
697 FLUSH_DMA();
698}
699
704static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf,
700static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf,
705 unsigned int start, unsigned int end)
706{
707 drm_mga_private_t *dev_priv = dev->dev_private;
708 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
709 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
710 u32 address = (u32) buf->bus_address;
711 int i = 0;
712 DMA_LOCALS;
701 unsigned int start, unsigned int end)
702{
703 drm_mga_private_t *dev_priv = dev->dev_private;
704 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
705 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
706 u32 address = (u32) buf->bus_address;
707 int i = 0;
708 DMA_LOCALS;
713 DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
709 DRM_DEBUG("buf=%d start=%d end=%d\n", buf->idx, start, end);
714
715 if (start != end) {
716 buf_priv->dispatched = 1;
717
718 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
719
720 do {
721 if (i < sarea_priv->nbox) {

--- 23 unchanged lines hidden (view full) ---

745 }
746
747 FLUSH_DMA();
748}
749
750/* This copies a 64 byte aligned agp region to the frambuffer with a
751 * standard blit, the ioctl needs to do checking.
752 */
710
711 if (start != end) {
712 buf_priv->dispatched = 1;
713
714 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
715
716 do {
717 if (i < sarea_priv->nbox) {

--- 23 unchanged lines hidden (view full) ---

741 }
742
743 FLUSH_DMA();
744}
745
746/* This copies a 64 byte aligned agp region to the frambuffer with a
747 * standard blit, the ioctl needs to do checking.
748 */
753static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf,
749static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf,
754 unsigned int dstorg, unsigned int length)
755{
756 drm_mga_private_t *dev_priv = dev->dev_private;
757 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
758 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
759 u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
760 u32 y2;
761 DMA_LOCALS;

--- 36 unchanged lines hidden (view full) ---

798 buf->used = 0;
799 buf_priv->dispatched = 0;
800
801 mga_freelist_put(dev, buf);
802
803 FLUSH_DMA();
804}
805
750 unsigned int dstorg, unsigned int length)
751{
752 drm_mga_private_t *dev_priv = dev->dev_private;
753 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
754 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
755 u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
756 u32 y2;
757 DMA_LOCALS;

--- 36 unchanged lines hidden (view full) ---

794 buf->used = 0;
795 buf_priv->dispatched = 0;
796
797 mga_freelist_put(dev, buf);
798
799 FLUSH_DMA();
800}
801
806static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit)
802static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit)
807{
808 drm_mga_private_t *dev_priv = dev->dev_private;
809 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
810 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
803{
804 drm_mga_private_t *dev_priv = dev->dev_private;
805 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
806 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
811 drm_clip_rect_t *pbox = sarea_priv->boxes;
807 struct drm_clip_rect *pbox = sarea_priv->boxes;
812 int nbox = sarea_priv->nbox;
813 u32 scandir = 0, i;
814 DMA_LOCALS;
815 DRM_DEBUG("\n");
816
817 BEGIN_DMA(4 + nbox);
818
819 DMA_BLOCK(MGA_DMAPAD, 0x00000000,

--- 43 unchanged lines hidden (view full) ---

863
864 ADVANCE_DMA();
865}
866
867/* ================================================================
868 *
869 */
870
808 int nbox = sarea_priv->nbox;
809 u32 scandir = 0, i;
810 DMA_LOCALS;
811 DRM_DEBUG("\n");
812
813 BEGIN_DMA(4 + nbox);
814
815 DMA_BLOCK(MGA_DMAPAD, 0x00000000,

--- 43 unchanged lines hidden (view full) ---

859
860 ADVANCE_DMA();
861}
862
863/* ================================================================
864 *
865 */
866
871static int mga_dma_clear(DRM_IOCTL_ARGS)
867static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
872{
868{
873 DRM_DEVICE;
874 drm_mga_private_t *dev_priv = dev->dev_private;
875 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
869 drm_mga_private_t *dev_priv = dev->dev_private;
870 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
876 drm_mga_clear_t clear;
871 drm_mga_clear_t *clear = data;
877
872
878 LOCK_TEST_WITH_RETURN(dev, filp);
873 LOCK_TEST_WITH_RETURN(dev, file_priv);
879
874
880 DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data,
881 sizeof(clear));
882
883 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
884 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
885
886 WRAP_TEST_WITH_RETURN(dev_priv);
887
875 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
876 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
877
878 WRAP_TEST_WITH_RETURN(dev_priv);
879
888 mga_dma_dispatch_clear(dev, &clear);
880 mga_dma_dispatch_clear(dev, clear);
889
890 /* Make sure we restore the 3D state next time.
891 */
892 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
893
894 return 0;
895}
896
881
882 /* Make sure we restore the 3D state next time.
883 */
884 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
885
886 return 0;
887}
888
897static int mga_dma_swap(DRM_IOCTL_ARGS)
889static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
898{
890{
899 DRM_DEVICE;
900 drm_mga_private_t *dev_priv = dev->dev_private;
901 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
902
891 drm_mga_private_t *dev_priv = dev->dev_private;
892 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
893
903 LOCK_TEST_WITH_RETURN(dev, filp);
894 LOCK_TEST_WITH_RETURN(dev, file_priv);
904
905 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
906 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
907
908 WRAP_TEST_WITH_RETURN(dev_priv);
909
910 mga_dma_dispatch_swap(dev);
911
912 /* Make sure we restore the 3D state next time.
913 */
914 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
915
916 return 0;
917}
918
895
896 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
897 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
898
899 WRAP_TEST_WITH_RETURN(dev_priv);
900
901 mga_dma_dispatch_swap(dev);
902
903 /* Make sure we restore the 3D state next time.
904 */
905 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
906
907 return 0;
908}
909
919static int mga_dma_vertex(DRM_IOCTL_ARGS)
910static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
920{
911{
921 DRM_DEVICE;
922 drm_mga_private_t *dev_priv = dev->dev_private;
912 drm_mga_private_t *dev_priv = dev->dev_private;
923 drm_device_dma_t *dma = dev->dma;
924 drm_buf_t *buf;
913 struct drm_device_dma *dma = dev->dma;
914 struct drm_buf *buf;
925 drm_mga_buf_priv_t *buf_priv;
915 drm_mga_buf_priv_t *buf_priv;
926 drm_mga_vertex_t vertex;
916 drm_mga_vertex_t *vertex = data;
927
917
928 LOCK_TEST_WITH_RETURN(dev, filp);
918 LOCK_TEST_WITH_RETURN(dev, file_priv);
929
919
930 DRM_COPY_FROM_USER_IOCTL(vertex,
931 (drm_mga_vertex_t __user *) data,
932 sizeof(vertex));
933
934 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
935 return DRM_ERR(EINVAL);
936 buf = dma->buflist[vertex.idx];
920 if (vertex->idx < 0 || vertex->idx > dma->buf_count)
921 return -EINVAL;
922 buf = dma->buflist[vertex->idx];
937 buf_priv = buf->dev_private;
938
923 buf_priv = buf->dev_private;
924
939 buf->used = vertex.used;
940 buf_priv->discard = vertex.discard;
925 buf->used = vertex->used;
926 buf_priv->discard = vertex->discard;
941
942 if (!mga_verify_state(dev_priv)) {
927
928 if (!mga_verify_state(dev_priv)) {
943 if (vertex.discard) {
929 if (vertex->discard) {
944 if (buf_priv->dispatched == 1)
945 AGE_BUFFER(buf_priv);
946 buf_priv->dispatched = 0;
947 mga_freelist_put(dev, buf);
948 }
930 if (buf_priv->dispatched == 1)
931 AGE_BUFFER(buf_priv);
932 buf_priv->dispatched = 0;
933 mga_freelist_put(dev, buf);
934 }
949 return DRM_ERR(EINVAL);
935 return -EINVAL;
950 }
951
952 WRAP_TEST_WITH_RETURN(dev_priv);
953
954 mga_dma_dispatch_vertex(dev, buf);
955
956 return 0;
957}
958
936 }
937
938 WRAP_TEST_WITH_RETURN(dev_priv);
939
940 mga_dma_dispatch_vertex(dev, buf);
941
942 return 0;
943}
944
959static int mga_dma_indices(DRM_IOCTL_ARGS)
945static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
960{
946{
961 DRM_DEVICE;
962 drm_mga_private_t *dev_priv = dev->dev_private;
947 drm_mga_private_t *dev_priv = dev->dev_private;
963 drm_device_dma_t *dma = dev->dma;
964 drm_buf_t *buf;
948 struct drm_device_dma *dma = dev->dma;
949 struct drm_buf *buf;
965 drm_mga_buf_priv_t *buf_priv;
950 drm_mga_buf_priv_t *buf_priv;
966 drm_mga_indices_t indices;
951 drm_mga_indices_t *indices = data;
967
952
968 LOCK_TEST_WITH_RETURN(dev, filp);
953 LOCK_TEST_WITH_RETURN(dev, file_priv);
969
954
970 DRM_COPY_FROM_USER_IOCTL(indices,
971 (drm_mga_indices_t __user *) data,
972 sizeof(indices));
955 if (indices->idx < 0 || indices->idx > dma->buf_count)
956 return -EINVAL;
973
957
974 if (indices.idx < 0 || indices.idx > dma->buf_count)
975 return DRM_ERR(EINVAL);
976
977 buf = dma->buflist[indices.idx];
958 buf = dma->buflist[indices->idx];
978 buf_priv = buf->dev_private;
979
959 buf_priv = buf->dev_private;
960
980 buf_priv->discard = indices.discard;
961 buf_priv->discard = indices->discard;
981
982 if (!mga_verify_state(dev_priv)) {
962
963 if (!mga_verify_state(dev_priv)) {
983 if (indices.discard) {
964 if (indices->discard) {
984 if (buf_priv->dispatched == 1)
985 AGE_BUFFER(buf_priv);
986 buf_priv->dispatched = 0;
987 mga_freelist_put(dev, buf);
988 }
965 if (buf_priv->dispatched == 1)
966 AGE_BUFFER(buf_priv);
967 buf_priv->dispatched = 0;
968 mga_freelist_put(dev, buf);
969 }
989 return DRM_ERR(EINVAL);
970 return -EINVAL;
990 }
991
992 WRAP_TEST_WITH_RETURN(dev_priv);
993
971 }
972
973 WRAP_TEST_WITH_RETURN(dev_priv);
974
994 mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
975 mga_dma_dispatch_indices(dev, buf, indices->start, indices->end);
995
996 return 0;
997}
998
976
977 return 0;
978}
979
999static int mga_dma_iload(DRM_IOCTL_ARGS)
980static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv)
1000{
981{
1001 DRM_DEVICE;
1002 drm_device_dma_t *dma = dev->dma;
982 struct drm_device_dma *dma = dev->dma;
1003 drm_mga_private_t *dev_priv = dev->dev_private;
983 drm_mga_private_t *dev_priv = dev->dev_private;
1004 drm_buf_t *buf;
984 struct drm_buf *buf;
1005 drm_mga_buf_priv_t *buf_priv;
985 drm_mga_buf_priv_t *buf_priv;
1006 drm_mga_iload_t iload;
986 drm_mga_iload_t *iload = data;
1007 DRM_DEBUG("\n");
1008
987 DRM_DEBUG("\n");
988
1009 LOCK_TEST_WITH_RETURN(dev, filp);
989 LOCK_TEST_WITH_RETURN(dev, file_priv);
1010
990
1011 DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data,
1012 sizeof(iload));
1013
1014#if 0
1015 if (mga_do_wait_for_idle(dev_priv) < 0) {
1016 if (MGA_DMA_DEBUG)
991#if 0
992 if (mga_do_wait_for_idle(dev_priv) < 0) {
993 if (MGA_DMA_DEBUG)
1017 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1018 return DRM_ERR(EBUSY);
994 DRM_INFO("-EBUSY\n");
995 return -EBUSY;
1019 }
1020#endif
996 }
997#endif
1021 if (iload.idx < 0 || iload.idx > dma->buf_count)
1022 return DRM_ERR(EINVAL);
998 if (iload->idx < 0 || iload->idx > dma->buf_count)
999 return -EINVAL;
1023
1000
1024 buf = dma->buflist[iload.idx];
1001 buf = dma->buflist[iload->idx];
1025 buf_priv = buf->dev_private;
1026
1002 buf_priv = buf->dev_private;
1003
1027 if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) {
1004 if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) {
1028 mga_freelist_put(dev, buf);
1005 mga_freelist_put(dev, buf);
1029 return DRM_ERR(EINVAL);
1006 return -EINVAL;
1030 }
1031
1032 WRAP_TEST_WITH_RETURN(dev_priv);
1033
1007 }
1008
1009 WRAP_TEST_WITH_RETURN(dev_priv);
1010
1034 mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length);
1011 mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length);
1035
1036 /* Make sure we restore the 3D state next time.
1037 */
1038 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1039
1040 return 0;
1041}
1042
1012
1013 /* Make sure we restore the 3D state next time.
1014 */
1015 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1016
1017 return 0;
1018}
1019
1043static int mga_dma_blit(DRM_IOCTL_ARGS)
1020static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1044{
1021{
1045 DRM_DEVICE;
1046 drm_mga_private_t *dev_priv = dev->dev_private;
1047 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1022 drm_mga_private_t *dev_priv = dev->dev_private;
1023 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1048 drm_mga_blit_t blit;
1024 drm_mga_blit_t *blit = data;
1049 DRM_DEBUG("\n");
1050
1025 DRM_DEBUG("\n");
1026
1051 LOCK_TEST_WITH_RETURN(dev, filp);
1027 LOCK_TEST_WITH_RETURN(dev, file_priv);
1052
1028
1053 DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data,
1054 sizeof(blit));
1055
1056 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1057 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1058
1029 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1030 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1031
1059 if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg))
1060 return DRM_ERR(EINVAL);
1032 if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg))
1033 return -EINVAL;
1061
1062 WRAP_TEST_WITH_RETURN(dev_priv);
1063
1034
1035 WRAP_TEST_WITH_RETURN(dev_priv);
1036
1064 mga_dma_dispatch_blit(dev, &blit);
1037 mga_dma_dispatch_blit(dev, blit);
1065
1066 /* Make sure we restore the 3D state next time.
1067 */
1068 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1069
1070 return 0;
1071}
1072
1038
1039 /* Make sure we restore the 3D state next time.
1040 */
1041 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1042
1043 return 0;
1044}
1045
1073static int mga_getparam(DRM_IOCTL_ARGS)
1046static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1074{
1047{
1075 DRM_DEVICE;
1076 drm_mga_private_t *dev_priv = dev->dev_private;
1048 drm_mga_private_t *dev_priv = dev->dev_private;
1077 drm_mga_getparam_t param;
1049 drm_mga_getparam_t *param = data;
1078 int value;
1079
1080 if (!dev_priv) {
1050 int value;
1051
1052 if (!dev_priv) {
1081 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1082 return DRM_ERR(EINVAL);
1053 DRM_ERROR("called with no initialization\n");
1054 return -EINVAL;
1083 }
1084
1055 }
1056
1085 DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data,
1086 sizeof(param));
1087
1088 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1089
1057 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1058
1090 switch (param.param) {
1059 switch (param->param) {
1091 case MGA_PARAM_IRQ_NR:
1092 value = dev->irq;
1093 break;
1094 case MGA_PARAM_CARD_TYPE:
1095 value = dev_priv->chipset;
1096 break;
1097 default:
1060 case MGA_PARAM_IRQ_NR:
1061 value = dev->irq;
1062 break;
1063 case MGA_PARAM_CARD_TYPE:
1064 value = dev_priv->chipset;
1065 break;
1066 default:
1098 return DRM_ERR(EINVAL);
1067 return -EINVAL;
1099 }
1100
1068 }
1069
1101 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1070 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1102 DRM_ERROR("copy_to_user\n");
1071 DRM_ERROR("copy_to_user\n");
1103 return DRM_ERR(EFAULT);
1072 return -EFAULT;
1104 }
1105
1106 return 0;
1107}
1108
1073 }
1074
1075 return 0;
1076}
1077
1109static int mga_set_fence(DRM_IOCTL_ARGS)
1078static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1110{
1079{
1111 DRM_DEVICE;
1112 drm_mga_private_t *dev_priv = dev->dev_private;
1080 drm_mga_private_t *dev_priv = dev->dev_private;
1113 u32 temp;
1081 u32 *fence = data;
1114 DMA_LOCALS;
1115
1116 if (!dev_priv) {
1082 DMA_LOCALS;
1083
1084 if (!dev_priv) {
1117 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1118 return DRM_ERR(EINVAL);
1085 DRM_ERROR("called with no initialization\n");
1086 return -EINVAL;
1119 }
1120
1121 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1122
1087 }
1088
1089 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1090
1123 /* I would normal do this assignment in the declaration of temp,
1091 /* I would normal do this assignment in the declaration of fence,
1124 * but dev_priv may be NULL.
1125 */
1126
1092 * but dev_priv may be NULL.
1093 */
1094
1127 temp = dev_priv->next_fence_to_post;
1095 *fence = dev_priv->next_fence_to_post;
1128 dev_priv->next_fence_to_post++;
1129
1130 BEGIN_DMA(1);
1131 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1132 MGA_DMAPAD, 0x00000000,
1133 MGA_DMAPAD, 0x00000000,
1134 MGA_SOFTRAP, 0x00000000);
1135 ADVANCE_DMA();
1136
1096 dev_priv->next_fence_to_post++;
1097
1098 BEGIN_DMA(1);
1099 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1100 MGA_DMAPAD, 0x00000000,
1101 MGA_DMAPAD, 0x00000000,
1102 MGA_SOFTRAP, 0x00000000);
1103 ADVANCE_DMA();
1104
1137 DRM_COPY_TO_USER_IOCTL((u32 __user *)data, temp, sizeof(u32));
1138
1139 return 0;
1140}
1141
1105 return 0;
1106}
1107
1142static int mga_wait_fence(DRM_IOCTL_ARGS)
1108static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1143{
1109{
1144 DRM_DEVICE;
1145 drm_mga_private_t *dev_priv = dev->dev_private;
1110 drm_mga_private_t *dev_priv = dev->dev_private;
1146 u32 fence;
1111 u32 *fence = data;
1147
1148 if (!dev_priv) {
1112
1113 if (!dev_priv) {
1149 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1150 return DRM_ERR(EINVAL);
1114 DRM_ERROR("called with no initialization\n");
1115 return -EINVAL;
1151 }
1152
1116 }
1117
1153 DRM_COPY_FROM_USER_IOCTL(fence, (u32 __user *) data, sizeof(u32));
1154
1155 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1156
1118 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1119
1157 mga_driver_fence_wait(dev, & fence);
1120 mga_driver_fence_wait(dev, fence);
1158
1121
1159 DRM_COPY_TO_USER_IOCTL((u32 __user *)data, fence, sizeof(u32));
1160
1161 return 0;
1162}
1163
1122 return 0;
1123}
1124
1164drm_ioctl_desc_t mga_ioctls[] = {
1165 [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1166 [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, DRM_AUTH},
1167 [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, DRM_AUTH},
1168 [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, DRM_AUTH},
1169 [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, DRM_AUTH},
1170 [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, DRM_AUTH},
1171 [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, DRM_AUTH},
1172 [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, DRM_AUTH},
1173 [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, DRM_AUTH},
1174 [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, DRM_AUTH},
1175 [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, DRM_AUTH},
1176 [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, DRM_AUTH},
1177 [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1125struct drm_ioctl_desc mga_ioctls[] = {
1126 DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1127 DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH),
1128 DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH),
1129 DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH),
1130 DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH),
1131 DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH),
1132 DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH),
1133 DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH),
1134 DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH),
1135 DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH),
1136 DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH),
1137 DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH),
1138 DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1178
1179};
1180
1181int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);
1139
1140};
1141
1142int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);