1/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
3 */
4/*-
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *
--- 20 unchanged lines hidden (view full) ---
29 * Jeff Hartmann <jhartmann@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 *
32 * Rewritten by:
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36#include <sys/cdefs.h>
37__FBSDID("$FreeBSD: head/sys/dev/drm/mga_state.c 182080 2008-08-23 20:59:12Z rnoland $");
38
39#include "dev/drm/drmP.h"
40#include "dev/drm/drm.h"
41#include "dev/drm/mga_drm.h"
42#include "dev/drm/mga_drv.h"
43
44/* ================================================================
45 * DMA hardware state programming functions
46 */
47
48static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
49 struct drm_clip_rect * box)
50{
51 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
52 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
53 unsigned int pitch = dev_priv->front_pitch;
54 DMA_LOCALS;
55
56 BEGIN_DMA(2);
57
58 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
59 */
60 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
61 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
62 MGA_LEN + MGA_EXEC, 0x80000000,
63 MGA_DWGCTL, ctx->dwgctl,
64 MGA_LEN + MGA_EXEC, 0x80000000);
65 }
66 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
67 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
68 MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
69
70 ADVANCE_DMA();
71}
72
73static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
74{
75 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
76 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
77 DMA_LOCALS;
78
79 BEGIN_DMA(3);
80
81 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
82 MGA_MACCESS, ctx->maccess,
83 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
84
85 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
86 MGA_FOGCOL, ctx->fogcolor,
87 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
88
89 DMA_BLOCK(MGA_FCOL, ctx->fcol,
90 MGA_DMAPAD, 0x00000000,
91 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
92
93 ADVANCE_DMA();
94}
95
96static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
97{
98 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
99 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
--- 56 unchanged lines hidden (view full) ---
156}
157
158static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
159{
160 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
161 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
162 DMA_LOCALS;
163
164/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
165/* tex->texctl, tex->texctl2); */
166
167 BEGIN_DMA(6);
168
169 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
170 MGA_TEXCTL, tex->texctl,
171 MGA_TEXFILTER, tex->texfilter,
172 MGA_TEXBORDERCOL, tex->texbordercol);
173
--- 26 unchanged lines hidden (view full) ---
200}
201
202static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
203{
204 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
205 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
206 DMA_LOCALS;
207
208/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
209/* tex->texctl, tex->texctl2); */
210
211 BEGIN_DMA(5);
212
213 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
214 MGA_MAP1_ENABLE |
215 MGA_G400_TC2_MAGIC),
216 MGA_TEXCTL, tex->texctl,
217 MGA_TEXFILTER, tex->texfilter,
--- 52 unchanged lines hidden (view full) ---
270}
271
272static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
273{
274 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
275 unsigned int pipe = sarea_priv->warp_pipe;
276 DMA_LOCALS;
277
278/* printk("mga_g400_emit_pipe %x\n", pipe); */
279
280 BEGIN_DMA(10);
281
282 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
283 MGA_DMAPAD, 0x00000000,
284 MGA_DMAPAD, 0x00000000,
285 MGA_DMAPAD, 0x00000000);
286
--- 123 unchanged lines hidden (view full) ---
410 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
411
412 if (ctx->dstorg != dev_priv->front_offset &&
413 ctx->dstorg != dev_priv->back_offset) {
414 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
415 ctx->dstorg, dev_priv->front_offset,
416 dev_priv->back_offset);
417 ctx->dstorg = 0;
418 return -EINVAL;
419 }
420
421 return 0;
422}
423
424/* Disallow texture reads from PCI space.
425 */
426static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
427{
428 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
429 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
430 unsigned int org;
431
432 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
433
434 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
435 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
436 tex->texorg = 0;
437 return -EINVAL;
438 }
439
440 return 0;
441}
442
443static int mga_verify_state(drm_mga_private_t * dev_priv)
444{
445 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
--- 25 unchanged lines hidden (view full) ---
471
472static int mga_verify_iload(drm_mga_private_t * dev_priv,
473 unsigned int dstorg, unsigned int length)
474{
475 if (dstorg < dev_priv->texture_offset ||
476 dstorg + length > (dev_priv->texture_offset +
477 dev_priv->texture_size)) {
478 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
479 return -EINVAL;
480 }
481
482 if (length & MGA_ILOAD_MASK) {
483 DRM_ERROR("*** bad iload length: 0x%x\n",
484 length & MGA_ILOAD_MASK);
485 return -EINVAL;
486 }
487
488 return 0;
489}
490
491static int mga_verify_blit(drm_mga_private_t * dev_priv,
492 unsigned int srcorg, unsigned int dstorg)
493{
494 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
495 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
496 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
497 return -EINVAL;
498 }
499 return 0;
500}
501
502/* ================================================================
503 *
504 */
505
506static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear)
507{
508 drm_mga_private_t *dev_priv = dev->dev_private;
509 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
510 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
511 struct drm_clip_rect *pbox = sarea_priv->boxes;
512 int nbox = sarea_priv->nbox;
513 int i;
514 DMA_LOCALS;
515 DRM_DEBUG("\n");
516
517 BEGIN_DMA(1);
518
519 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
520 MGA_DMAPAD, 0x00000000,
521 MGA_DWGSYNC, 0x00007100,
522 MGA_DWGSYNC, 0x00007000);
523
524 ADVANCE_DMA();
525
526 for (i = 0; i < nbox; i++) {
527 struct drm_clip_rect *box = &pbox[i];
528 u32 height = box->y2 - box->y1;
529
530 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
531 box->x1, box->y1, box->x2, box->y2);
532
533 if (clear->flags & MGA_FRONT) {
534 BEGIN_DMA(2);
535
--- 52 unchanged lines hidden (view full) ---
588 MGA_PLNWT, ctx->plnwt,
589 MGA_DWGCTL, ctx->dwgctl);
590
591 ADVANCE_DMA();
592
593 FLUSH_DMA();
594}
595
596static void mga_dma_dispatch_swap(struct drm_device * dev)
597{
598 drm_mga_private_t *dev_priv = dev->dev_private;
599 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
600 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
601 struct drm_clip_rect *pbox = sarea_priv->boxes;
602 int nbox = sarea_priv->nbox;
603 int i;
604 DMA_LOCALS;
605 DRM_DEBUG("\n");
606
607 sarea_priv->last_frame.head = dev_priv->prim.tail;
608 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
609
--- 10 unchanged lines hidden (view full) ---
620 MGA_AR5, dev_priv->front_pitch);
621
622 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
623 MGA_DMAPAD, 0x00000000,
624 MGA_PLNWT, 0xffffffff,
625 MGA_DWGCTL, MGA_DWGCTL_COPY);
626
627 for (i = 0; i < nbox; i++) {
628 struct drm_clip_rect *box = &pbox[i];
629 u32 height = box->y2 - box->y1;
630 u32 start = box->y1 * dev_priv->front_pitch;
631
632 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
633 box->x1, box->y1, box->x2, box->y2);
634
635 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
636 MGA_AR3, start + box->x1,
--- 5 unchanged lines hidden (view full) ---
642 MGA_PLNWT, ctx->plnwt,
643 MGA_SRCORG, dev_priv->front_offset,
644 MGA_DWGCTL, ctx->dwgctl);
645
646 ADVANCE_DMA();
647
648 FLUSH_DMA();
649
650 DRM_DEBUG("... done.\n");
651}
652
653static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
654{
655 drm_mga_private_t *dev_priv = dev->dev_private;
656 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
657 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
658 u32 address = (u32) buf->bus_address;
659 u32 length = (u32) buf->used;
660 int i = 0;
661 DMA_LOCALS;
662 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
663
664 if (buf->used) {
665 buf_priv->dispatched = 1;
666
667 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
668
669 do {
670 if (i < sarea_priv->nbox) {
--- 21 unchanged lines hidden (view full) ---
692 buf_priv->dispatched = 0;
693
694 mga_freelist_put(dev, buf);
695 }
696
697 FLUSH_DMA();
698}
699
700static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf,
701 unsigned int start, unsigned int end)
702{
703 drm_mga_private_t *dev_priv = dev->dev_private;
704 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
705 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
706 u32 address = (u32) buf->bus_address;
707 int i = 0;
708 DMA_LOCALS;
709 DRM_DEBUG("buf=%d start=%d end=%d\n", buf->idx, start, end);
710
711 if (start != end) {
712 buf_priv->dispatched = 1;
713
714 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
715
716 do {
717 if (i < sarea_priv->nbox) {
--- 23 unchanged lines hidden (view full) ---
741 }
742
743 FLUSH_DMA();
744}
745
746/* This copies a 64 byte aligned agp region to the frambuffer with a
747 * standard blit, the ioctl needs to do checking.
748 */
749static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf,
750 unsigned int dstorg, unsigned int length)
751{
752 drm_mga_private_t *dev_priv = dev->dev_private;
753 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
754 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
755 u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
756 u32 y2;
757 DMA_LOCALS;
--- 36 unchanged lines hidden (view full) ---
794 buf->used = 0;
795 buf_priv->dispatched = 0;
796
797 mga_freelist_put(dev, buf);
798
799 FLUSH_DMA();
800}
801
802static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit)
803{
804 drm_mga_private_t *dev_priv = dev->dev_private;
805 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
806 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
807 struct drm_clip_rect *pbox = sarea_priv->boxes;
808 int nbox = sarea_priv->nbox;
809 u32 scandir = 0, i;
810 DMA_LOCALS;
811 DRM_DEBUG("\n");
812
813 BEGIN_DMA(4 + nbox);
814
815 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
--- 43 unchanged lines hidden (view full) ---
859
860 ADVANCE_DMA();
861}
862
863/* ================================================================
864 *
865 */
866
867static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
868{
869 drm_mga_private_t *dev_priv = dev->dev_private;
870 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
871 drm_mga_clear_t *clear = data;
872
873 LOCK_TEST_WITH_RETURN(dev, file_priv);
874
875 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
876 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
877
878 WRAP_TEST_WITH_RETURN(dev_priv);
879
880 mga_dma_dispatch_clear(dev, clear);
881
882 /* Make sure we restore the 3D state next time.
883 */
884 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
885
886 return 0;
887}
888
889static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
890{
891 drm_mga_private_t *dev_priv = dev->dev_private;
892 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
893
894 LOCK_TEST_WITH_RETURN(dev, file_priv);
895
896 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
897 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
898
899 WRAP_TEST_WITH_RETURN(dev_priv);
900
901 mga_dma_dispatch_swap(dev);
902
903 /* Make sure we restore the 3D state next time.
904 */
905 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
906
907 return 0;
908}
909
910static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
911{
912 drm_mga_private_t *dev_priv = dev->dev_private;
913 struct drm_device_dma *dma = dev->dma;
914 struct drm_buf *buf;
915 drm_mga_buf_priv_t *buf_priv;
916 drm_mga_vertex_t *vertex = data;
917
918 LOCK_TEST_WITH_RETURN(dev, file_priv);
919
920 if (vertex->idx < 0 || vertex->idx > dma->buf_count)
921 return -EINVAL;
922 buf = dma->buflist[vertex->idx];
923 buf_priv = buf->dev_private;
924
925 buf->used = vertex->used;
926 buf_priv->discard = vertex->discard;
927
928 if (!mga_verify_state(dev_priv)) {
929 if (vertex->discard) {
930 if (buf_priv->dispatched == 1)
931 AGE_BUFFER(buf_priv);
932 buf_priv->dispatched = 0;
933 mga_freelist_put(dev, buf);
934 }
935 return -EINVAL;
936 }
937
938 WRAP_TEST_WITH_RETURN(dev_priv);
939
940 mga_dma_dispatch_vertex(dev, buf);
941
942 return 0;
943}
944
945static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
946{
947 drm_mga_private_t *dev_priv = dev->dev_private;
948 struct drm_device_dma *dma = dev->dma;
949 struct drm_buf *buf;
950 drm_mga_buf_priv_t *buf_priv;
951 drm_mga_indices_t *indices = data;
952
953 LOCK_TEST_WITH_RETURN(dev, file_priv);
954
955 if (indices->idx < 0 || indices->idx > dma->buf_count)
956 return -EINVAL;
957
958 buf = dma->buflist[indices->idx];
959 buf_priv = buf->dev_private;
960
961 buf_priv->discard = indices->discard;
962
963 if (!mga_verify_state(dev_priv)) {
964 if (indices->discard) {
965 if (buf_priv->dispatched == 1)
966 AGE_BUFFER(buf_priv);
967 buf_priv->dispatched = 0;
968 mga_freelist_put(dev, buf);
969 }
970 return -EINVAL;
971 }
972
973 WRAP_TEST_WITH_RETURN(dev_priv);
974
975 mga_dma_dispatch_indices(dev, buf, indices->start, indices->end);
976
977 return 0;
978}
979
980static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv)
981{
982 struct drm_device_dma *dma = dev->dma;
983 drm_mga_private_t *dev_priv = dev->dev_private;
984 struct drm_buf *buf;
985 drm_mga_buf_priv_t *buf_priv;
986 drm_mga_iload_t *iload = data;
987 DRM_DEBUG("\n");
988
989 LOCK_TEST_WITH_RETURN(dev, file_priv);
990
991#if 0
992 if (mga_do_wait_for_idle(dev_priv) < 0) {
993 if (MGA_DMA_DEBUG)
994 DRM_INFO("-EBUSY\n");
995 return -EBUSY;
996 }
997#endif
998 if (iload->idx < 0 || iload->idx > dma->buf_count)
999 return -EINVAL;
1000
1001 buf = dma->buflist[iload->idx];
1002 buf_priv = buf->dev_private;
1003
1004 if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) {
1005 mga_freelist_put(dev, buf);
1006 return -EINVAL;
1007 }
1008
1009 WRAP_TEST_WITH_RETURN(dev_priv);
1010
1011 mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length);
1012
1013 /* Make sure we restore the 3D state next time.
1014 */
1015 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1016
1017 return 0;
1018}
1019
1020static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1021{
1022 drm_mga_private_t *dev_priv = dev->dev_private;
1023 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1024 drm_mga_blit_t *blit = data;
1025 DRM_DEBUG("\n");
1026
1027 LOCK_TEST_WITH_RETURN(dev, file_priv);
1028
1029 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1030 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1031
1032 if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg))
1033 return -EINVAL;
1034
1035 WRAP_TEST_WITH_RETURN(dev_priv);
1036
1037 mga_dma_dispatch_blit(dev, blit);
1038
1039 /* Make sure we restore the 3D state next time.
1040 */
1041 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1042
1043 return 0;
1044}
1045
1046static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1047{
1048 drm_mga_private_t *dev_priv = dev->dev_private;
1049 drm_mga_getparam_t *param = data;
1050 int value;
1051
1052 if (!dev_priv) {
1053 DRM_ERROR("called with no initialization\n");
1054 return -EINVAL;
1055 }
1056
1057 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1058
1059 switch (param->param) {
1060 case MGA_PARAM_IRQ_NR:
1061 value = dev->irq;
1062 break;
1063 case MGA_PARAM_CARD_TYPE:
1064 value = dev_priv->chipset;
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069
1070 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1071 DRM_ERROR("copy_to_user\n");
1072 return -EFAULT;
1073 }
1074
1075 return 0;
1076}
1077
1078static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1079{
1080 drm_mga_private_t *dev_priv = dev->dev_private;
1081 u32 *fence = data;
1082 DMA_LOCALS;
1083
1084 if (!dev_priv) {
1085 DRM_ERROR("called with no initialization\n");
1086 return -EINVAL;
1087 }
1088
1089 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1090
1091 /* I would normal do this assignment in the declaration of fence,
1092 * but dev_priv may be NULL.
1093 */
1094
1095 *fence = dev_priv->next_fence_to_post;
1096 dev_priv->next_fence_to_post++;
1097
1098 BEGIN_DMA(1);
1099 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1100 MGA_DMAPAD, 0x00000000,
1101 MGA_DMAPAD, 0x00000000,
1102 MGA_SOFTRAP, 0x00000000);
1103 ADVANCE_DMA();
1104
1105 return 0;
1106}
1107
1108static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1109{
1110 drm_mga_private_t *dev_priv = dev->dev_private;
1111 u32 *fence = data;
1112
1113 if (!dev_priv) {
1114 DRM_ERROR("called with no initialization\n");
1115 return -EINVAL;
1116 }
1117
1118 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1119
1120 mga_driver_fence_wait(dev, fence);
1121
1122 return 0;
1123}
1124
1125struct drm_ioctl_desc mga_ioctls[] = {
1126 DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1127 DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH),
1128 DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH),
1129 DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH),
1130 DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH),
1131 DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH),
1132 DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH),
1133 DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH),
1134 DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH),
1135 DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH),
1136 DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH),
1137 DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH),
1138 DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1139
1140};
1141
1142int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
3 */
4/*-
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *
--- 20 unchanged lines hidden (view full) ---
29 * Jeff Hartmann <jhartmann@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 *
32 * Rewritten by:
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36#include <sys/cdefs.h>
37__FBSDID("$FreeBSD: head/sys/dev/drm/mga_state.c 182080 2008-08-23 20:59:12Z rnoland $");
38
39#include "dev/drm/drmP.h"
40#include "dev/drm/drm.h"
41#include "dev/drm/mga_drm.h"
42#include "dev/drm/mga_drv.h"
43
44/* ================================================================
45 * DMA hardware state programming functions
46 */
47
48static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
49 struct drm_clip_rect * box)
50{
51 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
52 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
53 unsigned int pitch = dev_priv->front_pitch;
54 DMA_LOCALS;
55
56 BEGIN_DMA(2);
57
58 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
59 */
60 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
61 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
62 MGA_LEN + MGA_EXEC, 0x80000000,
63 MGA_DWGCTL, ctx->dwgctl,
64 MGA_LEN + MGA_EXEC, 0x80000000);
65 }
66 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
67 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
68 MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
69
70 ADVANCE_DMA();
71}
72
73static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
74{
75 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
76 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
77 DMA_LOCALS;
78
79 BEGIN_DMA(3);
80
81 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
82 MGA_MACCESS, ctx->maccess,
83 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
84
85 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
86 MGA_FOGCOL, ctx->fogcolor,
87 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
88
89 DMA_BLOCK(MGA_FCOL, ctx->fcol,
90 MGA_DMAPAD, 0x00000000,
91 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
92
93 ADVANCE_DMA();
94}
95
96static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
97{
98 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
99 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
--- 56 unchanged lines hidden (view full) ---
156}
157
158static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
159{
160 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
161 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
162 DMA_LOCALS;
163
164/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
165/* tex->texctl, tex->texctl2); */
166
167 BEGIN_DMA(6);
168
169 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
170 MGA_TEXCTL, tex->texctl,
171 MGA_TEXFILTER, tex->texfilter,
172 MGA_TEXBORDERCOL, tex->texbordercol);
173
--- 26 unchanged lines hidden (view full) ---
200}
201
202static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
203{
204 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
205 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
206 DMA_LOCALS;
207
208/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
209/* tex->texctl, tex->texctl2); */
210
211 BEGIN_DMA(5);
212
213 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
214 MGA_MAP1_ENABLE |
215 MGA_G400_TC2_MAGIC),
216 MGA_TEXCTL, tex->texctl,
217 MGA_TEXFILTER, tex->texfilter,
--- 52 unchanged lines hidden (view full) ---
270}
271
272static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
273{
274 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
275 unsigned int pipe = sarea_priv->warp_pipe;
276 DMA_LOCALS;
277
278/* printk("mga_g400_emit_pipe %x\n", pipe); */
279
280 BEGIN_DMA(10);
281
282 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
283 MGA_DMAPAD, 0x00000000,
284 MGA_DMAPAD, 0x00000000,
285 MGA_DMAPAD, 0x00000000);
286
--- 123 unchanged lines hidden (view full) ---
410 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
411
412 if (ctx->dstorg != dev_priv->front_offset &&
413 ctx->dstorg != dev_priv->back_offset) {
414 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
415 ctx->dstorg, dev_priv->front_offset,
416 dev_priv->back_offset);
417 ctx->dstorg = 0;
418 return -EINVAL;
419 }
420
421 return 0;
422}
423
424/* Disallow texture reads from PCI space.
425 */
426static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
427{
428 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
429 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
430 unsigned int org;
431
432 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
433
434 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
435 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
436 tex->texorg = 0;
437 return -EINVAL;
438 }
439
440 return 0;
441}
442
443static int mga_verify_state(drm_mga_private_t * dev_priv)
444{
445 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
--- 25 unchanged lines hidden (view full) ---
471
472static int mga_verify_iload(drm_mga_private_t * dev_priv,
473 unsigned int dstorg, unsigned int length)
474{
475 if (dstorg < dev_priv->texture_offset ||
476 dstorg + length > (dev_priv->texture_offset +
477 dev_priv->texture_size)) {
478 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
479 return -EINVAL;
480 }
481
482 if (length & MGA_ILOAD_MASK) {
483 DRM_ERROR("*** bad iload length: 0x%x\n",
484 length & MGA_ILOAD_MASK);
485 return -EINVAL;
486 }
487
488 return 0;
489}
490
491static int mga_verify_blit(drm_mga_private_t * dev_priv,
492 unsigned int srcorg, unsigned int dstorg)
493{
494 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
495 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
496 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
497 return -EINVAL;
498 }
499 return 0;
500}
501
502/* ================================================================
503 *
504 */
505
506static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear)
507{
508 drm_mga_private_t *dev_priv = dev->dev_private;
509 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
510 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
511 struct drm_clip_rect *pbox = sarea_priv->boxes;
512 int nbox = sarea_priv->nbox;
513 int i;
514 DMA_LOCALS;
515 DRM_DEBUG("\n");
516
517 BEGIN_DMA(1);
518
519 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
520 MGA_DMAPAD, 0x00000000,
521 MGA_DWGSYNC, 0x00007100,
522 MGA_DWGSYNC, 0x00007000);
523
524 ADVANCE_DMA();
525
526 for (i = 0; i < nbox; i++) {
527 struct drm_clip_rect *box = &pbox[i];
528 u32 height = box->y2 - box->y1;
529
530 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
531 box->x1, box->y1, box->x2, box->y2);
532
533 if (clear->flags & MGA_FRONT) {
534 BEGIN_DMA(2);
535
--- 52 unchanged lines hidden (view full) ---
588 MGA_PLNWT, ctx->plnwt,
589 MGA_DWGCTL, ctx->dwgctl);
590
591 ADVANCE_DMA();
592
593 FLUSH_DMA();
594}
595
596static void mga_dma_dispatch_swap(struct drm_device * dev)
597{
598 drm_mga_private_t *dev_priv = dev->dev_private;
599 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
600 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
601 struct drm_clip_rect *pbox = sarea_priv->boxes;
602 int nbox = sarea_priv->nbox;
603 int i;
604 DMA_LOCALS;
605 DRM_DEBUG("\n");
606
607 sarea_priv->last_frame.head = dev_priv->prim.tail;
608 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
609
--- 10 unchanged lines hidden (view full) ---
620 MGA_AR5, dev_priv->front_pitch);
621
622 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
623 MGA_DMAPAD, 0x00000000,
624 MGA_PLNWT, 0xffffffff,
625 MGA_DWGCTL, MGA_DWGCTL_COPY);
626
627 for (i = 0; i < nbox; i++) {
628 struct drm_clip_rect *box = &pbox[i];
629 u32 height = box->y2 - box->y1;
630 u32 start = box->y1 * dev_priv->front_pitch;
631
632 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
633 box->x1, box->y1, box->x2, box->y2);
634
635 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
636 MGA_AR3, start + box->x1,
--- 5 unchanged lines hidden (view full) ---
642 MGA_PLNWT, ctx->plnwt,
643 MGA_SRCORG, dev_priv->front_offset,
644 MGA_DWGCTL, ctx->dwgctl);
645
646 ADVANCE_DMA();
647
648 FLUSH_DMA();
649
650 DRM_DEBUG("... done.\n");
651}
652
653static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
654{
655 drm_mga_private_t *dev_priv = dev->dev_private;
656 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
657 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
658 u32 address = (u32) buf->bus_address;
659 u32 length = (u32) buf->used;
660 int i = 0;
661 DMA_LOCALS;
662 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
663
664 if (buf->used) {
665 buf_priv->dispatched = 1;
666
667 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
668
669 do {
670 if (i < sarea_priv->nbox) {
--- 21 unchanged lines hidden (view full) ---
692 buf_priv->dispatched = 0;
693
694 mga_freelist_put(dev, buf);
695 }
696
697 FLUSH_DMA();
698}
699
700static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf,
701 unsigned int start, unsigned int end)
702{
703 drm_mga_private_t *dev_priv = dev->dev_private;
704 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
705 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
706 u32 address = (u32) buf->bus_address;
707 int i = 0;
708 DMA_LOCALS;
709 DRM_DEBUG("buf=%d start=%d end=%d\n", buf->idx, start, end);
710
711 if (start != end) {
712 buf_priv->dispatched = 1;
713
714 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
715
716 do {
717 if (i < sarea_priv->nbox) {
--- 23 unchanged lines hidden (view full) ---
741 }
742
743 FLUSH_DMA();
744}
745
746/* This copies a 64 byte aligned agp region to the frambuffer with a
747 * standard blit, the ioctl needs to do checking.
748 */
749static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf,
750 unsigned int dstorg, unsigned int length)
751{
752 drm_mga_private_t *dev_priv = dev->dev_private;
753 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
754 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
755 u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
756 u32 y2;
757 DMA_LOCALS;
--- 36 unchanged lines hidden (view full) ---
794 buf->used = 0;
795 buf_priv->dispatched = 0;
796
797 mga_freelist_put(dev, buf);
798
799 FLUSH_DMA();
800}
801
802static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit)
803{
804 drm_mga_private_t *dev_priv = dev->dev_private;
805 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
806 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
807 struct drm_clip_rect *pbox = sarea_priv->boxes;
808 int nbox = sarea_priv->nbox;
809 u32 scandir = 0, i;
810 DMA_LOCALS;
811 DRM_DEBUG("\n");
812
813 BEGIN_DMA(4 + nbox);
814
815 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
--- 43 unchanged lines hidden (view full) ---
859
860 ADVANCE_DMA();
861}
862
863/* ================================================================
864 *
865 */
866
867static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
868{
869 drm_mga_private_t *dev_priv = dev->dev_private;
870 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
871 drm_mga_clear_t *clear = data;
872
873 LOCK_TEST_WITH_RETURN(dev, file_priv);
874
875 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
876 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
877
878 WRAP_TEST_WITH_RETURN(dev_priv);
879
880 mga_dma_dispatch_clear(dev, clear);
881
882 /* Make sure we restore the 3D state next time.
883 */
884 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
885
886 return 0;
887}
888
889static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
890{
891 drm_mga_private_t *dev_priv = dev->dev_private;
892 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
893
894 LOCK_TEST_WITH_RETURN(dev, file_priv);
895
896 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
897 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
898
899 WRAP_TEST_WITH_RETURN(dev_priv);
900
901 mga_dma_dispatch_swap(dev);
902
903 /* Make sure we restore the 3D state next time.
904 */
905 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
906
907 return 0;
908}
909
910static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
911{
912 drm_mga_private_t *dev_priv = dev->dev_private;
913 struct drm_device_dma *dma = dev->dma;
914 struct drm_buf *buf;
915 drm_mga_buf_priv_t *buf_priv;
916 drm_mga_vertex_t *vertex = data;
917
918 LOCK_TEST_WITH_RETURN(dev, file_priv);
919
920 if (vertex->idx < 0 || vertex->idx > dma->buf_count)
921 return -EINVAL;
922 buf = dma->buflist[vertex->idx];
923 buf_priv = buf->dev_private;
924
925 buf->used = vertex->used;
926 buf_priv->discard = vertex->discard;
927
928 if (!mga_verify_state(dev_priv)) {
929 if (vertex->discard) {
930 if (buf_priv->dispatched == 1)
931 AGE_BUFFER(buf_priv);
932 buf_priv->dispatched = 0;
933 mga_freelist_put(dev, buf);
934 }
935 return -EINVAL;
936 }
937
938 WRAP_TEST_WITH_RETURN(dev_priv);
939
940 mga_dma_dispatch_vertex(dev, buf);
941
942 return 0;
943}
944
945static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
946{
947 drm_mga_private_t *dev_priv = dev->dev_private;
948 struct drm_device_dma *dma = dev->dma;
949 struct drm_buf *buf;
950 drm_mga_buf_priv_t *buf_priv;
951 drm_mga_indices_t *indices = data;
952
953 LOCK_TEST_WITH_RETURN(dev, file_priv);
954
955 if (indices->idx < 0 || indices->idx > dma->buf_count)
956 return -EINVAL;
957
958 buf = dma->buflist[indices->idx];
959 buf_priv = buf->dev_private;
960
961 buf_priv->discard = indices->discard;
962
963 if (!mga_verify_state(dev_priv)) {
964 if (indices->discard) {
965 if (buf_priv->dispatched == 1)
966 AGE_BUFFER(buf_priv);
967 buf_priv->dispatched = 0;
968 mga_freelist_put(dev, buf);
969 }
970 return -EINVAL;
971 }
972
973 WRAP_TEST_WITH_RETURN(dev_priv);
974
975 mga_dma_dispatch_indices(dev, buf, indices->start, indices->end);
976
977 return 0;
978}
979
980static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv)
981{
982 struct drm_device_dma *dma = dev->dma;
983 drm_mga_private_t *dev_priv = dev->dev_private;
984 struct drm_buf *buf;
985 drm_mga_buf_priv_t *buf_priv;
986 drm_mga_iload_t *iload = data;
987 DRM_DEBUG("\n");
988
989 LOCK_TEST_WITH_RETURN(dev, file_priv);
990
991#if 0
992 if (mga_do_wait_for_idle(dev_priv) < 0) {
993 if (MGA_DMA_DEBUG)
994 DRM_INFO("-EBUSY\n");
995 return -EBUSY;
996 }
997#endif
998 if (iload->idx < 0 || iload->idx > dma->buf_count)
999 return -EINVAL;
1000
1001 buf = dma->buflist[iload->idx];
1002 buf_priv = buf->dev_private;
1003
1004 if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) {
1005 mga_freelist_put(dev, buf);
1006 return -EINVAL;
1007 }
1008
1009 WRAP_TEST_WITH_RETURN(dev_priv);
1010
1011 mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length);
1012
1013 /* Make sure we restore the 3D state next time.
1014 */
1015 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1016
1017 return 0;
1018}
1019
1020static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
1021{
1022 drm_mga_private_t *dev_priv = dev->dev_private;
1023 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1024 drm_mga_blit_t *blit = data;
1025 DRM_DEBUG("\n");
1026
1027 LOCK_TEST_WITH_RETURN(dev, file_priv);
1028
1029 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1030 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1031
1032 if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg))
1033 return -EINVAL;
1034
1035 WRAP_TEST_WITH_RETURN(dev_priv);
1036
1037 mga_dma_dispatch_blit(dev, blit);
1038
1039 /* Make sure we restore the 3D state next time.
1040 */
1041 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1042
1043 return 0;
1044}
1045
1046static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
1047{
1048 drm_mga_private_t *dev_priv = dev->dev_private;
1049 drm_mga_getparam_t *param = data;
1050 int value;
1051
1052 if (!dev_priv) {
1053 DRM_ERROR("called with no initialization\n");
1054 return -EINVAL;
1055 }
1056
1057 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1058
1059 switch (param->param) {
1060 case MGA_PARAM_IRQ_NR:
1061 value = dev->irq;
1062 break;
1063 case MGA_PARAM_CARD_TYPE:
1064 value = dev_priv->chipset;
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069
1070 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1071 DRM_ERROR("copy_to_user\n");
1072 return -EFAULT;
1073 }
1074
1075 return 0;
1076}
1077
1078static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1079{
1080 drm_mga_private_t *dev_priv = dev->dev_private;
1081 u32 *fence = data;
1082 DMA_LOCALS;
1083
1084 if (!dev_priv) {
1085 DRM_ERROR("called with no initialization\n");
1086 return -EINVAL;
1087 }
1088
1089 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1090
1091 /* I would normal do this assignment in the declaration of fence,
1092 * but dev_priv may be NULL.
1093 */
1094
1095 *fence = dev_priv->next_fence_to_post;
1096 dev_priv->next_fence_to_post++;
1097
1098 BEGIN_DMA(1);
1099 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1100 MGA_DMAPAD, 0x00000000,
1101 MGA_DMAPAD, 0x00000000,
1102 MGA_SOFTRAP, 0x00000000);
1103 ADVANCE_DMA();
1104
1105 return 0;
1106}
1107
1108static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
1109{
1110 drm_mga_private_t *dev_priv = dev->dev_private;
1111 u32 *fence = data;
1112
1113 if (!dev_priv) {
1114 DRM_ERROR("called with no initialization\n");
1115 return -EINVAL;
1116 }
1117
1118 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1119
1120 mga_driver_fence_wait(dev, fence);
1121
1122 return 0;
1123}
1124
1125struct drm_ioctl_desc mga_ioctls[] = {
1126 DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1127 DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH),
1128 DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH),
1129 DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH),
1130 DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH),
1131 DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH),
1132 DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH),
1133 DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH),
1134 DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH),
1135 DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH),
1136 DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH),
1137 DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH),
1138 DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1139
1140};
1141
1142int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);