| t4_netmap.c (306664) | t4_netmap.c (309560) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> |
| 29__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_netmap.c 306664 2016-10-03 23:49:05Z jhb $"); | 29__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_netmap.c 309560 2016-12-05 20:43:25Z jhb $"); |
| 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33 34#ifdef DEV_NETMAP 35#include <sys/param.h> 36#include <sys/bus.h> 37#include <sys/eventhandler.h> --- 96 unchanged lines hidden (view full) --- 134 F_FW_IQ_CMD_FL0CONGEN); 135 } 136 c.iqns_to_fl0congen |= 137 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 138 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 139 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 140 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 141 c.fl0dcaen_to_fl0cidxfthresh = | 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33 34#ifdef DEV_NETMAP 35#include <sys/param.h> 36#include <sys/bus.h> 37#include <sys/eventhandler.h> --- 96 unchanged lines hidden (view full) --- 134 F_FW_IQ_CMD_FL0CONGEN); 135 } 136 c.iqns_to_fl0congen |= 137 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 138 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 139 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 140 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 141 c.fl0dcaen_to_fl0cidxfthresh = |
| 142 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) | 143 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); | 142 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 143 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 144 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 145 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); |
| 144 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 145 c.fl0addr = htobe64(nm_rxq->fl_ba); 146 147 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 148 if (rc != 0) { 149 device_printf(sc->dev, 150 "failed to create netmap ingress queue: %d\n", rc); 151 return (rc); --- 19 unchanged lines hidden (view full) --- 171 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 172 __func__, cntxt_id, sc->sge.neq - 1); 173 } 174 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 175 176 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 177 sc->chip_params->sge_fl_db; 178 | 146 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 147 c.fl0addr = htobe64(nm_rxq->fl_ba); 148 149 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 150 if (rc != 0) { 151 device_printf(sc->dev, 152 "failed to create netmap ingress queue: %d\n", rc); 153 return (rc); --- 19 unchanged lines hidden (view full) --- 173 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 174 __func__, cntxt_id, sc->sge.neq - 1); 175 } 176 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 177 178 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 179 sc->chip_params->sge_fl_db; 180 |
| 179 if (is_t5(sc) && cong >= 0) { | 181 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { |
| 180 uint32_t param, val; 181 182 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 183 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 184 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 185 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 186 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 187 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); --- 688 unchanged lines hidden (view full) --- 876{ 877 878 MPASS(vi->nnmrxq > 0); 879 MPASS(vi->ifp != NULL); 880 881 netmap_detach(vi->ifp); 882} 883 | 182 uint32_t param, val; 183 184 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 185 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 186 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 187 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 188 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 189 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); --- 688 unchanged lines hidden (view full) --- 878{ 879 880 MPASS(vi->nnmrxq > 0); 881 MPASS(vi->ifp != NULL); 882 883 netmap_detach(vi->ifp); 884} 885 |
| 886static inline const void * 887unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 888{ 889 890 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 891 892 /* data[0] is RSS header */ 893 return (&cpl->data[1]); 894} 895 |
|
| 884static void | 896static void |
| 885handle_nm_fw6_msg(struct adapter *sc, struct ifnet *ifp, 886 const struct cpl_fw6_msg *cpl) | 897handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 898 const struct cpl_sge_egr_update *egr) |
| 887{ | 899{ |
| 888 const struct cpl_sge_egr_update *egr; | |
| 889 uint32_t oq; 890 struct sge_nm_txq *nm_txq; 891 | 900 uint32_t oq; 901 struct sge_nm_txq *nm_txq; 902 |
| 892 if (cpl->type != FW_TYPE_RSSCPL && cpl->type != FW6_TYPE_RSSCPL) 893 panic("%s: FW_TYPE 0x%x on nm_rxq.", __func__, cpl->type); 894 895 /* data[0] is RSS header */ 896 egr = (const void *)&cpl->data[1]; | |
| 897 oq = be32toh(egr->opcode_qid); 898 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 899 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 900 901 netmap_tx_irq(ifp, nm_txq->nid); 902} 903 904void 905t4_nm_intr(void *arg) 906{ 907 struct sge_nm_rxq *nm_rxq = arg; 908 struct vi_info *vi = nm_rxq->vi; 909 struct adapter *sc = vi->pi->adapter; 910 struct ifnet *ifp = vi->ifp; 911 struct netmap_adapter *na = NA(ifp); 912 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid]; 913 struct netmap_ring *ring = kring->ring; 914 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; | 903 oq = be32toh(egr->opcode_qid); 904 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 905 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 906 907 netmap_tx_irq(ifp, nm_txq->nid); 908} 909 910void 911t4_nm_intr(void *arg) 912{ 913 struct sge_nm_rxq *nm_rxq = arg; 914 struct vi_info *vi = nm_rxq->vi; 915 struct adapter *sc = vi->pi->adapter; 916 struct ifnet *ifp = vi->ifp; 917 struct netmap_adapter *na = NA(ifp); 918 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid]; 919 struct netmap_ring *ring = kring->ring; 920 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; |
| 921 const void *cpl; |
|
| 915 uint32_t lq; 916 u_int n = 0, work = 0; 917 uint8_t opcode; 918 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 919 u_int fl_credits = fl_cidx & 7; 920 921 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 922 923 rmb(); 924 925 lq = be32toh(d->rsp.pldbuflen_qid); 926 opcode = d->rss.opcode; | 922 uint32_t lq; 923 u_int n = 0, work = 0; 924 uint8_t opcode; 925 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 926 u_int fl_credits = fl_cidx & 7; 927 928 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 929 930 rmb(); 931 932 lq = be32toh(d->rsp.pldbuflen_qid); 933 opcode = d->rss.opcode; |
| 934 cpl = &d->cpl[0]; |
|
| 927 928 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 929 case X_RSPD_TYPE_FLBUF: 930 if (black_hole != 2) { 931 /* No buffer packing so new buf every time */ 932 MPASS(lq & F_RSPD_NEWBUF); 933 } 934 935 /* fall through */ 936 937 case X_RSPD_TYPE_CPL: 938 MPASS(opcode < NUM_CPL_CMDS); 939 940 switch (opcode) { 941 case CPL_FW4_MSG: 942 case CPL_FW6_MSG: | 935 936 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 937 case X_RSPD_TYPE_FLBUF: 938 if (black_hole != 2) { 939 /* No buffer packing so new buf every time */ 940 MPASS(lq & F_RSPD_NEWBUF); 941 } 942 943 /* fall through */ 944 945 case X_RSPD_TYPE_CPL: 946 MPASS(opcode < NUM_CPL_CMDS); 947 948 switch (opcode) { 949 case CPL_FW4_MSG: 950 case CPL_FW6_MSG: |
| 943 handle_nm_fw6_msg(sc, ifp, 944 (const void *)&d->cpl[0]); | 951 cpl = unwrap_nm_fw6_msg(cpl); 952 /* fall through */ 953 case CPL_SGE_EGR_UPDATE: 954 handle_nm_sge_egr_update(sc, ifp, cpl); |
| 945 break; 946 case CPL_RX_PKT: 947 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 948 sc->params.sge.fl_pktshift; 949 ring->slot[fl_cidx].flags = kring->nkr_slot_flags; 950 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0; 951 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0; 952 if (__predict_false(fl_cidx == nm_rxq->fl_sidx)) --- 59 unchanged lines hidden --- | 955 break; 956 case CPL_RX_PKT: 957 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 958 sc->params.sge.fl_pktshift; 959 ring->slot[fl_cidx].flags = kring->nkr_slot_flags; 960 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0; 961 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0; 962 if (__predict_false(fl_cidx == nm_rxq->fl_sidx)) --- 59 unchanged lines hidden --- |