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t4_main.c (309559) t4_main.c (309560)
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_main.c 309559 2016-12-05 19:37:15Z jhb $");
29__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_main.c 309560 2016-12-05 20:43:25Z jhb $");
30
31#include "opt_ddb.h"
32#include "opt_inet.h"
33#include "opt_inet6.h"
34#include "opt_rss.h"
35
36#include <sys/param.h>
37#include <sys/conf.h>

--- 131 unchanged lines hidden (view full) ---

169
170/* T5 VI (vcxl) interface */
171static driver_t vcxl_driver = {
172 "vcxl",
173 vcxgbe_methods,
174 sizeof(struct vi_info)
175};
176
30
31#include "opt_ddb.h"
32#include "opt_inet.h"
33#include "opt_inet6.h"
34#include "opt_rss.h"
35
36#include <sys/param.h>
37#include <sys/conf.h>

--- 131 unchanged lines hidden (view full) ---

169
170/* T5 VI (vcxl) interface */
171static driver_t vcxl_driver = {
172 "vcxl",
173 vcxgbe_methods,
174 sizeof(struct vi_info)
175};
176
177/* T6 bus driver interface */
178static int t6_probe(device_t);
179static device_method_t t6_methods[] = {
180 DEVMETHOD(device_probe, t6_probe),
181 DEVMETHOD(device_attach, t4_attach),
182 DEVMETHOD(device_detach, t4_detach),
183
184 DEVMETHOD(t4_is_main_ready, t4_ready),
185 DEVMETHOD(t4_read_port_device, t4_read_port_device),
186
187 DEVMETHOD_END
188};
189static driver_t t6_driver = {
190 "t6nex",
191 t6_methods,
192 sizeof(struct adapter)
193};
194
195
196/* T6 port (cc) interface */
197static driver_t cc_driver = {
198 "cc",
199 cxgbe_methods,
200 sizeof(struct port_info)
201};
202
203/* T6 VI (vcc) interface */
204static driver_t vcc_driver = {
205 "vcc",
206 vcxgbe_methods,
207 sizeof(struct vi_info)
208};
209
177/* ifnet + media interface */
178static void cxgbe_init(void *);
179static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
180static int cxgbe_transmit(struct ifnet *, struct mbuf *);
181static void cxgbe_qflush(struct ifnet *);
182static int cxgbe_media_change(struct ifnet *);
183static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
184

--- 165 unchanged lines hidden (view full) ---

350TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
351
352static int t4_toecaps_allowed = -1;
353TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
354
355static int t4_rdmacaps_allowed = -1;
356TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
357
210/* ifnet + media interface */
211static void cxgbe_init(void *);
212static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
213static int cxgbe_transmit(struct ifnet *, struct mbuf *);
214static void cxgbe_qflush(struct ifnet *);
215static int cxgbe_media_change(struct ifnet *);
216static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
217

--- 165 unchanged lines hidden (view full) ---

383TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
384
385static int t4_toecaps_allowed = -1;
386TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
387
388static int t4_rdmacaps_allowed = -1;
389TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
390
358static int t4_tlscaps_allowed = 0;
359TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
391static int t4_cryptocaps_allowed = 0;
392TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
360
361static int t4_iscsicaps_allowed = -1;
362TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
363
364static int t4_fcoecaps_allowed = 0;
365TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
366
367static int t5_write_combine = 0;

--- 194 unchanged lines hidden (view full) ---

562 {0x5405, "Chelsio T540-BCH"},
563 {0x5406, "Chelsio T540-CH"},
564 {0x5408, "Chelsio T520-CX"},
565 {0x540b, "Chelsio B520-SR"},
566 {0x540c, "Chelsio B504-BT"},
567 {0x540f, "Chelsio Amsterdam"},
568 {0x5413, "Chelsio T580-CHR"},
569#endif
393
394static int t4_iscsicaps_allowed = -1;
395TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
396
397static int t4_fcoecaps_allowed = 0;
398TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
399
400static int t5_write_combine = 0;

--- 194 unchanged lines hidden (view full) ---

595 {0x5405, "Chelsio T540-BCH"},
596 {0x5406, "Chelsio T540-CH"},
597 {0x5408, "Chelsio T520-CX"},
598 {0x540b, "Chelsio B520-SR"},
599 {0x540c, "Chelsio B504-BT"},
600 {0x540f, "Chelsio Amsterdam"},
601 {0x5413, "Chelsio T580-CHR"},
602#endif
603}, t6_pciids[] = {
604 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
605 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
606 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
607 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
608 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
609 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
610 {0x6410, "Chelsio T62100-DBG"}, /* 2 x 40/50/100G, debug */
570};
571
572#ifdef TCP_OFFLOAD
573/*
574 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
575 * exactly the same for both rxq and ofld_rxq.
576 */
577CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));

--- 46 unchanged lines hidden (view full) ---

624 device_set_desc(dev, t5_pciids[i].desc);
625 return (BUS_PROBE_DEFAULT);
626 }
627 }
628
629 return (ENXIO);
630}
631
611};
612
613#ifdef TCP_OFFLOAD
614/*
615 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
616 * exactly the same for both rxq and ofld_rxq.
617 */
618CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));

--- 46 unchanged lines hidden (view full) ---

665 device_set_desc(dev, t5_pciids[i].desc);
666 return (BUS_PROBE_DEFAULT);
667 }
668 }
669
670 return (ENXIO);
671}
672
673static int
674t6_probe(device_t dev)
675{
676 int i;
677 uint16_t v = pci_get_vendor(dev);
678 uint16_t d = pci_get_device(dev);
679
680 if (v != PCI_VENDOR_ID_CHELSIO)
681 return (ENXIO);
682
683 for (i = 0; i < nitems(t6_pciids); i++) {
684 if (d == t6_pciids[i].device) {
685 device_set_desc(dev, t6_pciids[i].desc);
686 return (BUS_PROBE_DEFAULT);
687 }
688 }
689
690 return (ENXIO);
691}
692
632static void
633t5_attribute_workaround(device_t dev)
634{
635 device_t root_port;
636 uint32_t v;
637
638 /*
639 * The T5 chips do not properly echo the No Snoop and Relaxed

--- 11 unchanged lines hidden (view full) ---

651 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
652 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
653 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
654 0)
655 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
656 device_get_nameunit(root_port));
657}
658
693static void
694t5_attribute_workaround(device_t dev)
695{
696 device_t root_port;
697 uint32_t v;
698
699 /*
700 * The T5 chips do not properly echo the No Snoop and Relaxed

--- 11 unchanged lines hidden (view full) ---

712 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
713 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
714 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
715 0)
716 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
717 device_get_nameunit(root_port));
718}
719
720static const struct devnames devnames[] = {
721 {
722 .nexus_name = "t4nex",
723 .ifnet_name = "cxgbe",
724 .vi_ifnet_name = "vcxgbe",
725 .pf03_drv_name = "t4iov",
726 .vf_nexus_name = "t4vf",
727 .vf_ifnet_name = "cxgbev"
728 }, {
729 .nexus_name = "t5nex",
730 .ifnet_name = "cxl",
731 .vi_ifnet_name = "vcxl",
732 .pf03_drv_name = "t5iov",
733 .vf_nexus_name = "t5vf",
734 .vf_ifnet_name = "cxlv"
735 }, {
736 .nexus_name = "t6nex",
737 .ifnet_name = "cc",
738 .vi_ifnet_name = "vcc",
739 .pf03_drv_name = "t6iov",
740 .vf_nexus_name = "t6vf",
741 .vf_ifnet_name = "ccv"
742 }
743};
744
745void
746t4_init_devnames(struct adapter *sc)
747{
748 int id;
749
750 id = chip_id(sc);
751 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
752 sc->names = &devnames[id - CHELSIO_T4];
753 else {
754 device_printf(sc->dev, "chip id %d is not supported.\n", id);
755 sc->names = NULL;
756 }
757}
758
659static int
660t4_attach(device_t dev)
661{
662 struct adapter *sc;
663 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
664 struct make_dev_args mda;
665 struct intrs_and_queues iaq;
666 struct sge *s;

--- 41 unchanged lines hidden (view full) ---

708 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
709
710 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
711
712 rc = t4_map_bars_0_and_4(sc);
713 if (rc != 0)
714 goto done; /* error message displayed already */
715
759static int
760t4_attach(device_t dev)
761{
762 struct adapter *sc;
763 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
764 struct make_dev_args mda;
765 struct intrs_and_queues iaq;
766 struct sge *s;

--- 41 unchanged lines hidden (view full) ---

808 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
809
810 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
811
812 rc = t4_map_bars_0_and_4(sc);
813 if (rc != 0)
814 goto done; /* error message displayed already */
815
716 /*
717 * This is the real PF# to which we're attaching. Works from within PCI
718 * passthrough environments too, where pci_get_function() could return a
719 * different PF# depending on the passthrough configuration. We need to
720 * use the real PF# in all our communication with the firmware.
721 */
722 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
723 sc->mbox = sc->pf;
724
725 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
726
727 /* Prepare the adapter for operation. */
728 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
729 rc = -t4_prep_adapter(sc, buf);
730 free(buf, M_CXGBE);
731 if (rc != 0) {
732 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
733 goto done;
734 }
735
736 /*
816 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
817
818 /* Prepare the adapter for operation. */
819 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
820 rc = -t4_prep_adapter(sc, buf);
821 free(buf, M_CXGBE);
822 if (rc != 0) {
823 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
824 goto done;
825 }
826
827 /*
828 * This is the real PF# to which we're attaching. Works from within PCI
829 * passthrough environments too, where pci_get_function() could return a
830 * different PF# depending on the passthrough configuration. We need to
831 * use the real PF# in all our communication with the firmware.
832 */
833 j = t4_read_reg(sc, A_PL_WHOAMI);
834 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
835 sc->mbox = sc->pf;
836
837 t4_init_devnames(sc);
838 if (sc->names == NULL) {
839 rc = ENOTSUP;
840 goto done; /* error message displayed already */
841 }
842
843 /*
737 * Do this really early, with the memory windows set up even before the
738 * character device. The userland tool's register i/o and mem read
739 * will work even in "recovery mode".
740 */
741 setup_memwin(sc);
742 if (t4_init_devlog_params(sc, 0) == 0)
743 fixup_devlog_params(sc);
744 make_dev_args_init(&mda);

--- 114 unchanged lines hidden (view full) ---

859 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
860 device_get_nameunit(dev), i);
861 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
862 sc->chan_map[pi->tx_chan] = i;
863
864 pi->tc = malloc(sizeof(struct tx_sched_class) *
865 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
866
844 * Do this really early, with the memory windows set up even before the
845 * character device. The userland tool's register i/o and mem read
846 * will work even in "recovery mode".
847 */
848 setup_memwin(sc);
849 if (t4_init_devlog_params(sc, 0) == 0)
850 fixup_devlog_params(sc);
851 make_dev_args_init(&mda);

--- 114 unchanged lines hidden (view full) ---

966 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
967 device_get_nameunit(dev), i);
968 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
969 sc->chan_map[pi->tx_chan] = i;
970
971 pi->tc = malloc(sizeof(struct tx_sched_class) *
972 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
973
867 if (is_10G_port(pi) || is_40G_port(pi)) {
974 if (port_top_speed(pi) >= 10) {
868 n10g++;
869 } else {
870 n1g++;
871 }
872
873 pi->linkdnrc = -1;
874
975 n10g++;
976 } else {
977 n1g++;
978 }
979
980 pi->linkdnrc = -1;
981
875 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
982 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1);
876 if (pi->dev == NULL) {
877 device_printf(dev,
878 "failed to add device for port %d.\n", i);
879 rc = ENXIO;
880 goto done;
881 }
882 pi->vi[0].dev = pi->dev;
883 device_set_softc(pi->dev, pi);

--- 91 unchanged lines hidden (view full) ---

975 pi->nvi = num_vis;
976 for_each_vi(pi, j, vi) {
977 vi->pi = pi;
978 vi->qsize_rxq = t4_qsize_rxq;
979 vi->qsize_txq = t4_qsize_txq;
980
981 vi->first_rxq = rqidx;
982 vi->first_txq = tqidx;
983 if (pi->dev == NULL) {
984 device_printf(dev,
985 "failed to add device for port %d.\n", i);
986 rc = ENXIO;
987 goto done;
988 }
989 pi->vi[0].dev = pi->dev;
990 device_set_softc(pi->dev, pi);

--- 91 unchanged lines hidden (view full) ---

1082 pi->nvi = num_vis;
1083 for_each_vi(pi, j, vi) {
1084 vi->pi = pi;
1085 vi->qsize_rxq = t4_qsize_rxq;
1086 vi->qsize_txq = t4_qsize_txq;
1087
1088 vi->first_rxq = rqidx;
1089 vi->first_txq = tqidx;
983 if (is_10G_port(pi) || is_40G_port(pi)) {
1090 if (port_top_speed(pi) >= 10) {
984 vi->tmr_idx = t4_tmr_idx_10g;
985 vi->pktc_idx = t4_pktc_idx_10g;
986 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
987 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
988 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
989 } else {
990 vi->tmr_idx = t4_tmr_idx_1g;
991 vi->pktc_idx = t4_pktc_idx_1g;

--- 7 unchanged lines hidden (view full) ---

999 if (j == 0 && vi->ntxq > 1)
1000 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1001 else
1002 vi->rsrv_noflowq = 0;
1003
1004#ifdef TCP_OFFLOAD
1005 vi->first_ofld_rxq = ofld_rqidx;
1006 vi->first_ofld_txq = ofld_tqidx;
1091 vi->tmr_idx = t4_tmr_idx_10g;
1092 vi->pktc_idx = t4_pktc_idx_10g;
1093 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
1094 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
1095 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
1096 } else {
1097 vi->tmr_idx = t4_tmr_idx_1g;
1098 vi->pktc_idx = t4_pktc_idx_1g;

--- 7 unchanged lines hidden (view full) ---

1106 if (j == 0 && vi->ntxq > 1)
1107 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1108 else
1109 vi->rsrv_noflowq = 0;
1110
1111#ifdef TCP_OFFLOAD
1112 vi->first_ofld_rxq = ofld_rqidx;
1113 vi->first_ofld_txq = ofld_tqidx;
1007 if (is_10G_port(pi) || is_40G_port(pi)) {
1114 if (port_top_speed(pi) >= 10) {
1008 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1009 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1010 iaq.nofldrxq_vi;
1011 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1012 iaq.nofldtxq_vi;
1013 } else {
1014 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1015 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :

--- 334 unchanged lines hidden (view full) ---

1350
1351 return (0);
1352}
1353
1354static int
1355cxgbe_attach(device_t dev)
1356{
1357 struct port_info *pi = device_get_softc(dev);
1115 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1116 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1117 iaq.nofldrxq_vi;
1118 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1119 iaq.nofldtxq_vi;
1120 } else {
1121 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1122 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :

--- 334 unchanged lines hidden (view full) ---

1457
1458 return (0);
1459}
1460
1461static int
1462cxgbe_attach(device_t dev)
1463{
1464 struct port_info *pi = device_get_softc(dev);
1465 struct adapter *sc = pi->adapter;
1358 struct vi_info *vi;
1359 int i, rc;
1360
1361 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1362
1363 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1364 if (rc)
1365 return (rc);
1366
1367 for_each_vi(pi, i, vi) {
1368 if (i == 0)
1369 continue;
1466 struct vi_info *vi;
1467 int i, rc;
1468
1469 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1470
1471 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1472 if (rc)
1473 return (rc);
1474
1475 for_each_vi(pi, i, vi) {
1476 if (i == 0)
1477 continue;
1370 vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
1371 "vcxgbe" : "vcxl", -1);
1478 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1372 if (vi->dev == NULL) {
1373 device_printf(dev, "failed to add VI %d\n", i);
1374 continue;
1375 }
1376 device_set_softc(vi->dev, vi);
1377 }
1378
1379 cxgbe_sysctls(pi);

--- 246 unchanged lines hidden (view full) ---

1626 VLAN_CAPABILITIES(ifp);
1627#endif
1628fail:
1629 end_synchronized_op(sc, 0);
1630 break;
1631
1632 case SIOCSIFMEDIA:
1633 case SIOCGIFMEDIA:
1479 if (vi->dev == NULL) {
1480 device_printf(dev, "failed to add VI %d\n", i);
1481 continue;
1482 }
1483 device_set_softc(vi->dev, vi);
1484 }
1485
1486 cxgbe_sysctls(pi);

--- 246 unchanged lines hidden (view full) ---

1733 VLAN_CAPABILITIES(ifp);
1734#endif
1735fail:
1736 end_synchronized_op(sc, 0);
1737 break;
1738
1739 case SIOCSIFMEDIA:
1740 case SIOCGIFMEDIA:
1741 case SIOCGIFXMEDIA:
1634 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1635 break;
1636
1637 case SIOCGI2C: {
1638 struct ifi2creq i2c;
1639
1640 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1641 if (rc != 0)

--- 278 unchanged lines hidden (view full) ---

1920 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1921 vi->hw_addr, &vi->rss_size, func, 0);
1922 if (rc < 0) {
1923 device_printf(dev, "Failed to allocate virtual interface "
1924 "for port %d: %d\n", pi->port_id, -rc);
1925 return (-rc);
1926 }
1927 vi->viid = rc;
1742 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1743 break;
1744
1745 case SIOCGI2C: {
1746 struct ifi2creq i2c;
1747
1748 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1749 if (rc != 0)

--- 278 unchanged lines hidden (view full) ---

2028 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2029 vi->hw_addr, &vi->rss_size, func, 0);
2030 if (rc < 0) {
2031 device_printf(dev, "Failed to allocate virtual interface "
2032 "for port %d: %d\n", pi->port_id, -rc);
2033 return (-rc);
2034 }
2035 vi->viid = rc;
2036 if (chip_id(sc) <= CHELSIO_T5)
2037 vi->smt_idx = (rc & 0x7f) << 1;
2038 else
2039 vi->smt_idx = (rc & 0x7f);
1928
1929 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1930 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1931 V_FW_PARAMS_PARAM_YZ(vi->viid);
1932 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
1933 if (rc)
1934 vi->rss_base = 0xffff;
1935 else {

--- 86 unchanged lines hidden (view full) ---

2022 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2023 &sc->udbs_rid, RF_ACTIVE);
2024 if (sc->udbs_res == NULL) {
2025 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2026 return (ENXIO);
2027 }
2028 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2029
2040
2041 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2042 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2043 V_FW_PARAMS_PARAM_YZ(vi->viid);
2044 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
2045 if (rc)
2046 vi->rss_base = 0xffff;
2047 else {

--- 86 unchanged lines hidden (view full) ---

2134 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2135 &sc->udbs_rid, RF_ACTIVE);
2136 if (sc->udbs_res == NULL) {
2137 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2138 return (ENXIO);
2139 }
2140 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2141
2030 if (is_t5(sc)) {
2142 if (chip_id(sc) >= CHELSIO_T5) {
2031 setbit(&sc->doorbells, DOORBELL_UDB);
2032#if defined(__i386__) || defined(__amd64__)
2033 if (t5_write_combine) {
2143 setbit(&sc->doorbells, DOORBELL_UDB);
2144#if defined(__i386__) || defined(__amd64__)
2145 if (t5_write_combine) {
2034 int rc;
2146 int rc, mode;
2035
2036 /*
2037 * Enable write combining on BAR2. This is the
2038 * userspace doorbell BAR and is split into 128B
2039 * (UDBS_SEG_SIZE) doorbell regions, each associated
2040 * with an egress queue. The first 64B has the doorbell
2041 * and the second 64B can be used to submit a tx work
2042 * request with an implicit doorbell.

--- 6 unchanged lines hidden (view full) ---

2049 setbit(&sc->doorbells, DOORBELL_WCWR);
2050 setbit(&sc->doorbells, DOORBELL_UDBWC);
2051 } else {
2052 device_printf(sc->dev,
2053 "couldn't enable write combining: %d\n",
2054 rc);
2055 }
2056
2147
2148 /*
2149 * Enable write combining on BAR2. This is the
2150 * userspace doorbell BAR and is split into 128B
2151 * (UDBS_SEG_SIZE) doorbell regions, each associated
2152 * with an egress queue. The first 64B has the doorbell
2153 * and the second 64B can be used to submit a tx work
2154 * request with an implicit doorbell.

--- 6 unchanged lines hidden (view full) ---

2161 setbit(&sc->doorbells, DOORBELL_WCWR);
2162 setbit(&sc->doorbells, DOORBELL_UDBWC);
2163 } else {
2164 device_printf(sc->dev,
2165 "couldn't enable write combining: %d\n",
2166 rc);
2167 }
2168
2169 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2057 t4_write_reg(sc, A_SGE_STAT_CFG,
2170 t4_write_reg(sc, A_SGE_STAT_CFG,
2058 V_STATSOURCE_T5(7) | V_STATMODE(0));
2171 V_STATSOURCE_T5(7) | mode);
2059 }
2060#endif
2061 }
2062
2063 return (0);
2064}
2065
2066struct memwin_init {

--- 613 unchanged lines hidden (view full) ---

2680 .intfver_vnic = FW_INTFVER(T5, VNIC),
2681 .intfver_ofld = FW_INTFVER(T5, OFLD),
2682 .intfver_ri = FW_INTFVER(T5, RI),
2683 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2684 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2685 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2686 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2687 },
2172 }
2173#endif
2174 }
2175
2176 return (0);
2177}
2178
2179struct memwin_init {

--- 613 unchanged lines hidden (view full) ---

2793 .intfver_vnic = FW_INTFVER(T5, VNIC),
2794 .intfver_ofld = FW_INTFVER(T5, OFLD),
2795 .intfver_ri = FW_INTFVER(T5, RI),
2796 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2797 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2798 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2799 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2800 },
2801 }, {
2802 .chip = CHELSIO_T6,
2803 .kld_name = "t6fw_cfg",
2804 .fw_mod_name = "t6fw",
2805 .fw_hdr = {
2806 .chip = FW_HDR_CHIP_T6,
2807 .fw_ver = htobe32_const(FW_VERSION(T6)),
2808 .intfver_nic = FW_INTFVER(T6, NIC),
2809 .intfver_vnic = FW_INTFVER(T6, VNIC),
2810 .intfver_ofld = FW_INTFVER(T6, OFLD),
2811 .intfver_ri = FW_INTFVER(T6, RI),
2812 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
2813 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
2814 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
2815 .intfver_fcoe = FW_INTFVER(T6, FCOE),
2816 },
2688 }
2689};
2690
2691static struct fw_info *
2692find_fw_info(int chip)
2693{
2694 int i;
2695

--- 412 unchanged lines hidden (view full) ---

3108 * things accordingly.
3109 */
3110 LIMIT_CAPS(nbmcaps);
3111 LIMIT_CAPS(linkcaps);
3112 LIMIT_CAPS(switchcaps);
3113 LIMIT_CAPS(niccaps);
3114 LIMIT_CAPS(toecaps);
3115 LIMIT_CAPS(rdmacaps);
2817 }
2818};
2819
2820static struct fw_info *
2821find_fw_info(int chip)
2822{
2823 int i;
2824

--- 412 unchanged lines hidden (view full) ---

3237 * things accordingly.
3238 */
3239 LIMIT_CAPS(nbmcaps);
3240 LIMIT_CAPS(linkcaps);
3241 LIMIT_CAPS(switchcaps);
3242 LIMIT_CAPS(niccaps);
3243 LIMIT_CAPS(toecaps);
3244 LIMIT_CAPS(rdmacaps);
3116 LIMIT_CAPS(tlscaps);
3245 LIMIT_CAPS(cryptocaps);
3117 LIMIT_CAPS(iscsicaps);
3118 LIMIT_CAPS(fcoecaps);
3119#undef LIMIT_CAPS
3120
3121 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3122 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3123 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3124 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);

--- 120 unchanged lines hidden (view full) ---

3245 sc->x = htobe16(caps.x); \
3246} while (0)
3247 READ_CAPS(nbmcaps);
3248 READ_CAPS(linkcaps);
3249 READ_CAPS(switchcaps);
3250 READ_CAPS(niccaps);
3251 READ_CAPS(toecaps);
3252 READ_CAPS(rdmacaps);
3246 LIMIT_CAPS(iscsicaps);
3247 LIMIT_CAPS(fcoecaps);
3248#undef LIMIT_CAPS
3249
3250 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3251 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3252 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3253 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);

--- 120 unchanged lines hidden (view full) ---

3374 sc->x = htobe16(caps.x); \
3375} while (0)
3376 READ_CAPS(nbmcaps);
3377 READ_CAPS(linkcaps);
3378 READ_CAPS(switchcaps);
3379 READ_CAPS(niccaps);
3380 READ_CAPS(toecaps);
3381 READ_CAPS(rdmacaps);
3253 READ_CAPS(tlscaps);
3382 READ_CAPS(cryptocaps);
3254 READ_CAPS(iscsicaps);
3255 READ_CAPS(fcoecaps);
3256
3257 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3258 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3259 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3260 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3261 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);

--- 192 unchanged lines hidden (view full) ---

3454 "unknown port_type (%d), mod_type (%d)\n",
3455 pi->port_type, pi->mod_type);
3456 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3457 ifmedia_set(media, m | IFM_UNKNOWN);
3458 break;
3459 }
3460 break;
3461
3383 READ_CAPS(iscsicaps);
3384 READ_CAPS(fcoecaps);
3385
3386 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3387 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3388 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3389 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3390 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);

--- 192 unchanged lines hidden (view full) ---

3583 "unknown port_type (%d), mod_type (%d)\n",
3584 pi->port_type, pi->mod_type);
3585 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3586 ifmedia_set(media, m | IFM_UNKNOWN);
3587 break;
3588 }
3589 break;
3590
3591 case FW_PORT_TYPE_CR_QSFP:
3592 case FW_PORT_TYPE_CR_SFP28:
3593 case FW_PORT_TYPE_SFP28:
3594 case FW_PORT_TYPE_KR_SFP28:
3595 switch (pi->mod_type) {
3596
3597 case FW_PORT_MOD_TYPE_SR:
3598 ifmedia_add(media, m | IFM_25G_SR, 0, NULL);
3599 ifmedia_set(media, m | IFM_25G_SR);
3600 break;
3601
3602 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3603 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3604 ifmedia_add(media, m | IFM_25G_CR, 0, NULL);
3605 ifmedia_set(media, m | IFM_25G_CR);
3606 break;
3607
3608 case FW_PORT_MOD_TYPE_NONE:
3609 m &= ~IFM_FDX;
3610 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3611 ifmedia_set(media, m | IFM_NONE);
3612 break;
3613
3614 default:
3615 device_printf(pi->dev,
3616 "unknown port_type (%d), mod_type (%d)\n",
3617 pi->port_type, pi->mod_type);
3618 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3619 ifmedia_set(media, m | IFM_UNKNOWN);
3620 break;
3621 }
3622 break;
3623
3462 case FW_PORT_TYPE_QSFP:
3463 switch (pi->mod_type) {
3464
3465 case FW_PORT_MOD_TYPE_LR:
3466 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3467 ifmedia_set(media, m | IFM_40G_LR4);
3468 break;
3469

--- 19 unchanged lines hidden (view full) ---

3489 "unknown port_type (%d), mod_type (%d)\n",
3490 pi->port_type, pi->mod_type);
3491 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3492 ifmedia_set(media, m | IFM_UNKNOWN);
3493 break;
3494 }
3495 break;
3496
3624 case FW_PORT_TYPE_QSFP:
3625 switch (pi->mod_type) {
3626
3627 case FW_PORT_MOD_TYPE_LR:
3628 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3629 ifmedia_set(media, m | IFM_40G_LR4);
3630 break;
3631

--- 19 unchanged lines hidden (view full) ---

3651 "unknown port_type (%d), mod_type (%d)\n",
3652 pi->port_type, pi->mod_type);
3653 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3654 ifmedia_set(media, m | IFM_UNKNOWN);
3655 break;
3656 }
3657 break;
3658
3659 case FW_PORT_TYPE_KR4_100G:
3660 case FW_PORT_TYPE_CR4_QSFP:
3661 switch (pi->mod_type) {
3662
3663 case FW_PORT_MOD_TYPE_LR:
3664 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL);
3665 ifmedia_set(media, m | IFM_100G_LR4);
3666 break;
3667
3668 case FW_PORT_MOD_TYPE_SR:
3669 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL);
3670 ifmedia_set(media, m | IFM_100G_SR4);
3671 break;
3672
3673 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3674 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3675 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL);
3676 ifmedia_set(media, m | IFM_100G_CR4);
3677 break;
3678
3679 case FW_PORT_MOD_TYPE_NONE:
3680 m &= ~IFM_FDX;
3681 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3682 ifmedia_set(media, m | IFM_NONE);
3683 break;
3684
3685 default:
3686 device_printf(pi->dev,
3687 "unknown port_type (%d), mod_type (%d)\n",
3688 pi->port_type, pi->mod_type);
3689 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3690 ifmedia_set(media, m | IFM_UNKNOWN);
3691 break;
3692 }
3693 break;
3694
3497 default:
3498 device_printf(pi->dev,
3499 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3500 pi->mod_type);
3501 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3502 ifmedia_set(media, m | IFM_UNKNOWN);
3503 break;
3504 }

--- 724 unchanged lines hidden (view full) ---

4229 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4230 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4231#else
4232 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4233 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4234 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4235 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4236#endif
3695 default:
3696 device_printf(pi->dev,
3697 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3698 pi->mod_type);
3699 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3700 ifmedia_set(media, m | IFM_UNKNOWN);
3701 break;
3702 }

--- 724 unchanged lines hidden (view full) ---

4427 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4428 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4429#else
4430 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4431 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4432 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4433 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4434#endif
4237 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
4435 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
4238 if (rc != 0) {
4239 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4240 goto done;
4241 }
4242
4243 vi->rss = rss;
4244 vi->flags |= VI_INIT_DONE;
4245done:

--- 339 unchanged lines hidden (view full) ---

4585 "\006HASHFILTER\007ETHOFLD",
4586 "\20\001TOE", /* 4: TOE */
4587 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4588 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4589 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4590 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4591 "\007T10DIF"
4592 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4436 if (rc != 0) {
4437 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4438 goto done;
4439 }
4440
4441 vi->rss = rss;
4442 vi->flags |= VI_INIT_DONE;
4443done:

--- 339 unchanged lines hidden (view full) ---

4783 "\006HASHFILTER\007ETHOFLD",
4784 "\20\001TOE", /* 4: TOE */
4785 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4786 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4787 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4788 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4789 "\007T10DIF"
4790 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4593 "\20\00KEYS", /* 7: TLS */
4791 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
4594 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4595 "\004PO_INITIATOR\005PO_TARGET",
4596};
4597
4598void
4599t4_sysctls(struct adapter *sc)
4600{
4601 struct sysctl_ctx_list *ctx;

--- 91 unchanged lines hidden (view full) ---

4693
4694 SYSCTL_CAP(nbmcaps, 0, "NBM");
4695 SYSCTL_CAP(linkcaps, 1, "link");
4696 SYSCTL_CAP(switchcaps, 2, "switch");
4697 SYSCTL_CAP(niccaps, 3, "NIC");
4698 SYSCTL_CAP(toecaps, 4, "TCP offload");
4699 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4700 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4792 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4793 "\004PO_INITIATOR\005PO_TARGET",
4794};
4795
4796void
4797t4_sysctls(struct adapter *sc)
4798{
4799 struct sysctl_ctx_list *ctx;

--- 91 unchanged lines hidden (view full) ---

4891
4892 SYSCTL_CAP(nbmcaps, 0, "NBM");
4893 SYSCTL_CAP(linkcaps, 1, "link");
4894 SYSCTL_CAP(switchcaps, 2, "switch");
4895 SYSCTL_CAP(niccaps, 3, "NIC");
4896 SYSCTL_CAP(toecaps, 4, "TCP offload");
4897 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4898 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4701 SYSCTL_CAP(tlscaps, 7, "TLS");
4899 SYSCTL_CAP(cryptocaps, 7, "crypto");
4702 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4703#undef SYSCTL_CAP
4704
4705 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4706 NULL, sc->tids.nftids, "number of filters");
4707
4708 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4709 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",

--- 159 unchanged lines hidden (view full) ---

4869 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4870 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4871 sysctl_tx_rate, "A", "Tx rate");
4872
4873 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4874 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4875 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4876
4900 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4901#undef SYSCTL_CAP
4902
4903 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4904 NULL, sc->tids.nftids, "number of filters");
4905
4906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4907 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",

--- 159 unchanged lines hidden (view full) ---

5067 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
5068 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5069 sysctl_tx_rate, "A", "Tx rate");
5070
5071 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
5072 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5073 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
5074
4877 if (is_t5(sc)) {
5075 if (chip_id(sc) >= CHELSIO_T5) {
4878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4879 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4880 sysctl_wcwr_stats, "A", "write combined work requests");
4881 }
4882#endif
4883
4884#ifdef TCP_OFFLOAD
4885 if (is_offload(sc)) {

--- 2127 unchanged lines hidden (view full) ---

7013
7014 if (t->natids) {
7015 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
7016 t->atids_in_use);
7017 }
7018
7019 if (t->ntids) {
7020 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
5076 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
5077 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5078 sysctl_wcwr_stats, "A", "write combined work requests");
5079 }
5080#endif
5081
5082#ifdef TCP_OFFLOAD
5083 if (is_offload(sc)) {

--- 2127 unchanged lines hidden (view full) ---

7211
7212 if (t->natids) {
7213 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
7214 t->atids_in_use);
7215 }
7216
7217 if (t->ntids) {
7218 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7021 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
7219 uint32_t b;
7022
7220
7221 if (chip_id(sc) <= CHELSIO_T5)
7222 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
7223 else
7224 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
7225
7023 if (b) {
7024 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
7025 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
7026 t->ntids - 1);
7027 } else {
7028 sbuf_printf(sb, "TID range: %u-%u",
7029 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
7030 t->ntids - 1);

--- 437 unchanged lines hidden (view full) ---

7468
7469static int
7470sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7471{
7472 struct adapter *sc = arg1;
7473 struct sbuf *sb;
7474 int rc, v;
7475
7226 if (b) {
7227 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
7228 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
7229 t->ntids - 1);
7230 } else {
7231 sbuf_printf(sb, "TID range: %u-%u",
7232 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
7233 t->ntids - 1);

--- 437 unchanged lines hidden (view full) ---

7671
7672static int
7673sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7674{
7675 struct adapter *sc = arg1;
7676 struct sbuf *sb;
7677 int rc, v;
7678
7679 MPASS(chip_id(sc) >= CHELSIO_T5);
7680
7476 rc = sysctl_wire_old_buffer(req, 0);
7477 if (rc != 0)
7478 return (rc);
7479
7480 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7481 if (sb == NULL)
7482 return (ENOMEM);
7483
7484 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7485 if (G_STATSOURCE_T5(v) == 7) {
7681 rc = sysctl_wire_old_buffer(req, 0);
7682 if (rc != 0)
7683 return (rc);
7684
7685 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7686 if (sb == NULL)
7687 return (ENOMEM);
7688
7689 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7690 if (G_STATSOURCE_T5(v) == 7) {
7486 if (G_STATMODE(v) == 0) {
7691 int mode;
7692
7693 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
7694 if (mode == 0) {
7487 sbuf_printf(sb, "total %d, incomplete %d",
7488 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7489 t4_read_reg(sc, A_SGE_STAT_MATCH));
7695 sbuf_printf(sb, "total %d, incomplete %d",
7696 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7697 t4_read_reg(sc, A_SGE_STAT_MATCH));
7490 } else if (G_STATMODE(v) == 1) {
7698 } else if (mode == 1) {
7491 sbuf_printf(sb, "total %d, data overflow %d",
7492 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7493 t4_read_reg(sc, A_SGE_STAT_MATCH));
7699 sbuf_printf(sb, "total %d, data overflow %d",
7700 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7701 t4_read_reg(sc, A_SGE_STAT_MATCH));
7702 } else {
7703 sbuf_printf(sb, "unknown mode %d", mode);
7494 }
7495 }
7496 rc = sbuf_finish(sb);
7497 sbuf_delete(sb);
7498
7499 return (rc);
7500}
7501

--- 2049 unchanged lines hidden (view full) ---

9551done_unload:
9552 sx_xunlock(&mlu);
9553 break;
9554 }
9555
9556 return (rc);
9557}
9558
7704 }
7705 }
7706 rc = sbuf_finish(sb);
7707 sbuf_delete(sb);
7708
7709 return (rc);
7710}
7711

--- 2049 unchanged lines hidden (view full) ---

9761done_unload:
9762 sx_xunlock(&mlu);
9763 break;
9764 }
9765
9766 return (rc);
9767}
9768
9559static devclass_t t4_devclass, t5_devclass;
9560static devclass_t cxgbe_devclass, cxl_devclass;
9561static devclass_t vcxgbe_devclass, vcxl_devclass;
9769static devclass_t t4_devclass, t5_devclass, t6_devclass;
9770static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
9771static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
9562
9563DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9564MODULE_VERSION(t4nex, 1);
9565MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9566#ifdef DEV_NETMAP
9567MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
9568#endif /* DEV_NETMAP */
9569
9772
9773DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9774MODULE_VERSION(t4nex, 1);
9775MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9776#ifdef DEV_NETMAP
9777MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
9778#endif /* DEV_NETMAP */
9779
9570
9571DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9572MODULE_VERSION(t5nex, 1);
9573MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9574#ifdef DEV_NETMAP
9575MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
9576#endif /* DEV_NETMAP */
9577
9780DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9781MODULE_VERSION(t5nex, 1);
9782MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9783#ifdef DEV_NETMAP
9784MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
9785#endif /* DEV_NETMAP */
9786
9787DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
9788MODULE_VERSION(t6nex, 1);
9789MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
9790#ifdef DEV_NETMAP
9791MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
9792#endif /* DEV_NETMAP */
9793
9578DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9579MODULE_VERSION(cxgbe, 1);
9580
9581DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9582MODULE_VERSION(cxl, 1);
9583
9794DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9795MODULE_VERSION(cxgbe, 1);
9796
9797DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9798MODULE_VERSION(cxl, 1);
9799
9800DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
9801MODULE_VERSION(cc, 1);
9802
9584DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9585MODULE_VERSION(vcxgbe, 1);
9586
9587DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9588MODULE_VERSION(vcxl, 1);
9803DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9804MODULE_VERSION(vcxgbe, 1);
9805
9806DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9807MODULE_VERSION(vcxl, 1);
9808
9809DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
9810MODULE_VERSION(vcc, 1);