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bxe_elink.c (255736) bxe_elink.c (258187)
1/*-
2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
3 *
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

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27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
3 *
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

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27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bxe/bxe_elink.c 255736 2013-09-20 20:18:49Z davidch $");
35__FBSDID("$FreeBSD: head/sys/dev/bxe/bxe_elink.c 258187 2013-11-15 20:26:14Z edavis $");
36
37#include "bxe.h"
38#include "bxe_elink.h"
39#include "ecore_mfw_req.h"
40#include "ecore_fw_defs.h"
41#include "ecore_hsi.h"
42#include "ecore_reg.h"
43

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602#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
603#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
604#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
605#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
606#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
607#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
608#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
609#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
36
37#include "bxe.h"
38#include "bxe_elink.h"
39#include "ecore_mfw_req.h"
40#include "ecore_fw_defs.h"
41#include "ecore_hsi.h"
42#include "ecore_reg.h"
43

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602#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
603#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
604#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
605#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
606#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
607#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
608#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
609#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
610#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
610#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
611#define MDIO_WC_REG_XGXS_STATUS3 0x8129
612#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
613#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
614#define MDIO_WC_REG_XGXS_STATUS4 0x813c
615#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
616#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
617#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B

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4627 (1<<11));
4628
4629 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4630 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
4631 elink_set_aer_mmd(params, phy);
4632
4633 elink_warpcore_enable_AN_KR2(phy, params, vars);
4634 } else {
611#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
612#define MDIO_WC_REG_XGXS_STATUS3 0x8129
613#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
614#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
615#define MDIO_WC_REG_XGXS_STATUS4 0x813c
616#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
617#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
618#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B

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4628 (1<<11));
4629
4630 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4631 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
4632 elink_set_aer_mmd(params, phy);
4633
4634 elink_warpcore_enable_AN_KR2(phy, params, vars);
4635 } else {
4636 /* Enable Auto-Detect to support 1G over CL37 as well */
4637 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4638 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
4639
4640 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
4641 * parallel-detect loop when CL73 and CL37 are enabled.
4642 */
4643 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4644 MDIO_AER_BLOCK_AER_REG, 0);
4645 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4646 MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
4647 elink_set_aer_mmd(params, phy);
4648
4635 elink_disable_kr2(params, vars, phy);
4636 }
4637
4638 /* Enable Autoneg: only on the main lane */
4639 elink_warpcore_restart_AN_KR(phy, params);
4640}
4641
4642static void elink_warpcore_set_10G_KR(struct elink_phy *phy,

--- 2669 unchanged lines hidden (view full) ---

7312 if (non_ext_phy ||
7313 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7314 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
7315 struct elink_phy *phy = &params->phy[ELINK_INT_PHY];
7316 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
7317 (CHIP_IS_E1x(sc) ||
7318 CHIP_IS_E2(sc)))
7319 elink_set_parallel_detection(phy, params);
4649 elink_disable_kr2(params, vars, phy);
4650 }
4651
4652 /* Enable Autoneg: only on the main lane */
4653 elink_warpcore_restart_AN_KR(phy, params);
4654}
4655
4656static void elink_warpcore_set_10G_KR(struct elink_phy *phy,

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7326 if (non_ext_phy ||
7327 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7328 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
7329 struct elink_phy *phy = &params->phy[ELINK_INT_PHY];
7330 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
7331 (CHIP_IS_E1x(sc) ||
7332 CHIP_IS_E2(sc)))
7333 elink_set_parallel_detection(phy, params);
7320 if (params->phy[ELINK_INT_PHY].config_init)
7321 params->phy[ELINK_INT_PHY].config_init(phy,
7322 params,
7323 vars);
7334 if (params->phy[ELINK_INT_PHY].config_init)
7335 params->phy[ELINK_INT_PHY].config_init(phy, params, vars);
7324 }
7325
7326 /* Re-read this value in case it was changed inside config_init due to
7327 * limitations of optic module
7328 */
7329 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7330
7331 /* Init external phy*/

--- 1567 unchanged lines hidden (view full) ---

8899
8900 if (copper_module_type &
8901 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8902 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n");
8903 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8904 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
8905 else
8906 check_limiting_mode = 1;
7336 }
7337
7338 /* Re-read this value in case it was changed inside config_init due to
7339 * limitations of optic module
7340 */
7341 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7342
7343 /* Init external phy*/

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8911
8912 if (copper_module_type &
8913 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8914 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n");
8915 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8916 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
8917 else
8918 check_limiting_mode = 1;
8907 } else if (copper_module_type &
8908 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8909 ELINK_DEBUG_P0(sc,
8910 "Passive Copper cable detected\n");
8911 *edc_mode =
8912 ELINK_EDC_MODE_PASSIVE_DAC;
8913 } else {
8919 } else {
8914 ELINK_DEBUG_P1(sc,
8915 "Unknown copper-cable-type 0x%x !!!\n",
8916 copper_module_type);
8917 return ELINK_STATUS_ERROR;
8920 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
8921 /* Even in case PASSIVE_DAC indication is not set,
8922 * treat it as a passive DAC cable, since some cables
8923 * don't have this indication.
8924 */
8925 if (copper_module_type &
8926 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8927 ELINK_DEBUG_P0(sc,
8928 "Passive Copper cable detected\n");
8929 } else {
8930 ELINK_DEBUG_P0(sc,
8931 "Unknown copper-cable-type\n");
8932 }
8918 }
8919 break;
8920 }
8921 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
8922 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
8923 check_limiting_mode = 1;
8924 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
8925 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |

--- 5429 unchanged lines hidden (view full) ---

14355 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n");
14356 break;
14357 default:
14358 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n");
14359 }
14360 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up,
14361 old_status, status);
14362
8933 }
8934 break;
8935 }
8936 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
8937 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
8938 check_limiting_mode = 1;
8939 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
8940 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |

--- 5429 unchanged lines hidden (view full) ---

14370 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n");
14371 break;
14372 default:
14373 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n");
14374 }
14375 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up,
14376 old_status, status);
14377
14378 /* Do not touch the link in case physical link down */
14379 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
14380 return 1;
14381
14363 /* a. Update shmem->link_status accordingly
14364 * b. Update elink_vars->link_up
14365 */
14366 if (status) {
14367 vars->link_status &= ~LINK_STATUS_LINK_UP;
14368 vars->link_status |= link_flag;
14369 vars->link_up = 0;
14370 vars->phy_flags |= phy_flag;

--- 377 unchanged lines hidden --- 		14382 /* a. Update shmem->link_status accordingly
14383 * b. Update elink_vars->link_up
14384 */
14385 if (status) {
14386 vars->link_status &= ~LINK_STATUS_LINK_UP;
14387 vars->link_status |= link_flag;
14388 vars->link_up = 0;
14389 vars->phy_flags |= phy_flag;

--- 377 unchanged lines hidden ---