18 */
19#ifndef _ATH_AH_INTERAL_H_
20#define _ATH_AH_INTERAL_H_
21/*
22 * Atheros Device Hardware Access Layer (HAL).
23 *
24 * Internal definitions.
25 */
26#define AH_NULL 0
27#define AH_MIN(a,b) ((a)<(b)?(a):(b))
28#define AH_MAX(a,b) ((a)>(b)?(a):(b))
29
30#include <net80211/_ieee80211.h>
31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */
32
33#ifndef NBBY
34#define NBBY 8 /* number of bits/byte */
35#endif
36
37#ifndef roundup
38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
39#endif
40#ifndef howmany
41#define howmany(x, y) (((x)+((y)-1))/(y))
42#endif
43
44#ifndef offsetof
45#define offsetof(type, field) ((size_t)(&((type *)0)->field))
46#endif
47
48typedef struct {
49 uint16_t start; /* first register */
50 uint16_t end; /* ending register or zero */
51} HAL_REGRANGE;
52
53typedef struct {
54 uint32_t addr; /* regiser address/offset */
55 uint32_t value; /* value to write */
56} HAL_REGWRITE;
57
58/*
59 * Transmit power scale factor.
60 *
61 * NB: This is not public because we want to discourage the use of
62 * scaling; folks should use the tx power limit interface.
63 */
64typedef enum {
65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
69 HAL_TP_SCALE_MIN = 4, /* min, but still on */
70} HAL_TP_SCALE;
71
72typedef enum {
73 HAL_CAP_RADAR = 0, /* Radar capability */
74 HAL_CAP_AR = 1, /* AR capability */
75} HAL_PHYDIAG_CAPS;
76
77/*
78 * Each chip or class of chips registers to offer support.
79 */
80struct ath_hal_chip {
81 const char *name;
82 const char *(*probe)(uint16_t vendorid, uint16_t devid);
83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
85 HAL_STATUS *error);
86};
87#ifndef AH_CHIP
88#define AH_CHIP(_name, _probe, _attach) \
89static struct ath_hal_chip _name##_chip = { \
90 .name = #_name, \
91 .probe = _probe, \
92 .attach = _attach \
93}; \
94OS_DATA_SET(ah_chips, _name##_chip)
95#endif
96
97/*
98 * Each RF backend registers to offer support; this is mostly
99 * used by multi-chip 5212 solutions. Single-chip solutions
100 * have a fixed idea about which RF to use.
101 */
102struct ath_hal_rf {
103 const char *name;
104 HAL_BOOL (*probe)(struct ath_hal *ah);
105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
106};
107#ifndef AH_RF
108#define AH_RF(_name, _probe, _attach) \
109static struct ath_hal_rf _name##_rf = { \
110 .name = __STRING(_name), \
111 .probe = _probe, \
112 .attach = _attach \
113}; \
114OS_DATA_SET(ah_rfs, _name##_rf)
115#endif
116
117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
118
119/*
120 * Maximum number of internal channels. Entries are per unique
121 * frequency so this might be need to be increased to handle all
122 * usage cases; typically no more than 32 are really needed but
123 * dynamically allocating the data structures is a bit painful
124 * right now.
125 */
126#ifndef AH_MAXCHAN
127#define AH_MAXCHAN 96
128#endif
129
130/*
131 * Internal per-channel state. These are found
132 * using ic_devdata in the ieee80211_channel.
133 */
134typedef struct {
135 uint16_t channel; /* h/w frequency, NB: may be mapped */
136 uint8_t privFlags;
137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */
138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */
139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */
140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */
141 uint8_t calValid; /* bitmask of cal types */
142 int8_t iCoff;
143 int8_t qCoff;
144 int16_t rawNoiseFloor;
145 int16_t noiseFloorAdjust;
146#ifdef AH_SUPPORT_AR5416
147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS];
148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS];
149#endif /* AH_SUPPORT_AR5416 */
150 uint16_t mainSpur; /* cached spur value for this channel */
151} HAL_CHANNEL_INTERNAL;
152
153/* channel requires noise floor check */
154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0
155
156/* all full-width channels */
157#define IEEE80211_CHAN_ALLFULL \
158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
159#define IEEE80211_CHAN_ALLTURBOFULL \
160 (IEEE80211_CHAN_ALLTURBO - \
161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
162
163typedef struct {
164 uint32_t halChanSpreadSupport : 1,
165 halSleepAfterBeaconBroken : 1,
166 halCompressSupport : 1,
167 halBurstSupport : 1,
168 halFastFramesSupport : 1,
169 halChapTuningSupport : 1,
170 halTurboGSupport : 1,
171 halTurboPrimeSupport : 1,
172 halMicAesCcmSupport : 1,
173 halMicCkipSupport : 1,
174 halMicTkipSupport : 1,
175 halTkipMicTxRxKeySupport : 1,
176 halCipherAesCcmSupport : 1,
177 halCipherCkipSupport : 1,
178 halCipherTkipSupport : 1,
179 halPSPollBroken : 1,
180 halVEOLSupport : 1,
181 halBssIdMaskSupport : 1,
182 halMcastKeySrchSupport : 1,
183 halTsfAddSupport : 1,
184 halChanHalfRate : 1,
185 halChanQuarterRate : 1,
186 halHTSupport : 1,
187 halRfSilentSupport : 1,
188 halHwPhyCounterSupport : 1,
189 halWowSupport : 1,
190 halWowMatchPatternExact : 1,
191 halAutoSleepSupport : 1,
192 halFastCCSupport : 1,
193 halBtCoexSupport : 1;
194 uint32_t halRxStbcSupport : 1,
195 halTxStbcSupport : 1,
196 halGTTSupport : 1,
197 halCSTSupport : 1,
198 halRifsRxSupport : 1,
199 halRifsTxSupport : 1,
200 halExtChanDfsSupport : 1,
201 halForcePpmSupport : 1,
202 halEnhancedPmSupport : 1,
203 halMbssidAggrSupport : 1,
204 halBssidMatchSupport : 1,
205 hal4kbSplitTransSupport : 1,
206 halHasPsPollSupport : 1,
207 halHasRxSelfLinkedTail : 1;
208 uint32_t halWirelessModes;
209 uint16_t halTotalQueues;
210 uint16_t halKeyCacheSize;
211 uint16_t halLow5GhzChan, halHigh5GhzChan;
212 uint16_t halLow2GhzChan, halHigh2GhzChan;
213 int halTstampPrecision;
214 int halRtsAggrLimit;
215 uint8_t halTxChainMask;
216 uint8_t halRxChainMask;
217 uint8_t halNumGpioPins;
218 uint8_t halNumAntCfg2GHz;
219 uint8_t halNumAntCfg5GHz;
220 uint32_t halIntrMask;
221 uint8_t halTxStreams;
222 uint8_t halRxStreams;
223} HAL_CAPABILITIES;
224
225struct regDomain;
226
227/*
228 * The ``private area'' follows immediately after the ``public area''
229 * in the data structure returned by ath_hal_attach. Private data are
230 * used by device-independent code such as the regulatory domain support.
231 * In general, code within the HAL should never depend on data in the
232 * public area. Instead any public data needed internally should be
233 * shadowed here.
234 *
235 * When declaring a device-specific ath_hal data structure this structure
236 * is assumed to at the front; e.g.
237 *
238 * struct ath_hal_5212 {
239 * struct ath_hal_private ah_priv;
240 * ...
241 * };
242 *
243 * It might be better to manage the method pointers in this structure
244 * using an indirect pointer to a read-only data structure but this would
245 * disallow class-style method overriding.
246 */
247struct ath_hal_private {
248 struct ath_hal h; /* public area */
249
250 /* NB: all methods go first to simplify initialization */
251 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
252 uint16_t channelFlags,
253 uint16_t *lowChannel, uint16_t *highChannel);
254 u_int (*ah_getWirelessModes)(struct ath_hal*);
255 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
256 uint16_t *data);
257 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
258 uint16_t data);
259 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
260 struct ieee80211_channel *);
261 int16_t (*ah_getNfAdjust)(struct ath_hal *,
262 const HAL_CHANNEL_INTERNAL*);
263 void (*ah_getNoiseFloor)(struct ath_hal *,
264 int16_t nfarray[]);
265
266 void *ah_eeprom; /* opaque EEPROM state */
267 uint16_t ah_eeversion; /* EEPROM version */
268 void (*ah_eepromDetach)(struct ath_hal *);
269 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
270 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int);
271 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
272 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
273 const void *args, uint32_t argsize,
274 void **result, uint32_t *resultsize);
275
276 /*
277 * Device revision information.
278 */
279 uint16_t ah_devid; /* PCI device ID */
280 uint16_t ah_subvendorid; /* PCI subvendor ID */
281 uint32_t ah_macVersion; /* MAC version id */
282 uint16_t ah_macRev; /* MAC revision */
283 uint16_t ah_phyRev; /* PHY revision */
284 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
285 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
286 uint8_t ah_ispcie; /* PCIE, special treatment */
287
288 HAL_OPMODE ah_opmode; /* operating mode from reset */
289 const struct ieee80211_channel *ah_curchan;/* operating channel */
290 HAL_CAPABILITIES ah_caps; /* device capabilities */
291 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
292 int16_t ah_powerLimit; /* tx power cap */
293 uint16_t ah_maxPowerLevel; /* calculated max tx power */
294 u_int ah_tpScale; /* tx power scale factor */
295 uint32_t ah_11nCompat; /* 11n compat controls */
296
297 /*
298 * State for regulatory domain handling.
299 */
300 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */
| 18 */
19#ifndef _ATH_AH_INTERAL_H_
20#define _ATH_AH_INTERAL_H_
21/*
22 * Atheros Device Hardware Access Layer (HAL).
23 *
24 * Internal definitions.
25 */
26#define AH_NULL 0
27#define AH_MIN(a,b) ((a)<(b)?(a):(b))
28#define AH_MAX(a,b) ((a)>(b)?(a):(b))
29
30#include <net80211/_ieee80211.h>
31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */
32
33#ifndef NBBY
34#define NBBY 8 /* number of bits/byte */
35#endif
36
37#ifndef roundup
38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
39#endif
40#ifndef howmany
41#define howmany(x, y) (((x)+((y)-1))/(y))
42#endif
43
44#ifndef offsetof
45#define offsetof(type, field) ((size_t)(&((type *)0)->field))
46#endif
47
48typedef struct {
49 uint16_t start; /* first register */
50 uint16_t end; /* ending register or zero */
51} HAL_REGRANGE;
52
53typedef struct {
54 uint32_t addr; /* regiser address/offset */
55 uint32_t value; /* value to write */
56} HAL_REGWRITE;
57
58/*
59 * Transmit power scale factor.
60 *
61 * NB: This is not public because we want to discourage the use of
62 * scaling; folks should use the tx power limit interface.
63 */
64typedef enum {
65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
69 HAL_TP_SCALE_MIN = 4, /* min, but still on */
70} HAL_TP_SCALE;
71
72typedef enum {
73 HAL_CAP_RADAR = 0, /* Radar capability */
74 HAL_CAP_AR = 1, /* AR capability */
75} HAL_PHYDIAG_CAPS;
76
77/*
78 * Each chip or class of chips registers to offer support.
79 */
80struct ath_hal_chip {
81 const char *name;
82 const char *(*probe)(uint16_t vendorid, uint16_t devid);
83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
85 HAL_STATUS *error);
86};
87#ifndef AH_CHIP
88#define AH_CHIP(_name, _probe, _attach) \
89static struct ath_hal_chip _name##_chip = { \
90 .name = #_name, \
91 .probe = _probe, \
92 .attach = _attach \
93}; \
94OS_DATA_SET(ah_chips, _name##_chip)
95#endif
96
97/*
98 * Each RF backend registers to offer support; this is mostly
99 * used by multi-chip 5212 solutions. Single-chip solutions
100 * have a fixed idea about which RF to use.
101 */
102struct ath_hal_rf {
103 const char *name;
104 HAL_BOOL (*probe)(struct ath_hal *ah);
105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
106};
107#ifndef AH_RF
108#define AH_RF(_name, _probe, _attach) \
109static struct ath_hal_rf _name##_rf = { \
110 .name = __STRING(_name), \
111 .probe = _probe, \
112 .attach = _attach \
113}; \
114OS_DATA_SET(ah_rfs, _name##_rf)
115#endif
116
117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
118
119/*
120 * Maximum number of internal channels. Entries are per unique
121 * frequency so this might be need to be increased to handle all
122 * usage cases; typically no more than 32 are really needed but
123 * dynamically allocating the data structures is a bit painful
124 * right now.
125 */
126#ifndef AH_MAXCHAN
127#define AH_MAXCHAN 96
128#endif
129
130/*
131 * Internal per-channel state. These are found
132 * using ic_devdata in the ieee80211_channel.
133 */
134typedef struct {
135 uint16_t channel; /* h/w frequency, NB: may be mapped */
136 uint8_t privFlags;
137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */
138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */
139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */
140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */
141 uint8_t calValid; /* bitmask of cal types */
142 int8_t iCoff;
143 int8_t qCoff;
144 int16_t rawNoiseFloor;
145 int16_t noiseFloorAdjust;
146#ifdef AH_SUPPORT_AR5416
147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS];
148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS];
149#endif /* AH_SUPPORT_AR5416 */
150 uint16_t mainSpur; /* cached spur value for this channel */
151} HAL_CHANNEL_INTERNAL;
152
153/* channel requires noise floor check */
154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0
155
156/* all full-width channels */
157#define IEEE80211_CHAN_ALLFULL \
158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
159#define IEEE80211_CHAN_ALLTURBOFULL \
160 (IEEE80211_CHAN_ALLTURBO - \
161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
162
163typedef struct {
164 uint32_t halChanSpreadSupport : 1,
165 halSleepAfterBeaconBroken : 1,
166 halCompressSupport : 1,
167 halBurstSupport : 1,
168 halFastFramesSupport : 1,
169 halChapTuningSupport : 1,
170 halTurboGSupport : 1,
171 halTurboPrimeSupport : 1,
172 halMicAesCcmSupport : 1,
173 halMicCkipSupport : 1,
174 halMicTkipSupport : 1,
175 halTkipMicTxRxKeySupport : 1,
176 halCipherAesCcmSupport : 1,
177 halCipherCkipSupport : 1,
178 halCipherTkipSupport : 1,
179 halPSPollBroken : 1,
180 halVEOLSupport : 1,
181 halBssIdMaskSupport : 1,
182 halMcastKeySrchSupport : 1,
183 halTsfAddSupport : 1,
184 halChanHalfRate : 1,
185 halChanQuarterRate : 1,
186 halHTSupport : 1,
187 halRfSilentSupport : 1,
188 halHwPhyCounterSupport : 1,
189 halWowSupport : 1,
190 halWowMatchPatternExact : 1,
191 halAutoSleepSupport : 1,
192 halFastCCSupport : 1,
193 halBtCoexSupport : 1;
194 uint32_t halRxStbcSupport : 1,
195 halTxStbcSupport : 1,
196 halGTTSupport : 1,
197 halCSTSupport : 1,
198 halRifsRxSupport : 1,
199 halRifsTxSupport : 1,
200 halExtChanDfsSupport : 1,
201 halForcePpmSupport : 1,
202 halEnhancedPmSupport : 1,
203 halMbssidAggrSupport : 1,
204 halBssidMatchSupport : 1,
205 hal4kbSplitTransSupport : 1,
206 halHasPsPollSupport : 1,
207 halHasRxSelfLinkedTail : 1;
208 uint32_t halWirelessModes;
209 uint16_t halTotalQueues;
210 uint16_t halKeyCacheSize;
211 uint16_t halLow5GhzChan, halHigh5GhzChan;
212 uint16_t halLow2GhzChan, halHigh2GhzChan;
213 int halTstampPrecision;
214 int halRtsAggrLimit;
215 uint8_t halTxChainMask;
216 uint8_t halRxChainMask;
217 uint8_t halNumGpioPins;
218 uint8_t halNumAntCfg2GHz;
219 uint8_t halNumAntCfg5GHz;
220 uint32_t halIntrMask;
221 uint8_t halTxStreams;
222 uint8_t halRxStreams;
223} HAL_CAPABILITIES;
224
225struct regDomain;
226
227/*
228 * The ``private area'' follows immediately after the ``public area''
229 * in the data structure returned by ath_hal_attach. Private data are
230 * used by device-independent code such as the regulatory domain support.
231 * In general, code within the HAL should never depend on data in the
232 * public area. Instead any public data needed internally should be
233 * shadowed here.
234 *
235 * When declaring a device-specific ath_hal data structure this structure
236 * is assumed to at the front; e.g.
237 *
238 * struct ath_hal_5212 {
239 * struct ath_hal_private ah_priv;
240 * ...
241 * };
242 *
243 * It might be better to manage the method pointers in this structure
244 * using an indirect pointer to a read-only data structure but this would
245 * disallow class-style method overriding.
246 */
247struct ath_hal_private {
248 struct ath_hal h; /* public area */
249
250 /* NB: all methods go first to simplify initialization */
251 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
252 uint16_t channelFlags,
253 uint16_t *lowChannel, uint16_t *highChannel);
254 u_int (*ah_getWirelessModes)(struct ath_hal*);
255 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
256 uint16_t *data);
257 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
258 uint16_t data);
259 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
260 struct ieee80211_channel *);
261 int16_t (*ah_getNfAdjust)(struct ath_hal *,
262 const HAL_CHANNEL_INTERNAL*);
263 void (*ah_getNoiseFloor)(struct ath_hal *,
264 int16_t nfarray[]);
265
266 void *ah_eeprom; /* opaque EEPROM state */
267 uint16_t ah_eeversion; /* EEPROM version */
268 void (*ah_eepromDetach)(struct ath_hal *);
269 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
270 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int);
271 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
272 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
273 const void *args, uint32_t argsize,
274 void **result, uint32_t *resultsize);
275
276 /*
277 * Device revision information.
278 */
279 uint16_t ah_devid; /* PCI device ID */
280 uint16_t ah_subvendorid; /* PCI subvendor ID */
281 uint32_t ah_macVersion; /* MAC version id */
282 uint16_t ah_macRev; /* MAC revision */
283 uint16_t ah_phyRev; /* PHY revision */
284 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
285 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
286 uint8_t ah_ispcie; /* PCIE, special treatment */
287
288 HAL_OPMODE ah_opmode; /* operating mode from reset */
289 const struct ieee80211_channel *ah_curchan;/* operating channel */
290 HAL_CAPABILITIES ah_caps; /* device capabilities */
291 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
292 int16_t ah_powerLimit; /* tx power cap */
293 uint16_t ah_maxPowerLevel; /* calculated max tx power */
294 u_int ah_tpScale; /* tx power scale factor */
295 uint32_t ah_11nCompat; /* 11n compat controls */
296
297 /*
298 * State for regulatory domain handling.
299 */
300 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */
|
301 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
302 u_int ah_nchan; /* valid items in ah_channels */
303 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */
304 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */
305
306 uint8_t ah_coverageClass; /* coverage class */
307 /*
308 * RF Silent handling; setup according to the EEPROM.
309 */
310 uint16_t ah_rfsilent; /* GPIO pin + polarity */
311 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
312 /*
313 * Diagnostic support for discriminating HIUERR reports.
314 */
315 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
316 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
317};
318
319#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
320
321#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
322 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
323#define ath_hal_getWirelessModes(_ah) \
324 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
325#define ath_hal_eepromRead(_ah, _off, _data) \
326 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
327#define ath_hal_eepromWrite(_ah, _off, _data) \
328 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
329#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
330 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
331#define ath_hal_gpioCfgInput(_ah, _gpio) \
332 (_ah)->ah_gpioCfgInput(_ah, _gpio)
333#define ath_hal_gpioGet(_ah, _gpio) \
334 (_ah)->ah_gpioGet(_ah, _gpio)
335#define ath_hal_gpioSet(_ah, _gpio, _val) \
336 (_ah)->ah_gpioSet(_ah, _gpio, _val)
337#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
338 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
339#define ath_hal_getpowerlimits(_ah, _chan) \
340 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
341#define ath_hal_getNfAdjust(_ah, _c) \
342 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
343#define ath_hal_getNoiseFloor(_ah, _nfArray) \
344 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
345#define ath_hal_configPCIE(_ah, _reset) \
346 (_ah)->ah_configPCIE(_ah, _reset)
347#define ath_hal_disablePCIE(_ah) \
348 (_ah)->ah_disablePCIE(_ah)
349#define ath_hal_setInterrupts(_ah, _mask) \
350 (_ah)->ah_setInterrupts(_ah, _mask)
351
352#define ath_hal_eepromDetach(_ah) do { \
353 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
354 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
355} while (0)
356#define ath_hal_eepromGet(_ah, _param, _val) \
357 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
358#define ath_hal_eepromSet(_ah, _param, _val) \
359 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
360#define ath_hal_eepromGetFlag(_ah, _param) \
361 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
362#define ath_hal_getSpurChan(_ah, _ix, _is2G) \
363 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
364#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
365 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
366
367#ifndef _NET_IF_IEEE80211_H_
368/*
369 * Stuff that would naturally come from _ieee80211.h
370 */
371#define IEEE80211_ADDR_LEN 6
372
373#define IEEE80211_WEP_IVLEN 3 /* 24bit */
374#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
375#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
376
377#define IEEE80211_CRC_LEN 4
378
379#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
380 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
381#endif /* _NET_IF_IEEE80211_H_ */
382
383#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
384
385#define INIT_AIFS 2
386#define INIT_CWMIN 15
387#define INIT_CWMIN_11B 31
388#define INIT_CWMAX 1023
389#define INIT_SH_RETRY 10
390#define INIT_LG_RETRY 10
391#define INIT_SSH_RETRY 32
392#define INIT_SLG_RETRY 32
393
394typedef struct {
395 uint32_t tqi_ver; /* HAL TXQ verson */
396 HAL_TX_QUEUE tqi_type; /* hw queue type*/
397 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
398 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
399 uint32_t tqi_priority;
400 uint32_t tqi_aifs; /* aifs */
401 uint32_t tqi_cwmin; /* cwMin */
402 uint32_t tqi_cwmax; /* cwMax */
403 uint16_t tqi_shretry; /* frame short retry limit */
404 uint16_t tqi_lgretry; /* frame long retry limit */
405 uint32_t tqi_cbrPeriod;
406 uint32_t tqi_cbrOverflowLimit;
407 uint32_t tqi_burstTime;
408 uint32_t tqi_readyTime;
409 uint32_t tqi_physCompBuf;
410 uint32_t tqi_intFlags; /* flags for internal use */
411} HAL_TX_QUEUE_INFO;
412
413extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
414 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
415extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
416 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
417
418typedef enum {
419 HAL_ANI_PRESENT = 0x1, /* is ANI support present */
420 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2, /* set level */
421 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, /* enable/disable */
422 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8, /* enable/disable */
423 HAL_ANI_FIRSTEP_LEVEL = 0x10, /* set level */
424 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20, /* set level */
425 HAL_ANI_MODE = 0x40, /* 0 => manual, 1 => auto (XXX do not change) */
426 HAL_ANI_PHYERR_RESET =0x80, /* reset phy error stats */
427 HAL_ANI_ALL = 0xff
428} HAL_ANI_CMD;
429
430#define HAL_SPUR_VAL_MASK 0x3FFF
431#define HAL_SPUR_CHAN_WIDTH 87
432#define HAL_BIN_WIDTH_BASE_100HZ 3125
433#define HAL_BIN_WIDTH_TURBO_100HZ 6250
434#define HAL_MAX_BINS_ALLOWED 28
435
436#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900)
437#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
438
439#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
440
441/*
442 * Deduce if the host cpu has big- or litt-endian byte order.
443 */
444static __inline__ int
445isBigEndian(void)
446{
447 union {
448 int32_t i;
449 char c[4];
450 } u;
451 u.i = 1;
452 return (u.c[0] == 0);
453}
454
455/* unalligned little endian access */
456#define LE_READ_2(p) \
457 ((uint16_t) \
458 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
459#define LE_READ_4(p) \
460 ((uint32_t) \
461 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
462 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
463
464/*
465 * Register manipulation macros that expect bit field defines
466 * to follow the convention that an _S suffix is appended for
467 * a shift count, while the field mask has no suffix.
468 */
469#define SM(_v, _f) (((_v) << _f##_S) & (_f))
470#define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
471#define OS_REG_RMW(_a, _r, _set, _clr) \
472 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
473#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
474 OS_REG_WRITE(_a, _r, \
475 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
476#define OS_REG_SET_BIT(_a, _r, _f) \
477 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
478#define OS_REG_CLR_BIT(_a, _r, _f) \
479 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
480
481/* Analog register writes may require a delay between each one (eg Merlin?) */
482#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
483 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
484
485/* system-configurable parameters */
486extern int ath_hal_dma_beacon_response_time; /* in TU's */
487extern int ath_hal_sw_beacon_response_time; /* in TU's */
488extern int ath_hal_additional_swba_backoff; /* in TU's */
489extern int ath_hal_ar5416_biasadj; /* 1 or 0 */
490
491/* wait for the register contents to have the specified value */
492extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
493 uint32_t mask, uint32_t val);
494extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,
495 uint32_t mask, uint32_t val, uint32_t timeout);
496
497/* return the first n bits in val reversed */
498extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
499
500/* printf interfaces */
501extern void ath_hal_printf(struct ath_hal *, const char*, ...)
502 __printflike(2,3);
503extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
504 __printflike(2, 0);
505extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
506
507/* allocate and free memory */
508extern void *ath_hal_malloc(size_t);
509extern void ath_hal_free(void *);
510
511/* common debugging interfaces */
512#ifdef AH_DEBUG
513#include "ah_debug.h"
514extern int ath_hal_debug;
515#define HALDEBUG(_ah, __m, ...) \
516 do { \
517 if (ath_hal_debug & (__m)) { \
518 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \
519 } \
520 } while(0);
521
522extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
523 __printflike(3,4);
524#else
525#define HALDEBUG(_ah, __m, _fmt, ...)
526#endif /* AH_DEBUG */
527
528/*
529 * Register logging definitions shared with ardecode.
530 */
531#include "ah_decode.h"
532
533/*
534 * Common assertion interface. Note: it is a bad idea to generate
535 * an assertion failure for any recoverable event. Instead catch
536 * the violation and, if possible, fix it up or recover from it; either
537 * with an error return value or a diagnostic messages. System software
538 * does not panic unless the situation is hopeless.
539 */
540#ifdef AH_ASSERT
541extern void ath_hal_assert_failed(const char* filename,
542 int lineno, const char* msg);
543
544#define HALASSERT(_x) do { \
545 if (!(_x)) { \
546 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
547 } \
548} while (0)
549#else
550#define HALASSERT(_x)
551#endif /* AH_ASSERT */
552
553/*
554 * Regulatory domain support.
555 */
556
557/*
558 * Return the max allowed antenna gain and apply any regulatory
559 * domain specific changes.
560 */
561u_int ath_hal_getantennareduction(struct ath_hal *ah,
562 const struct ieee80211_channel *chan, u_int twiceGain);
563
564/*
565 * Return the test group for the specific channel based on
566 * the current regulatory setup.
567 */
568u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
569
570/*
571 * Map a public channel definition to the corresponding
572 * internal data structure. This implicitly specifies
573 * whether or not the specified channel is ok to use
574 * based on the current regulatory domain constraints.
575 */
576#ifndef AH_DEBUG
577static OS_INLINE HAL_CHANNEL_INTERNAL *
578ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
579{
580 HAL_CHANNEL_INTERNAL *cc;
581
582 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
583 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
584 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
585 return cc;
586}
587#else
588/* NB: non-inline version that checks state */
589HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
590 const struct ieee80211_channel *);
591#endif /* AH_DEBUG */
592
593/*
594 * Return the h/w frequency for a channel. This may be
595 * different from ic_freq if this is a GSM device that
596 * takes 2.4GHz frequencies and down-converts them.
597 */
598static OS_INLINE uint16_t
599ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
600{
601 return ath_hal_checkchannel(ah, c)->channel;
602}
603
604/*
605 * Convert between microseconds and core system clocks.
606 */
607extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
608extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
609
610/*
611 * Generic get/set capability support. Each chip overrides
612 * this routine to support chip-specific capabilities.
613 */
614extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
615 HAL_CAPABILITY_TYPE type, uint32_t capability,
616 uint32_t *result);
617extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
618 HAL_CAPABILITY_TYPE type, uint32_t capability,
619 uint32_t setting, HAL_STATUS *status);
620
621/* The diagnostic codes used to be internally defined here -adrian */
622#include "ah_diagcodes.h"
623
624enum {
625 HAL_BB_HANG_DFS = 0x0001,
626 HAL_BB_HANG_RIFS = 0x0002,
627 HAL_BB_HANG_RX_CLEAR = 0x0004,
628 HAL_BB_HANG_UNKNOWN = 0x0080,
629
630 HAL_MAC_HANG_SIG1 = 0x0100,
631 HAL_MAC_HANG_SIG2 = 0x0200,
632 HAL_MAC_HANG_UNKNOWN = 0x8000,
633
634 HAL_BB_HANGS = HAL_BB_HANG_DFS
635 | HAL_BB_HANG_RIFS
636 | HAL_BB_HANG_RX_CLEAR
637 | HAL_BB_HANG_UNKNOWN,
638 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
639 | HAL_MAC_HANG_SIG2
640 | HAL_MAC_HANG_UNKNOWN,
641};
642
643/*
644 * Device revision information.
645 */
646typedef struct {
647 uint16_t ah_devid; /* PCI device ID */
648 uint16_t ah_subvendorid; /* PCI subvendor ID */
649 uint32_t ah_macVersion; /* MAC version id */
650 uint16_t ah_macRev; /* MAC revision */
651 uint16_t ah_phyRev; /* PHY revision */
652 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
653 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
654} HAL_REVS;
655
656/*
657 * Argument payload for HAL_DIAG_SETKEY.
658 */
659typedef struct {
660 HAL_KEYVAL dk_keyval;
661 uint16_t dk_keyix; /* key index */
662 uint8_t dk_mac[IEEE80211_ADDR_LEN];
663 int dk_xor; /* XOR key data */
664} HAL_DIAG_KEYVAL;
665
666/*
667 * Argument payload for HAL_DIAG_EEWRITE.
668 */
669typedef struct {
670 uint16_t ee_off; /* eeprom offset */
671 uint16_t ee_data; /* write data */
672} HAL_DIAG_EEVAL;
673
674
675typedef struct {
676 u_int offset; /* reg offset */
677 uint32_t val; /* reg value */
678} HAL_DIAG_REGVAL;
679
680/*
681 * 11n compatibility tweaks.
682 */
683#define HAL_DIAG_11N_SERVICES 0x00000003
684#define HAL_DIAG_11N_SERVICES_S 0
685#define HAL_DIAG_11N_TXSTOMP 0x0000000c
686#define HAL_DIAG_11N_TXSTOMP_S 2
687
688typedef struct {
689 int maxNoiseImmunityLevel; /* [0..4] */
690 int totalSizeDesired[5];
691 int coarseHigh[5];
692 int coarseLow[5];
693 int firpwr[5];
694
695 int maxSpurImmunityLevel; /* [0..7] */
696 int cycPwrThr1[8];
697
698 int maxFirstepLevel; /* [0..2] */
699 int firstep[3];
700
701 uint32_t ofdmTrigHigh;
702 uint32_t ofdmTrigLow;
703 int32_t cckTrigHigh;
704 int32_t cckTrigLow;
705 int32_t rssiThrLow;
706 int32_t rssiThrHigh;
707
708 int period; /* update listen period */
709} HAL_ANI_PARAMS;
710
711extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
712 const void *args, uint32_t argsize,
713 void **result, uint32_t *resultsize);
714
715/*
716 * Setup a h/w rate table for use.
717 */
718extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
719
720/*
721 * Common routine for implementing getChanNoise api.
722 */
723int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
724
725/*
726 * Initialization support.
727 */
728typedef struct {
729 const uint32_t *data;
730 int rows, cols;
731} HAL_INI_ARRAY;
732
733#define HAL_INI_INIT(_ia, _data, _cols) do { \
734 (_ia)->data = (const uint32_t *)(_data); \
735 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
736 (_ia)->cols = (_cols); \
737} while (0)
738#define HAL_INI_VAL(_ia, _r, _c) \
739 ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
740
741/*
742 * OS_DELAY() does a PIO READ on the PCI bus which allows
743 * other cards' DMA reads to complete in the middle of our reset.
744 */
745#define DMA_YIELD(x) do { \
746 if ((++(x) % 64) == 0) \
747 OS_DELAY(1); \
748} while (0)
749
750#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
751 int r; \
752 for (r = 0; r < N(regArray); r++) { \
753 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
754 DMA_YIELD(regWr); \
755 } \
756} while (0)
757
758#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
759 int r; \
760 for (r = 0; r < N(regArray); r++) { \
761 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
762 DMA_YIELD(regWr); \
763 } \
764} while (0)
765
766extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
767 int col, int regWr);
768extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
769 int col);
770extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
771 const uint32_t data[], int regWr);
772
773#define CCK_SIFS_TIME 10
774#define CCK_PREAMBLE_BITS 144
775#define CCK_PLCP_BITS 48
776
777#define OFDM_SIFS_TIME 16
778#define OFDM_PREAMBLE_TIME 20
779#define OFDM_PLCP_BITS 22
780#define OFDM_SYMBOL_TIME 4
781
782#define OFDM_HALF_SIFS_TIME 32
783#define OFDM_HALF_PREAMBLE_TIME 40
784#define OFDM_HALF_PLCP_BITS 22
785#define OFDM_HALF_SYMBOL_TIME 8
786
787#define OFDM_QUARTER_SIFS_TIME 64
788#define OFDM_QUARTER_PREAMBLE_TIME 80
789#define OFDM_QUARTER_PLCP_BITS 22
790#define OFDM_QUARTER_SYMBOL_TIME 16
791
792#define TURBO_SIFS_TIME 8
793#define TURBO_PREAMBLE_TIME 14
794#define TURBO_PLCP_BITS 22
795#define TURBO_SYMBOL_TIME 4
796
797#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
798
799/* Generic EEPROM board value functions */
800extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList,
801 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
802extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
803 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts,
804 uint8_t *pRetVpdList);
805extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
806 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
807
808/* Whether 5ghz fast clock is needed for Merlin and later */
809#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
810 (IEEE80211_IS_CHAN_5GHZ(_c) && \
811 ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G))
812
813
814#endif /* _ATH_AH_INTERAL_H_ */
| 302 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
303 u_int ah_nchan; /* valid items in ah_channels */
304 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */
305 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */
306
307 uint8_t ah_coverageClass; /* coverage class */
308 /*
309 * RF Silent handling; setup according to the EEPROM.
310 */
311 uint16_t ah_rfsilent; /* GPIO pin + polarity */
312 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
313 /*
314 * Diagnostic support for discriminating HIUERR reports.
315 */
316 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
317 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
318};
319
320#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
321
322#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
323 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
324#define ath_hal_getWirelessModes(_ah) \
325 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
326#define ath_hal_eepromRead(_ah, _off, _data) \
327 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
328#define ath_hal_eepromWrite(_ah, _off, _data) \
329 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
330#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
331 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
332#define ath_hal_gpioCfgInput(_ah, _gpio) \
333 (_ah)->ah_gpioCfgInput(_ah, _gpio)
334#define ath_hal_gpioGet(_ah, _gpio) \
335 (_ah)->ah_gpioGet(_ah, _gpio)
336#define ath_hal_gpioSet(_ah, _gpio, _val) \
337 (_ah)->ah_gpioSet(_ah, _gpio, _val)
338#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
339 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
340#define ath_hal_getpowerlimits(_ah, _chan) \
341 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
342#define ath_hal_getNfAdjust(_ah, _c) \
343 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
344#define ath_hal_getNoiseFloor(_ah, _nfArray) \
345 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
346#define ath_hal_configPCIE(_ah, _reset) \
347 (_ah)->ah_configPCIE(_ah, _reset)
348#define ath_hal_disablePCIE(_ah) \
349 (_ah)->ah_disablePCIE(_ah)
350#define ath_hal_setInterrupts(_ah, _mask) \
351 (_ah)->ah_setInterrupts(_ah, _mask)
352
353#define ath_hal_eepromDetach(_ah) do { \
354 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
355 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
356} while (0)
357#define ath_hal_eepromGet(_ah, _param, _val) \
358 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
359#define ath_hal_eepromSet(_ah, _param, _val) \
360 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
361#define ath_hal_eepromGetFlag(_ah, _param) \
362 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
363#define ath_hal_getSpurChan(_ah, _ix, _is2G) \
364 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
365#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
366 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
367
368#ifndef _NET_IF_IEEE80211_H_
369/*
370 * Stuff that would naturally come from _ieee80211.h
371 */
372#define IEEE80211_ADDR_LEN 6
373
374#define IEEE80211_WEP_IVLEN 3 /* 24bit */
375#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
376#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
377
378#define IEEE80211_CRC_LEN 4
379
380#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
381 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
382#endif /* _NET_IF_IEEE80211_H_ */
383
384#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
385
386#define INIT_AIFS 2
387#define INIT_CWMIN 15
388#define INIT_CWMIN_11B 31
389#define INIT_CWMAX 1023
390#define INIT_SH_RETRY 10
391#define INIT_LG_RETRY 10
392#define INIT_SSH_RETRY 32
393#define INIT_SLG_RETRY 32
394
395typedef struct {
396 uint32_t tqi_ver; /* HAL TXQ verson */
397 HAL_TX_QUEUE tqi_type; /* hw queue type*/
398 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
399 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
400 uint32_t tqi_priority;
401 uint32_t tqi_aifs; /* aifs */
402 uint32_t tqi_cwmin; /* cwMin */
403 uint32_t tqi_cwmax; /* cwMax */
404 uint16_t tqi_shretry; /* frame short retry limit */
405 uint16_t tqi_lgretry; /* frame long retry limit */
406 uint32_t tqi_cbrPeriod;
407 uint32_t tqi_cbrOverflowLimit;
408 uint32_t tqi_burstTime;
409 uint32_t tqi_readyTime;
410 uint32_t tqi_physCompBuf;
411 uint32_t tqi_intFlags; /* flags for internal use */
412} HAL_TX_QUEUE_INFO;
413
414extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
415 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
416extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
417 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
418
419typedef enum {
420 HAL_ANI_PRESENT = 0x1, /* is ANI support present */
421 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2, /* set level */
422 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, /* enable/disable */
423 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8, /* enable/disable */
424 HAL_ANI_FIRSTEP_LEVEL = 0x10, /* set level */
425 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20, /* set level */
426 HAL_ANI_MODE = 0x40, /* 0 => manual, 1 => auto (XXX do not change) */
427 HAL_ANI_PHYERR_RESET =0x80, /* reset phy error stats */
428 HAL_ANI_ALL = 0xff
429} HAL_ANI_CMD;
430
431#define HAL_SPUR_VAL_MASK 0x3FFF
432#define HAL_SPUR_CHAN_WIDTH 87
433#define HAL_BIN_WIDTH_BASE_100HZ 3125
434#define HAL_BIN_WIDTH_TURBO_100HZ 6250
435#define HAL_MAX_BINS_ALLOWED 28
436
437#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900)
438#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
439
440#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
441
442/*
443 * Deduce if the host cpu has big- or litt-endian byte order.
444 */
445static __inline__ int
446isBigEndian(void)
447{
448 union {
449 int32_t i;
450 char c[4];
451 } u;
452 u.i = 1;
453 return (u.c[0] == 0);
454}
455
456/* unalligned little endian access */
457#define LE_READ_2(p) \
458 ((uint16_t) \
459 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
460#define LE_READ_4(p) \
461 ((uint32_t) \
462 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
463 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
464
465/*
466 * Register manipulation macros that expect bit field defines
467 * to follow the convention that an _S suffix is appended for
468 * a shift count, while the field mask has no suffix.
469 */
470#define SM(_v, _f) (((_v) << _f##_S) & (_f))
471#define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
472#define OS_REG_RMW(_a, _r, _set, _clr) \
473 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
474#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
475 OS_REG_WRITE(_a, _r, \
476 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
477#define OS_REG_SET_BIT(_a, _r, _f) \
478 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
479#define OS_REG_CLR_BIT(_a, _r, _f) \
480 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
481
482/* Analog register writes may require a delay between each one (eg Merlin?) */
483#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
484 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
485
486/* system-configurable parameters */
487extern int ath_hal_dma_beacon_response_time; /* in TU's */
488extern int ath_hal_sw_beacon_response_time; /* in TU's */
489extern int ath_hal_additional_swba_backoff; /* in TU's */
490extern int ath_hal_ar5416_biasadj; /* 1 or 0 */
491
492/* wait for the register contents to have the specified value */
493extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
494 uint32_t mask, uint32_t val);
495extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,
496 uint32_t mask, uint32_t val, uint32_t timeout);
497
498/* return the first n bits in val reversed */
499extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
500
501/* printf interfaces */
502extern void ath_hal_printf(struct ath_hal *, const char*, ...)
503 __printflike(2,3);
504extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
505 __printflike(2, 0);
506extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
507
508/* allocate and free memory */
509extern void *ath_hal_malloc(size_t);
510extern void ath_hal_free(void *);
511
512/* common debugging interfaces */
513#ifdef AH_DEBUG
514#include "ah_debug.h"
515extern int ath_hal_debug;
516#define HALDEBUG(_ah, __m, ...) \
517 do { \
518 if (ath_hal_debug & (__m)) { \
519 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \
520 } \
521 } while(0);
522
523extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
524 __printflike(3,4);
525#else
526#define HALDEBUG(_ah, __m, _fmt, ...)
527#endif /* AH_DEBUG */
528
529/*
530 * Register logging definitions shared with ardecode.
531 */
532#include "ah_decode.h"
533
534/*
535 * Common assertion interface. Note: it is a bad idea to generate
536 * an assertion failure for any recoverable event. Instead catch
537 * the violation and, if possible, fix it up or recover from it; either
538 * with an error return value or a diagnostic messages. System software
539 * does not panic unless the situation is hopeless.
540 */
541#ifdef AH_ASSERT
542extern void ath_hal_assert_failed(const char* filename,
543 int lineno, const char* msg);
544
545#define HALASSERT(_x) do { \
546 if (!(_x)) { \
547 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
548 } \
549} while (0)
550#else
551#define HALASSERT(_x)
552#endif /* AH_ASSERT */
553
554/*
555 * Regulatory domain support.
556 */
557
558/*
559 * Return the max allowed antenna gain and apply any regulatory
560 * domain specific changes.
561 */
562u_int ath_hal_getantennareduction(struct ath_hal *ah,
563 const struct ieee80211_channel *chan, u_int twiceGain);
564
565/*
566 * Return the test group for the specific channel based on
567 * the current regulatory setup.
568 */
569u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
570
571/*
572 * Map a public channel definition to the corresponding
573 * internal data structure. This implicitly specifies
574 * whether or not the specified channel is ok to use
575 * based on the current regulatory domain constraints.
576 */
577#ifndef AH_DEBUG
578static OS_INLINE HAL_CHANNEL_INTERNAL *
579ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
580{
581 HAL_CHANNEL_INTERNAL *cc;
582
583 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
584 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
585 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
586 return cc;
587}
588#else
589/* NB: non-inline version that checks state */
590HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
591 const struct ieee80211_channel *);
592#endif /* AH_DEBUG */
593
594/*
595 * Return the h/w frequency for a channel. This may be
596 * different from ic_freq if this is a GSM device that
597 * takes 2.4GHz frequencies and down-converts them.
598 */
599static OS_INLINE uint16_t
600ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
601{
602 return ath_hal_checkchannel(ah, c)->channel;
603}
604
605/*
606 * Convert between microseconds and core system clocks.
607 */
608extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
609extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
610
611/*
612 * Generic get/set capability support. Each chip overrides
613 * this routine to support chip-specific capabilities.
614 */
615extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
616 HAL_CAPABILITY_TYPE type, uint32_t capability,
617 uint32_t *result);
618extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
619 HAL_CAPABILITY_TYPE type, uint32_t capability,
620 uint32_t setting, HAL_STATUS *status);
621
622/* The diagnostic codes used to be internally defined here -adrian */
623#include "ah_diagcodes.h"
624
625enum {
626 HAL_BB_HANG_DFS = 0x0001,
627 HAL_BB_HANG_RIFS = 0x0002,
628 HAL_BB_HANG_RX_CLEAR = 0x0004,
629 HAL_BB_HANG_UNKNOWN = 0x0080,
630
631 HAL_MAC_HANG_SIG1 = 0x0100,
632 HAL_MAC_HANG_SIG2 = 0x0200,
633 HAL_MAC_HANG_UNKNOWN = 0x8000,
634
635 HAL_BB_HANGS = HAL_BB_HANG_DFS
636 | HAL_BB_HANG_RIFS
637 | HAL_BB_HANG_RX_CLEAR
638 | HAL_BB_HANG_UNKNOWN,
639 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
640 | HAL_MAC_HANG_SIG2
641 | HAL_MAC_HANG_UNKNOWN,
642};
643
644/*
645 * Device revision information.
646 */
647typedef struct {
648 uint16_t ah_devid; /* PCI device ID */
649 uint16_t ah_subvendorid; /* PCI subvendor ID */
650 uint32_t ah_macVersion; /* MAC version id */
651 uint16_t ah_macRev; /* MAC revision */
652 uint16_t ah_phyRev; /* PHY revision */
653 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
654 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
655} HAL_REVS;
656
657/*
658 * Argument payload for HAL_DIAG_SETKEY.
659 */
660typedef struct {
661 HAL_KEYVAL dk_keyval;
662 uint16_t dk_keyix; /* key index */
663 uint8_t dk_mac[IEEE80211_ADDR_LEN];
664 int dk_xor; /* XOR key data */
665} HAL_DIAG_KEYVAL;
666
667/*
668 * Argument payload for HAL_DIAG_EEWRITE.
669 */
670typedef struct {
671 uint16_t ee_off; /* eeprom offset */
672 uint16_t ee_data; /* write data */
673} HAL_DIAG_EEVAL;
674
675
676typedef struct {
677 u_int offset; /* reg offset */
678 uint32_t val; /* reg value */
679} HAL_DIAG_REGVAL;
680
681/*
682 * 11n compatibility tweaks.
683 */
684#define HAL_DIAG_11N_SERVICES 0x00000003
685#define HAL_DIAG_11N_SERVICES_S 0
686#define HAL_DIAG_11N_TXSTOMP 0x0000000c
687#define HAL_DIAG_11N_TXSTOMP_S 2
688
689typedef struct {
690 int maxNoiseImmunityLevel; /* [0..4] */
691 int totalSizeDesired[5];
692 int coarseHigh[5];
693 int coarseLow[5];
694 int firpwr[5];
695
696 int maxSpurImmunityLevel; /* [0..7] */
697 int cycPwrThr1[8];
698
699 int maxFirstepLevel; /* [0..2] */
700 int firstep[3];
701
702 uint32_t ofdmTrigHigh;
703 uint32_t ofdmTrigLow;
704 int32_t cckTrigHigh;
705 int32_t cckTrigLow;
706 int32_t rssiThrLow;
707 int32_t rssiThrHigh;
708
709 int period; /* update listen period */
710} HAL_ANI_PARAMS;
711
712extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
713 const void *args, uint32_t argsize,
714 void **result, uint32_t *resultsize);
715
716/*
717 * Setup a h/w rate table for use.
718 */
719extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
720
721/*
722 * Common routine for implementing getChanNoise api.
723 */
724int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
725
726/*
727 * Initialization support.
728 */
729typedef struct {
730 const uint32_t *data;
731 int rows, cols;
732} HAL_INI_ARRAY;
733
734#define HAL_INI_INIT(_ia, _data, _cols) do { \
735 (_ia)->data = (const uint32_t *)(_data); \
736 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
737 (_ia)->cols = (_cols); \
738} while (0)
739#define HAL_INI_VAL(_ia, _r, _c) \
740 ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
741
742/*
743 * OS_DELAY() does a PIO READ on the PCI bus which allows
744 * other cards' DMA reads to complete in the middle of our reset.
745 */
746#define DMA_YIELD(x) do { \
747 if ((++(x) % 64) == 0) \
748 OS_DELAY(1); \
749} while (0)
750
751#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
752 int r; \
753 for (r = 0; r < N(regArray); r++) { \
754 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
755 DMA_YIELD(regWr); \
756 } \
757} while (0)
758
759#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
760 int r; \
761 for (r = 0; r < N(regArray); r++) { \
762 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
763 DMA_YIELD(regWr); \
764 } \
765} while (0)
766
767extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
768 int col, int regWr);
769extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
770 int col);
771extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
772 const uint32_t data[], int regWr);
773
774#define CCK_SIFS_TIME 10
775#define CCK_PREAMBLE_BITS 144
776#define CCK_PLCP_BITS 48
777
778#define OFDM_SIFS_TIME 16
779#define OFDM_PREAMBLE_TIME 20
780#define OFDM_PLCP_BITS 22
781#define OFDM_SYMBOL_TIME 4
782
783#define OFDM_HALF_SIFS_TIME 32
784#define OFDM_HALF_PREAMBLE_TIME 40
785#define OFDM_HALF_PLCP_BITS 22
786#define OFDM_HALF_SYMBOL_TIME 8
787
788#define OFDM_QUARTER_SIFS_TIME 64
789#define OFDM_QUARTER_PREAMBLE_TIME 80
790#define OFDM_QUARTER_PLCP_BITS 22
791#define OFDM_QUARTER_SYMBOL_TIME 16
792
793#define TURBO_SIFS_TIME 8
794#define TURBO_PREAMBLE_TIME 14
795#define TURBO_PLCP_BITS 22
796#define TURBO_SYMBOL_TIME 4
797
798#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
799
800/* Generic EEPROM board value functions */
801extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList,
802 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
803extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
804 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts,
805 uint8_t *pRetVpdList);
806extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
807 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
808
809/* Whether 5ghz fast clock is needed for Merlin and later */
810#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
811 (IEEE80211_IS_CHAN_5GHZ(_c) && \
812 ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G))
813
814
815#endif /* _ATH_AH_INTERAL_H_ */
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