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1/*
2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
3 *
4 * Copyright (c) 1994-2001 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 14 unchanged lines hidden (view full) ---

23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
1/*
2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
3 *
4 * Copyright (c) 1994-2001 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 14 unchanged lines hidden (view full) ---

23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/src/aic7xxx/aic7xxx.seq#27 $
32 *
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 76634 2001-05-15 19:41:12Z gibbs $
31 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 79874 2001-07-18 21:39:48Z gibbs $
34 */
35
32 */
33
34VERSION = "$Id: //depot/src/aic7xxx/aic7xxx.seq#32 $"
35
36#include "aic7xxx.reg"
37#include "scsi_message.h"
38
39/*
40 * A few words on the waiting SCB list:
41 * After starting the selection hardware, we check for reconnecting targets
42 * as well as for our selection to complete just in case the reselection wins
43 * bus arbitration. The problem with this is that we must keep track of the

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170 test SSTAT0, TARGET jz initiator_reselect;
171 }
172 mvi CLRSINT0, CLRSELDI;
173
174 /*
175 * We've just been selected. Assert BSY and
176 * setup the phase for receiving messages
177 * from the target.
36#include "aic7xxx.reg"
37#include "scsi_message.h"
38
39/*
40 * A few words on the waiting SCB list:
41 * After starting the selection hardware, we check for reconnecting targets
42 * as well as for our selection to complete just in case the reselection wins
43 * bus arbitration. The problem with this is that we must keep track of the

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170 test SSTAT0, TARGET jz initiator_reselect;
171 }
172 mvi CLRSINT0, CLRSELDI;
173
174 /*
175 * We've just been selected. Assert BSY and
176 * setup the phase for receiving messages
177 * from the target.
178 *
179 * If bus reset interrupts have been disabled (from a
180 * previous reset), re-enable them now. Resets are only
181 * of interest when we have outstanding transactions, so
182 * we can safely defer re-enabling the interrupt until,
183 * as a target, we start receiving transactions again.
184 */
178 */
185 test SIMODE1, ENSCSIRST jnz . + 3;
186 mvi CLRSINT1, CLRSCSIRSTI;
187 or SIMODE1, ENSCSIRST;
188 mvi SCSISIGO, P_MESGOUT|BSYO;
189
190 /*
191 * Setup the DMA for sending the identify and
192 * command information.
193 */
194 or SEQ_FLAGS, CMDPHASE_PENDING;
195

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744 mvi CCSGCTL, CCSGEN|CCSGRESET ret;
745idle_sgfetch_complete:
746 call disable_ccsgen_fetch_done;
747 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
748idle_sg_avail:
749 if ((ahc->features & AHC_ULTRA2) != 0) {
750 /* Does the hardware have space for another SG entry? */
751 test DFSTATUS, PRELOAD_AVAIL jz return;
179 mvi SCSISIGO, P_MESGOUT|BSYO;
180
181 /*
182 * Setup the DMA for sending the identify and
183 * command information.
184 */
185 or SEQ_FLAGS, CMDPHASE_PENDING;
186

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735 mvi CCSGCTL, CCSGEN|CCSGRESET ret;
736idle_sgfetch_complete:
737 call disable_ccsgen_fetch_done;
738 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
739idle_sg_avail:
740 if ((ahc->features & AHC_ULTRA2) != 0) {
741 /* Does the hardware have space for another SG entry? */
742 test DFSTATUS, PRELOAD_AVAIL jz return;
752 bmov HADDR, CCSGRAM, 4;
753 bmov SINDEX, CCSGRAM, 1;
754 test SINDEX, 0x1 jz . + 2;
743 bmov HADDR, CCSGRAM, 7;
744 test HCNT[0], 0x1 jz . + 2;
755 xor DATA_COUNT_ODD, 0x1;
745 xor DATA_COUNT_ODD, 0x1;
756 bmov HCNT[0], SINDEX, 1;
757 bmov HCNT[1], CCSGRAM, 2;
758 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
746 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
747 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
748 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
749 }
759 call sg_advance;
760 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
761 test DATA_COUNT_ODD, 0x1 jz . + 2;
762 or SINDEX, ODD_SEG;
763 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
764 or SINDEX, LAST_SEG;
765 mov SG_CACHE_PRE, SINDEX;
766 /* Load the segment */

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798 mov MWI_RESIDUAL, A;
799 not A;
800 inc A;
801 add HCNT[0], A;
802 adc HCNT[1], -1;
803 adc HCNT[2], -1 ret;
804}
805
750 call sg_advance;
751 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
752 test DATA_COUNT_ODD, 0x1 jz . + 2;
753 or SINDEX, ODD_SEG;
754 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
755 or SINDEX, LAST_SEG;
756 mov SG_CACHE_PRE, SINDEX;
757 /* Load the segment */

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789 mov MWI_RESIDUAL, A;
790 not A;
791 inc A;
792 add HCNT[0], A;
793 adc HCNT[1], -1;
794 adc HCNT[2], -1 ret;
795}
796
806/*
807 * If we re-enter the data phase after going through another phase, the
808 * STCNT may have been cleared, so restore it from the residual field.
809 */
810data_phase_reinit:
811 if ((ahc->features & AHC_ULTRA2) != 0) {
812 /*
813 * The preload circuitry requires us to
814 * reload the address too, so pull it from
815 * the shaddow address.
816 */
817 bmov HADDR, SHADDR, 4;
818 bmov HCNT, SCB_RESIDUAL_DATACNT, 3;
819 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
820 bmov STCNT, SCB_RESIDUAL_DATACNT, 3;
821 } else {
822 mvi DINDEX, STCNT;
823 mvi SCB_RESIDUAL_DATACNT call bcopy_3;
824 }
825 and DATA_COUNT_ODD, 0x1, SCB_RESIDUAL_DATACNT[0];
826 jmp data_phase_loop;
827
828p_data:
797p_data:
798 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_data_okay;
799 mvi NO_IDENT jmp set_seqint;
800p_data_okay:
829 if ((ahc->features & AHC_ULTRA2) != 0) {
830 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
831 } else {
832 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
833 }
834 test LASTPHASE, IOI jnz . + 2;
835 or DMAPARAMS, DIRECTION;
801 if ((ahc->features & AHC_ULTRA2) != 0) {
802 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
803 } else {
804 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
805 }
806 test LASTPHASE, IOI jnz . + 2;
807 or DMAPARAMS, DIRECTION;
836 call assert; /*
837 * Ensure entering a data
838 * phase is okay - seen identify, etc.
839 */
840 if ((ahc->features & AHC_CMD_CHAN) != 0) {
841 /* We don't have any valid S/G elements */
842 mvi CCSGADDR, SG_PREFETCH_CNT;
843 }
808 if ((ahc->features & AHC_CMD_CHAN) != 0) {
809 /* We don't have any valid S/G elements */
810 mvi CCSGADDR, SG_PREFETCH_CNT;
811 }
844 test SEQ_FLAGS, DPHASE jnz data_phase_reinit;
812 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
845
813
846 /* We have seen a data phase */
814 /*
815 * If we re-enter the data phase after going through another
816 * phase, our transfer location has almost certainly been
817 * corrupted by the interveining, non-data, transfers. Ask
818 * the host driver to fix us up based on the transfer residual.
819 */
820 mvi PDATA_REINIT call set_seqint;
821 jmp data_phase_loop;
822
823data_phase_initialize:
824 /* We have seen a data phase for the first time */
847 or SEQ_FLAGS, DPHASE;
848
849 /*
850 * Initialize the DMA address and counter from the SCB.
851 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
852 * flag in the highest byte of the data count. We cannot
853 * modify the saved values in the SCB until we see a save
854 * data pointers message.
855 */
825 or SEQ_FLAGS, DPHASE;
826
827 /*
828 * Initialize the DMA address and counter from the SCB.
829 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
830 * flag in the highest byte of the data count. We cannot
831 * modify the saved values in the SCB until we see a save
832 * data pointers message.
833 */
834 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
835 /* The lowest address byte must be loaded last. */
836 mov SCB_DATACNT[3] call set_hhaddr;
837 }
856 if ((ahc->features & AHC_CMD_CHAN) != 0) {
857 bmov HADDR, SCB_DATAPTR, 7;
858 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
859 } else {
860 mvi DINDEX, HADDR;
861 mvi SCB_DATAPTR call bcopy_7;
862 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
863 mvi SCB_DATACNT + 3 call bcopy_5;

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1052 test DFSTATUS, FIFOEMP jz .;
1053 }
1054ultra2_fifoempty:
1055 /* Don't clobber an inprogress host data transfer */
1056 test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
1057ultra2_dmahalt:
1058 and DFCNTRL, ~(SCSIEN|HDMAEN);
1059 test DFCNTRL, SCSIEN|HDMAEN jnz .;
838 if ((ahc->features & AHC_CMD_CHAN) != 0) {
839 bmov HADDR, SCB_DATAPTR, 7;
840 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
841 } else {
842 mvi DINDEX, HADDR;
843 mvi SCB_DATAPTR call bcopy_7;
844 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
845 mvi SCB_DATACNT + 3 call bcopy_5;

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1034 test DFSTATUS, FIFOEMP jz .;
1035 }
1036ultra2_fifoempty:
1037 /* Don't clobber an inprogress host data transfer */
1038 test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
1039ultra2_dmahalt:
1040 and DFCNTRL, ~(SCSIEN|HDMAEN);
1041 test DFCNTRL, SCSIEN|HDMAEN jnz .;
1042 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1043 /*
1044 * Keep HHADDR cleared for future, 32bit addressed
1045 * only, DMA operations.
1046 *
1047 * Due to bayonette style S/G handling, our residual
1048 * data must be "fixed up" once the transfer is halted.
1049 * Here we fixup the HSHADDR stored in the high byte
1050 * of the residual data cnt. By postponing the fixup,
1051 * we can batch the clearing of HADDR with the fixup.
1052 * If we halted on the last segment, the residual is
1053 * already correct. If we are not on the last
1054 * segment, copy the high address directly from HSHADDR.
1055 * We don't need to worry about maintaining the
1056 * SG_LAST_SEG flag as it will always be false in the
1057 * case where an update is required.
1058 */
1059 or DSCOMMAND1, HADDLDSEL0;
1060 test SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
1061 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1062 clr HADDR;
1063 and DSCOMMAND1, ~HADDLDSEL0;
1064 }
1060 } else {
1061 /* If we are the last SG block, tell the hardware. */
1062 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1063 && ahc->pci_cachesize != 0) {
1064 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
1065 }
1066 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
1067 if ((ahc->flags & AHC_TARGETROLE) != 0) {

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1158 * segment from host memory first.
1159 */
1160 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1161 /* Wait for the idle loop to complete */
1162 test CCSGCTL, CCSGEN jz . + 3;
1163 call idle_loop;
1164 test CCSGCTL, CCSGEN jnz . - 1;
1165 bmov HADDR, CCSGRAM, 7;
1065 } else {
1066 /* If we are the last SG block, tell the hardware. */
1067 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1068 && ahc->pci_cachesize != 0) {
1069 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
1070 }
1071 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
1072 if ((ahc->flags & AHC_TARGETROLE) != 0) {

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1163 * segment from host memory first.
1164 */
1165 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1166 /* Wait for the idle loop to complete */
1167 test CCSGCTL, CCSGEN jz . + 3;
1168 call idle_loop;
1169 test CCSGCTL, CCSGEN jnz . - 1;
1170 bmov HADDR, CCSGRAM, 7;
1166 test CCSGRAM, SG_LAST_SEG jz . + 2;
1167 or SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG;
1171 /*
1172 * Workaround for flaky external SCB RAM
1173 * on certain aic7895 setups. It seems
1174 * unable to handle direct transfers from
1175 * S/G ram to certain SCB locations.
1176 */
1177 mov SINDEX, CCSGRAM;
1178 mov SCB_RESIDUAL_DATACNT[3], SINDEX;
1168 } else {
1179 } else {
1180 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1181 mov ALLZEROS call set_hhaddr;
1182 }
1169 mvi DINDEX, HADDR;
1170 mvi SCB_RESIDUAL_SGPTR call bcopy_4;
1171
1172 mvi SG_SIZEOF call set_hcnt;
1173
1174 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1175
1176 call dma_finish;
1177
1178 mvi DINDEX, HADDR;
1179 call dfdat_in_7;
1180 mov SCB_RESIDUAL_DATACNT[3], DFDAT;
1181 }
1182
1183 mvi DINDEX, HADDR;
1184 mvi SCB_RESIDUAL_SGPTR call bcopy_4;
1185
1186 mvi SG_SIZEOF call set_hcnt;
1187
1188 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1189
1190 call dma_finish;
1191
1192 mvi DINDEX, HADDR;
1193 call dfdat_in_7;
1194 mov SCB_RESIDUAL_DATACNT[3], DFDAT;
1195 }
1196
1197 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1198 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
1199
1200 /*
1201 * The lowest address byte must be loaded
1202 * last as it triggers the computation of
1203 * some items in the PCI block. The ULTRA2
1204 * chips do this on PRELOAD.
1205 */
1206 mov HADDR, HADDR;
1207 }
1183 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1184 && ahc->pci_cachesize != 0) {
1185 call calc_mwi_residual;
1186 }
1187
1188 /* Point to the new next sg in memory */
1189 call sg_advance;
1190

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1229 * of how many bytes were transferred on the SCSI (as opposed to the
1230 * host) bus.
1231 */
1232 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1233 /* Kill off any pending prefetch */
1234 call disable_ccsgen;
1235 }
1236
1208 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1209 && ahc->pci_cachesize != 0) {
1210 call calc_mwi_residual;
1211 }
1212
1213 /* Point to the new next sg in memory */
1214 call sg_advance;
1215

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1254 * of how many bytes were transferred on the SCSI (as opposed to the
1255 * host) bus.
1256 */
1257 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1258 /* Kill off any pending prefetch */
1259 call disable_ccsgen;
1260 }
1261
1262 if ((ahc->features & AHC_ULTRA2) == 0) {
1263 /*
1264 * Clear the high address byte so that all other DMA
1265 * operations, which use 32bit addressing, can assume
1266 * HHADDR is 0.
1267 */
1268 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1269 mov ALLZEROS call set_hhaddr;
1270 }
1271 }
1272
1273 /*
1274 * Update our residual information before the information is
1275 * lost by some other type of SCSI I/O (e.g. PIO). If we have
1276 * transferred all data, no update is needed.
1277 *
1278 */
1279 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
1237 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1238 && ahc->pci_cachesize != 0) {
1239 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1240 test MWI_RESIDUAL, 0xFF jz bmov_resid;
1241 }
1242 mov A, MWI_RESIDUAL;
1243 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
1244 clr A;

--- 7 unchanged lines hidden (view full) ---

1252 }
1253 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1254 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1255 } else {
1256 mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
1257 mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
1258 mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
1259 }
1280 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1281 && ahc->pci_cachesize != 0) {
1282 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1283 test MWI_RESIDUAL, 0xFF jz bmov_resid;
1284 }
1285 mov A, MWI_RESIDUAL;
1286 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
1287 clr A;

--- 7 unchanged lines hidden (view full) ---

1295 }
1296 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1297 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1298 } else {
1299 mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
1300 mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
1301 mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
1302 }
1260
1303residual_update_done:
1261 /*
1262 * Since we've been through a data phase, the SCB_RESID* fields
1263 * are now initialized. Clear the full residual flag.
1264 */
1265 and SCB_SGPTR[0], ~SG_FULL_RESID;
1266
1267 if ((ahc->features & AHC_ULTRA2) != 0) {
1268 /* Clear the channel in case we return to data phase later */

--- 15 unchanged lines hidden (view full) ---

1284 jmp ITloop;
1285 }
1286
1287if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1288/*
1289 * Command phase. Set up the DMA registers and let 'er rip.
1290 */
1291p_command:
1304 /*
1305 * Since we've been through a data phase, the SCB_RESID* fields
1306 * are now initialized. Clear the full residual flag.
1307 */
1308 and SCB_SGPTR[0], ~SG_FULL_RESID;
1309
1310 if ((ahc->features & AHC_ULTRA2) != 0) {
1311 /* Clear the channel in case we return to data phase later */

--- 15 unchanged lines hidden (view full) ---

1327 jmp ITloop;
1328 }
1329
1330if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1331/*
1332 * Command phase. Set up the DMA registers and let 'er rip.
1333 */
1334p_command:
1292 call assert;
1335 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_command_okay;
1336 mvi NO_IDENT jmp set_seqint;
1337p_command_okay:
1293
1294 if ((ahc->features & AHC_ULTRA2) != 0) {
1295 bmov HCNT[0], SCB_CDB_LEN, 1;
1296 bmov HCNT[1], ALLZEROS, 2;
1297 mvi SG_CACHE_PRE, LAST_SEG;
1298 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1299 bmov STCNT[0], SCB_CDB_LEN, 1;
1300 bmov STCNT[1], ALLZEROS, 2;

--- 77 unchanged lines hidden (view full) ---

1378 }
1379 jmp ITloop;
1380
1381/*
1382 * Status phase. Wait for the data byte to appear, then read it
1383 * and store it into the SCB.
1384 */
1385p_status:
1338
1339 if ((ahc->features & AHC_ULTRA2) != 0) {
1340 bmov HCNT[0], SCB_CDB_LEN, 1;
1341 bmov HCNT[1], ALLZEROS, 2;
1342 mvi SG_CACHE_PRE, LAST_SEG;
1343 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1344 bmov STCNT[0], SCB_CDB_LEN, 1;
1345 bmov STCNT[1], ALLZEROS, 2;

--- 77 unchanged lines hidden (view full) ---

1423 }
1424 jmp ITloop;
1425
1426/*
1427 * Status phase. Wait for the data byte to appear, then read it
1428 * and store it into the SCB.
1429 */
1430p_status:
1386 call assert;
1387
1431 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_status_okay;
1432 mvi NO_IDENT jmp set_seqint;
1433p_status_okay:
1388 mov SCB_SCSI_STATUS, SCSIDATL;
1389 jmp ITloop;
1390
1391/*
1392 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
1393 * indentify message sequence and send it to the target. The host may
1394 * override this behavior by setting the MK_MESSAGE bit in the SCB
1395 * control byte. This will cause us to interrupt the host and allow

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1621 */
1622mesgin_sdptrs:
1623 if ((ahc->features & AHC_ULTRA2) != 0) {
1624 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1625 test SEQ_FLAGS, DPHASE jz ITloop;
1626 } else {
1627 test SEQ_FLAGS, DPHASE jz mesgin_done;
1628 }
1434 mov SCB_SCSI_STATUS, SCSIDATL;
1435 jmp ITloop;
1436
1437/*
1438 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
1439 * indentify message sequence and send it to the target. The host may
1440 * override this behavior by setting the MK_MESSAGE bit in the SCB
1441 * control byte. This will cause us to interrupt the host and allow

--- 225 unchanged lines hidden (view full) ---

1667 */
1668mesgin_sdptrs:
1669 if ((ahc->features & AHC_ULTRA2) != 0) {
1670 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1671 test SEQ_FLAGS, DPHASE jz ITloop;
1672 } else {
1673 test SEQ_FLAGS, DPHASE jz mesgin_done;
1674 }
1675
1629 /*
1676 /*
1677 * If we are asked to save our position at the end of the
1678 * transfer, just mark us at the end rather than perform a
1679 * full save.
1680 */
1681 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full;
1682 or SCB_SGPTR, SG_LIST_NULL;
1683 jmp mesgin_done;
1684
1685mesgin_sdptrs_full:
1686
1687 /*
1630 * The SCB_SGPTR becomes the next one we'll download,
1631 * and the SCB_DATAPTR becomes the current SHADDR.
1632 * Use the residual number since STCNT is corrupted by
1633 * any message transfer.
1634 */
1635 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1636 bmov SCB_DATAPTR, SHADDR, 4;
1637 if ((ahc->features & AHC_ULTRA2) == 0) {

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1902target_outb:
1903 or SXFRCTL0, SPIOEN;
1904 test SSTAT0, SPIORDY jz .;
1905 mov SCSIDATL, SINDEX;
1906 test SSTAT0, SPIORDY jz .;
1907 and SXFRCTL0, ~SPIOEN ret;
1908}
1909
1688 * The SCB_SGPTR becomes the next one we'll download,
1689 * and the SCB_DATAPTR becomes the current SHADDR.
1690 * Use the residual number since STCNT is corrupted by
1691 * any message transfer.
1692 */
1693 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1694 bmov SCB_DATAPTR, SHADDR, 4;
1695 if ((ahc->features & AHC_ULTRA2) == 0) {

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1960target_outb:
1961 or SXFRCTL0, SPIOEN;
1962 test SSTAT0, SPIORDY jz .;
1963 mov SCSIDATL, SINDEX;
1964 test SSTAT0, SPIORDY jz .;
1965 and SXFRCTL0, ~SPIOEN ret;
1966}
1967
1910
1911/*
1968/*
1912 * Assert that if we've been reselected, then we've seen an IDENTIFY
1913 * message.
1914 */
1915assert:
1916 test SEQ_FLAGS,IDENTIFY_SEEN jnz return; /* seen IDENTIFY? */
1917
1918 mvi NO_IDENT jmp set_seqint; /* no - tell the kernel */
1919
1920/*
1921 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will
1922 * be set to the position of the SCB. If the SCB cannot be found locally,
1923 * it will be paged in from host memory. RETURN_2 stores the address of the
1924 * preceding SCB in the disconnected list which can be used to speed up
1925 * removal of the found SCB from the disconnected list.
1926 */
1927if ((ahc->flags & AHC_PAGESCBS) != 0) {
1928BEGIN_CRITICAL

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2245 mov SCB_NEXT, FREE_SCBH;
2246 mvi SCB_TAG, SCB_LIST_NULL;
2247 mov FREE_SCBH, SCBPTR ret;
2248END_CRITICAL
2249 } else {
2250 mvi SCB_TAG, SCB_LIST_NULL ret;
2251 }
2252
1969 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will
1970 * be set to the position of the SCB. If the SCB cannot be found locally,
1971 * it will be paged in from host memory. RETURN_2 stores the address of the
1972 * preceding SCB in the disconnected list which can be used to speed up
1973 * removal of the found SCB from the disconnected list.
1974 */
1975if ((ahc->flags & AHC_PAGESCBS) != 0) {
1976BEGIN_CRITICAL

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2293 mov SCB_NEXT, FREE_SCBH;
2294 mvi SCB_TAG, SCB_LIST_NULL;
2295 mov FREE_SCBH, SCBPTR ret;
2296END_CRITICAL
2297 } else {
2298 mvi SCB_TAG, SCB_LIST_NULL ret;
2299 }
2300
2301if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
2302set_hhaddr:
2303 or DSCOMMAND1, HADDLDSEL0;
2304 and HADDR, SG_HIGH_ADDR_BITS, SINDEX;
2305 and DSCOMMAND1, ~HADDLDSEL0 ret;
2306}
2307
2253if ((ahc->flags & AHC_PAGESCBS) != 0) {
2254get_free_or_disc_scb:
2255BEGIN_CRITICAL
2256 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
2257 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
2258return_error:
2259 mvi NO_FREE_SCB call set_seqint;
2260 mvi SINDEX, SCB_LIST_NULL ret;

--- 28 unchanged lines hidden --- 		2308if ((ahc->flags & AHC_PAGESCBS) != 0) {
2309get_free_or_disc_scb:
2310BEGIN_CRITICAL
2311 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
2312 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
2313return_error:
2314 mvi NO_FREE_SCB call set_seqint;
2315 mvi SINDEX, SCB_LIST_NULL ret;

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