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aic7xxx.c (76634) aic7xxx.c (79874)
1/*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 14 unchanged lines hidden (view full) ---

23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
1/*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 14 unchanged lines hidden (view full) ---

23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/src/aic7xxx/aic7xxx.c#39 $
31 * $Id: //depot/src/aic7xxx/aic7xxx.c#43 $
32 *
32 *
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 76634 2001-05-15 19:41:12Z gibbs $
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 79874 2001-07-18 21:39:48Z gibbs $
34 */
35
36#include <dev/aic7xxx/aic7xxx_freebsd.h>
37#include <dev/aic7xxx/aic7xxx_inline.h>
38#include <dev/aic7xxx/aicasm/aicasm_insformat.h>
39
40/****************************** Softc Data ************************************/
41struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);

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174static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
175 u_int msgval, int full);
176static int ahc_parse_msg(struct ahc_softc *ahc,
177 struct ahc_devinfo *devinfo);
178static int ahc_handle_msg_reject(struct ahc_softc *ahc,
179 struct ahc_devinfo *devinfo);
180static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
181 struct ahc_devinfo *devinfo);
34 */
35
36#include <dev/aic7xxx/aic7xxx_freebsd.h>
37#include <dev/aic7xxx/aic7xxx_inline.h>
38#include <dev/aic7xxx/aicasm/aicasm_insformat.h>
39
40/****************************** Softc Data ************************************/
41struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);

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174static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
175 u_int msgval, int full);
176static int ahc_parse_msg(struct ahc_softc *ahc,
177 struct ahc_devinfo *devinfo);
178static int ahc_handle_msg_reject(struct ahc_softc *ahc,
179 struct ahc_devinfo *devinfo);
180static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
181 struct ahc_devinfo *devinfo);
182static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
182static void ahc_handle_devreset(struct ahc_softc *ahc,
183 struct ahc_devinfo *devinfo,
184 cam_status status, char *message,
185 int verbose_level);
186#if AHC_TARGET_MODE
187static void ahc_setup_target_msgin(struct ahc_softc *ahc,
188 struct ahc_devinfo *devinfo,
189 struct scb *scb);

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277
278/************************* Input/Output Queues ********************************/
279void
280ahc_run_qoutfifo(struct ahc_softc *ahc)
281{
282 struct scb *scb;
283 u_int scb_index;
284
183static void ahc_handle_devreset(struct ahc_softc *ahc,
184 struct ahc_devinfo *devinfo,
185 cam_status status, char *message,
186 int verbose_level);
187#if AHC_TARGET_MODE
188static void ahc_setup_target_msgin(struct ahc_softc *ahc,
189 struct ahc_devinfo *devinfo,
190 struct scb *scb);

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278
279/************************* Input/Output Queues ********************************/
280void
281ahc_run_qoutfifo(struct ahc_softc *ahc)
282{
283 struct scb *scb;
284 u_int scb_index;
285
286 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
285 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
286
287 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
288 if ((ahc->qoutfifonext & 0x03) == 0x03) {
289 u_int modnext;
290
291 /*
292 * Clear 32bits of QOUTFIFO at a time
293 * so that we don't clobber an incoming
294 * byte DMA to the array on architectures
295 * that only support 32bit load and store
296 * operations.
297 */
298 modnext = ahc->qoutfifonext & ~0x3;
299 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
287 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
288
289 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
290 if ((ahc->qoutfifonext & 0x03) == 0x03) {
291 u_int modnext;
292
293 /*
294 * Clear 32bits of QOUTFIFO at a time
295 * so that we don't clobber an incoming
296 * byte DMA to the array on architectures
297 * that only support 32bit load and store
298 * operations.
299 */
300 modnext = ahc->qoutfifonext & ~0x3;
301 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
302 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
303 ahc->shared_data_dmamap,
304 /*offset*/modnext, /*len*/4,
305 BUS_DMASYNC_PREREAD);
300 }
301 ahc->qoutfifonext++;
302
303 scb = ahc_lookup_scb(ahc, scb_index);
304 if (scb == NULL) {
305 printf("%s: WARNING no command for scb %d "
306 "(cmdcmplt)\nQOUTPOS = %d\n",
307 ahc_name(ahc), scb_index,

--- 311 unchanged lines hidden (view full) ---

619 printf("%s: Issued Channel %c Bus Reset. "
620 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel,
621 found);
622 return;
623 }
624 case IGN_WIDE_RES:
625 ahc_handle_ign_wide_residue(ahc, &devinfo);
626 break;
306 }
307 ahc->qoutfifonext++;
308
309 scb = ahc_lookup_scb(ahc, scb_index);
310 if (scb == NULL) {
311 printf("%s: WARNING no command for scb %d "
312 "(cmdcmplt)\nQOUTPOS = %d\n",
313 ahc_name(ahc), scb_index,

--- 311 unchanged lines hidden (view full) ---

625 printf("%s: Issued Channel %c Bus Reset. "
626 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel,
627 found);
628 return;
629 }
630 case IGN_WIDE_RES:
631 ahc_handle_ign_wide_residue(ahc, &devinfo);
632 break;
633 case PDATA_REINIT:
634 ahc_reinitialize_dataptrs(ahc);
635 break;
627 case BAD_PHASE:
628 {
629 u_int lastphase;
630
631 lastphase = ahc_inb(ahc, LASTPHASE);
632 printf("%s:%c:%d: unknown scsi bus phase %x, "
633 "lastphase = 0x%x. Attempting to continue\n",
634 ahc_name(ahc), devinfo.channel, devinfo.target,

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772 ahc_phase_table[i].phasemsg,
773 scb->hscb->tag);
774 ahc_print_path(ahc, scb);
775 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
776 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
777 ahc_get_transfer_length(scb), scb->sg_count);
778 if (scb->sg_count > 0) {
779 for (i = 0; i < scb->sg_count; i++) {
636 case BAD_PHASE:
637 {
638 u_int lastphase;
639
640 lastphase = ahc_inb(ahc, LASTPHASE);
641 printf("%s:%c:%d: unknown scsi bus phase %x, "
642 "lastphase = 0x%x. Attempting to continue\n",
643 ahc_name(ahc), devinfo.channel, devinfo.target,

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781 ahc_phase_table[i].phasemsg,
782 scb->hscb->tag);
783 ahc_print_path(ahc, scb);
784 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
785 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
786 ahc_get_transfer_length(scb), scb->sg_count);
787 if (scb->sg_count > 0) {
788 for (i = 0; i < scb->sg_count; i++) {
780 printf("sg[%d] - Addr 0x%x : Length %d\n",
789
790 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
781 i,
791 i,
792 (ahc_le32toh(scb->sg_list[i].len) >> 24
793 & SG_HIGH_ADDR_BITS),
782 ahc_le32toh(scb->sg_list[i].addr),
783 ahc_le32toh(scb->sg_list[i].len)
784 & AHC_SG_LEN_MASK);
785 }
786 }
787 /*
788 * Set this and it will take effect when the
789 * target does a command complete.
790 */
791 ahc_freeze_devq(ahc, scb);
792 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
793 ahc_freeze_scb(scb);
794 ahc_le32toh(scb->sg_list[i].addr),
795 ahc_le32toh(scb->sg_list[i].len)
796 & AHC_SG_LEN_MASK);
797 }
798 }
799 /*
800 * Set this and it will take effect when the
801 * target does a command complete.
802 */
803 ahc_freeze_devq(ahc, scb);
804 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
805 ahc_freeze_scb(scb);
806
807 if ((ahc->features & AHC_ULTRA2) != 0) {
808 /*
809 * Clear the channel in case we return
810 * to data phase later.
811 */
812 ahc_outb(ahc, SXFRCTL0,
813 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
814 ahc_outb(ahc, SXFRCTL0,
815 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
816 }
817 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
818 u_int dscommand1;
819
820 /* Ensure HHADDR is 0 for future DMA operations. */
821 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
822 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
823 ahc_outb(ahc, HADDR, 0);
824 ahc_outb(ahc, DSCOMMAND1, dscommand1);
825 }
794 break;
795 }
796 case MKMSG_FAILED:
797 {
798 u_int scbindex;
799
800 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
801 ahc_name(ahc), devinfo.channel, devinfo.target,

--- 531 unchanged lines hidden (view full) ---

1333void
1334ahc_print_scb(struct scb *scb)
1335{
1336 int i;
1337
1338 struct hardware_scb *hscb = scb->hscb;
1339
1340 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
826 break;
827 }
828 case MKMSG_FAILED:
829 {
830 u_int scbindex;
831
832 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
833 ahc_name(ahc), devinfo.channel, devinfo.target,

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1365void
1366ahc_print_scb(struct scb *scb)
1367{
1368 int i;
1369
1370 struct hardware_scb *hscb = scb->hscb;
1371
1372 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1341 scb,
1373 (void *)scb,
1342 hscb->control,
1343 hscb->scsiid,
1344 hscb->lun,
1345 hscb->cdb_len);
1346 i = 0;
1347 printf("Shared Data: %#02x %#02x %#02x %#02x\n",
1348 hscb->shared_data.cdb[i++],
1349 hscb->shared_data.cdb[i++],

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1361 hscb->shared_data.cdb[i++]);
1362 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1363 ahc_le32toh(hscb->dataptr),
1364 ahc_le32toh(hscb->datacnt),
1365 ahc_le32toh(hscb->sgptr),
1366 hscb->tag);
1367 if (scb->sg_count > 0) {
1368 for (i = 0; i < scb->sg_count; i++) {
1374 hscb->control,
1375 hscb->scsiid,
1376 hscb->lun,
1377 hscb->cdb_len);
1378 i = 0;
1379 printf("Shared Data: %#02x %#02x %#02x %#02x\n",
1380 hscb->shared_data.cdb[i++],
1381 hscb->shared_data.cdb[i++],

--- 11 unchanged lines hidden (view full) ---

1393 hscb->shared_data.cdb[i++]);
1394 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1395 ahc_le32toh(hscb->dataptr),
1396 ahc_le32toh(hscb->datacnt),
1397 ahc_le32toh(hscb->sgptr),
1398 hscb->tag);
1399 if (scb->sg_count > 0) {
1400 for (i = 0; i < scb->sg_count; i++) {
1369 printf("sg[%d] - Addr 0x%x : Length %d\n",
1401 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1370 i,
1402 i,
1403 (ahc_le32toh(scb->sg_list[i].len) >> 24
1404 & SG_HIGH_ADDR_BITS),
1371 ahc_le32toh(scb->sg_list[i].addr),
1372 ahc_le32toh(scb->sg_list[i].len));
1373 }
1374 }
1375}
1376
1377/************************* Transfer Negotiation *******************************/
1378/*

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1906 * SCBs there have the proper settings.
1907 */
1908 pending_scb_count = 0;
1909 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
1910 struct ahc_devinfo devinfo;
1911 struct hardware_scb *pending_hscb;
1912 struct ahc_initiator_tinfo *tinfo;
1913 struct ahc_tmode_tstate *tstate;
1405 ahc_le32toh(scb->sg_list[i].addr),
1406 ahc_le32toh(scb->sg_list[i].len));
1407 }
1408 }
1409}
1410
1411/************************* Transfer Negotiation *******************************/
1412/*

--- 527 unchanged lines hidden (view full) ---

1940 * SCBs there have the proper settings.
1941 */
1942 pending_scb_count = 0;
1943 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
1944 struct ahc_devinfo devinfo;
1945 struct hardware_scb *pending_hscb;
1946 struct ahc_initiator_tinfo *tinfo;
1947 struct ahc_tmode_tstate *tstate;
1914
1948
1915 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
1916 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
1917 devinfo.our_scsiid,
1918 devinfo.target, &tstate);
1919 pending_hscb = pending_scb->hscb;
1920 pending_hscb->control &= ~ULTRAENB;
1921 if ((tstate->ultraenb & devinfo.target_mask) != 0)
1922 pending_hscb->control |= ULTRAENB;
1923 pending_hscb->scsirate = tinfo->scsirate;
1924 pending_hscb->scsioffset = tinfo->curr.offset;
1925 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
1926 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
1927 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
1928 pending_hscb->control &= ~MK_MESSAGE;
1929 }
1949 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
1950 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
1951 devinfo.our_scsiid,
1952 devinfo.target, &tstate);
1953 pending_hscb = pending_scb->hscb;
1954 pending_hscb->control &= ~ULTRAENB;
1955 if ((tstate->ultraenb & devinfo.target_mask) != 0)
1956 pending_hscb->control |= ULTRAENB;
1957 pending_hscb->scsirate = tinfo->scsirate;
1958 pending_hscb->scsioffset = tinfo->curr.offset;
1959 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
1960 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
1961 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
1962 pending_hscb->control &= ~MK_MESSAGE;
1963 }
1964 ahc_sync_scb(ahc, pending_scb,
1965 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1930 pending_scb_count++;
1931 }
1932
1933 if (pending_scb_count == 0)
1934 return;
1935
1936 if (ahc_is_paused(ahc)) {
1937 paused = 1;

--- 238 unchanged lines hidden (view full) ---

2176 /*
2177 * Filter our period based on the current connection.
2178 * If we can't perform DT transfers on this segment (not in LVD
2179 * mode for instance), then our decision to issue a PPR message
2180 * may change.
2181 */
2182 period = tinfo->goal.period;
2183 ppr_options = tinfo->goal.ppr_options;
1966 pending_scb_count++;
1967 }
1968
1969 if (pending_scb_count == 0)
1970 return;
1971
1972 if (ahc_is_paused(ahc)) {
1973 paused = 1;

--- 238 unchanged lines hidden (view full) ---

2212 /*
2213 * Filter our period based on the current connection.
2214 * If we can't perform DT transfers on this segment (not in LVD
2215 * mode for instance), then our decision to issue a PPR message
2216 * may change.
2217 */
2218 period = tinfo->goal.period;
2219 ppr_options = tinfo->goal.ppr_options;
2220 /* Target initiated PPR is not allowed in the SCSI spec */
2221 if (devinfo->role == ROLE_TARGET)
2222 ppr_options = 0;
2184 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2185 &ppr_options, devinfo->role);
2186 dowide = tinfo->curr.width != tinfo->goal.width;
2187 dosync = tinfo->curr.period != period;
2188 doppr = tinfo->curr.ppr_options != ppr_options;
2189
2190 if (!dowide && !dosync && !doppr) {
2191 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;

--- 1011 unchanged lines hidden (view full) ---

3203 * transfer and the transfer request was
3204 * expected to end on an odd count, do
3205 * nothing.
3206 */
3207 } else {
3208 struct ahc_dma_seg *sg;
3209 uint32_t data_cnt;
3210 uint32_t data_addr;
2223 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2224 &ppr_options, devinfo->role);
2225 dowide = tinfo->curr.width != tinfo->goal.width;
2226 dosync = tinfo->curr.period != period;
2227 doppr = tinfo->curr.ppr_options != ppr_options;
2228
2229 if (!dowide && !dosync && !doppr) {
2230 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;

--- 1011 unchanged lines hidden (view full) ---

3242 * transfer and the transfer request was
3243 * expected to end on an odd count, do
3244 * nothing.
3245 */
3246 } else {
3247 struct ahc_dma_seg *sg;
3248 uint32_t data_cnt;
3249 uint32_t data_addr;
3250 uint32_t sglen;
3211
3212 /* Pull in the rest of the sgptr */
3213 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3214 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3215 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8);
3216 sgptr &= SG_PTR_MASK;
3251
3252 /* Pull in the rest of the sgptr */
3253 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3254 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3255 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8);
3256 sgptr &= SG_PTR_MASK;
3217 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16)
3257 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24)
3258 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16)
3218 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8)
3219 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT));
3220
3221 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24)
3222 | (ahc_inb(ahc, SHADDR + 2) << 16)
3223 | (ahc_inb(ahc, SHADDR + 1) << 8)
3224 | (ahc_inb(ahc, SHADDR));
3225
3226 data_cnt += 1;
3227 data_addr -= 1;
3228
3229 sg = ahc_sg_bus_to_virt(scb, sgptr);
3230 /*
3231 * The residual sg ptr points to the next S/G
3232 * to load so we must go back one.
3233 */
3234 sg--;
3259 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8)
3260 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT));
3261
3262 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24)
3263 | (ahc_inb(ahc, SHADDR + 2) << 16)
3264 | (ahc_inb(ahc, SHADDR + 1) << 8)
3265 | (ahc_inb(ahc, SHADDR));
3266
3267 data_cnt += 1;
3268 data_addr -= 1;
3269
3270 sg = ahc_sg_bus_to_virt(scb, sgptr);
3271 /*
3272 * The residual sg ptr points to the next S/G
3273 * to load so we must go back one.
3274 */
3275 sg--;
3276 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3235 if (sg != scb->sg_list
3277 if (sg != scb->sg_list
3236 && (sg->len & AHC_SG_LEN_MASK) < data_cnt) {
3278 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3237
3238 sg--;
3279
3280 sg--;
3239 data_cnt = 1 | (sg->len & AHC_DMA_LAST_SEG);
3240 data_addr = sg->addr
3241 + (sg->len & AHC_SG_LEN_MASK) - 1;
3281 sglen = ahc_le32toh(sg->len);
3282 /*
3283 * Preserve High Address and SG_LIST bits
3284 * while setting the count to 1.
3285 */
3286 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3287 data_addr = ahc_le32toh(sg->addr)
3288 + (sglen & AHC_SG_LEN_MASK) - 1;
3242
3243 /*
3244 * Increment sg so it points to the
3245 * "next" sg.
3246 */
3247 sg++;
3248 sgptr = ahc_sg_virt_to_bus(scb, sg);
3249 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3,
3250 sgptr >> 24);
3251 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2,
3252 sgptr >> 16);
3253 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1,
3254 sgptr >> 8);
3255 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3256 }
3257
3289
3290 /*
3291 * Increment sg so it points to the
3292 * "next" sg.
3293 */
3294 sg++;
3295 sgptr = ahc_sg_virt_to_bus(scb, sg);
3296 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3,
3297 sgptr >> 24);
3298 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2,
3299 sgptr >> 16);
3300 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1,
3301 sgptr >> 8);
3302 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3303 }
3304
3258/* XXX What about high address byte??? */
3259 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24);
3260 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16);
3261 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8);
3262 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3305 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24);
3306 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16);
3307 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8);
3308 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3263
3264/* XXX Perhaps better to just keep the saved address in sram */
3265 if ((ahc->features & AHC_ULTRA2) != 0) {
3266 ahc_outb(ahc, HADDR + 3, data_addr >> 24);
3267 ahc_outb(ahc, HADDR + 2, data_addr >> 16);
3268 ahc_outb(ahc, HADDR + 1, data_addr >> 8);
3269 ahc_outb(ahc, HADDR, data_addr);
3270 ahc_outb(ahc, DFCNTRL, PRELOADEN);
3271 ahc_outb(ahc, SXFRCTL0,
3272 ahc_inb(ahc, SXFRCTL0) | CLRCHN);
3273 } else {
3274 ahc_outb(ahc, HADDR + 3, data_addr >> 24);
3275 ahc_outb(ahc, HADDR + 2, data_addr >> 16);
3276 ahc_outb(ahc, HADDR + 1, data_addr >> 8);
3277 ahc_outb(ahc, HADDR, data_addr);
3278 }
3279 }
3280 }
3281}
3282
3309 }
3310 }
3311}
3312
3313
3283/*
3314/*
3315 * Reinitialize the data pointers for the active transfer
3316 * based on its current residual.
3317 */
3318static void
3319ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3320{
3321 struct scb *scb;
3322 struct ahc_dma_seg *sg;
3323 u_int scb_index;
3324 uint32_t sgptr;
3325 uint32_t resid;
3326 uint32_t dataptr;
3327
3328 scb_index = ahc_inb(ahc, SCB_TAG);
3329 scb = ahc_lookup_scb(ahc, scb_index);
3330 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3331 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3332 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3333 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3334
3335 sgptr &= SG_PTR_MASK;
3336 sg = ahc_sg_bus_to_virt(scb, sgptr);
3337
3338 /* The residual sg_ptr always points to the next sg */
3339 sg--;
3340
3341 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3342 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3343 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3344
3345 dataptr = ahc_le32toh(sg->addr)
3346 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3347 - resid;
3348 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3349 u_int dscommand1;
3350
3351 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3352 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3353 ahc_outb(ahc, HADDR,
3354 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3355 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3356 }
3357 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3358 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3359 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3360 ahc_outb(ahc, HADDR, dataptr);
3361 ahc_outb(ahc, HCNT + 2, resid >> 16);
3362 ahc_outb(ahc, HCNT + 1, resid >> 8);
3363 ahc_outb(ahc, HCNT, resid);
3364 if ((ahc->features & AHC_ULTRA2) == 0) {
3365 ahc_outb(ahc, STCNT + 2, resid >> 16);
3366 ahc_outb(ahc, STCNT + 1, resid >> 8);
3367 ahc_outb(ahc, STCNT, resid);
3368 }
3369}
3370
3371/*
3284 * Handle the effects of issuing a bus device reset message.
3285 */
3286static void
3287ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3288 cam_status status, char *message, int verbose_level)
3289{
3290#ifdef AHC_TARGET_MODE
3291 struct ahc_tmode_tstate* tstate;

--- 88 unchanged lines hidden (view full) ---

3380#else
3381 ahc = device_get_softc((device_t)platform_arg);
3382#endif
3383 memset(ahc, 0, sizeof(*ahc));
3384 LIST_INIT(&ahc->pending_scbs);
3385 /* We don't know our unit number until the OSM sets it */
3386 ahc->name = name;
3387 ahc->unit = -1;
3372 * Handle the effects of issuing a bus device reset message.
3373 */
3374static void
3375ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3376 cam_status status, char *message, int verbose_level)
3377{
3378#ifdef AHC_TARGET_MODE
3379 struct ahc_tmode_tstate* tstate;

--- 88 unchanged lines hidden (view full) ---

3468#else
3469 ahc = device_get_softc((device_t)platform_arg);
3470#endif
3471 memset(ahc, 0, sizeof(*ahc));
3472 LIST_INIT(&ahc->pending_scbs);
3473 /* We don't know our unit number until the OSM sets it */
3474 ahc->name = name;
3475 ahc->unit = -1;
3476 ahc->description = NULL;
3477 ahc->channel = 'A';
3478 ahc->channel_b = 'B';
3479 ahc->chip = AHC_NONE;
3480 ahc->features = AHC_FENONE;
3481 ahc->bugs = AHC_BUGNONE;
3482 ahc->flags = AHC_FNONE;
3483
3388 for (i = 0; i < 16; i++)
3389 TAILQ_INIT(&ahc->untagged_queues[i]);
3390 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3391 ahc_free(ahc);
3392 ahc = NULL;
3393 }
3394 return (ahc);
3395}
3396
3397int
3484 for (i = 0; i < 16; i++)
3485 TAILQ_INIT(&ahc->untagged_queues[i]);
3486 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3487 ahc_free(ahc);
3488 ahc = NULL;
3489 }
3490 return (ahc);
3491}
3492
3493int
3398ahc_softc_init(struct ahc_softc *ahc, struct ahc_probe_config *config)
3494ahc_softc_init(struct ahc_softc *ahc)
3399{
3400
3495{
3496
3401 ahc->chip = config->chip;
3402 ahc->features = config->features;
3403 ahc->bugs = config->bugs;
3404 ahc->flags = config->flags;
3405 ahc->channel = config->channel;
3406 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS);
3407 ahc->description = config->description;
3408 /* The IRQMS bit is only valid on VL and EISA chips */
3409 if ((ahc->chip & AHC_PCI) != 0)
3410 ahc->unpause &= ~IRQMS;
3411 ahc->pause = ahc->unpause | PAUSE;
3412 /* XXX The shared scb data stuff should be deprecated */
3413 if (ahc->scb_data == NULL) {
3414 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3415 M_DEVBUF, M_NOWAIT);

--- 276 unchanged lines hidden (view full) ---

3692 break;
3693 ahc_outb(ahc, SCBPTR, 0);
3694 if (ahc_inb(ahc, SCB_BASE) != 0)
3695 break;
3696 }
3697 return (i);
3698}
3699
3497 /* The IRQMS bit is only valid on VL and EISA chips */
3498 if ((ahc->chip & AHC_PCI) != 0)
3499 ahc->unpause &= ~IRQMS;
3500 ahc->pause = ahc->unpause | PAUSE;
3501 /* XXX The shared scb data stuff should be deprecated */
3502 if (ahc->scb_data == NULL) {
3503 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3504 M_DEVBUF, M_NOWAIT);

--- 276 unchanged lines hidden (view full) ---

3781 break;
3782 ahc_outb(ahc, SCBPTR, 0);
3783 if (ahc_inb(ahc, SCB_BASE) != 0)
3784 break;
3785 }
3786 return (i);
3787}
3788
3700void
3701ahc_init_probe_config(struct ahc_probe_config *probe_config)
3702{
3703 probe_config->description = NULL;
3704 probe_config->channel = 'A';
3705 probe_config->channel_b = 'B';
3706 probe_config->chip = AHC_NONE;
3707 probe_config->features = AHC_FENONE;
3708 probe_config->bugs = AHC_BUGNONE;
3709 probe_config->flags = AHC_FNONE;
3710}
3711
3712static void
3713ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3714{
3715 bus_addr_t *baddr;
3716
3717 baddr = (bus_addr_t *)arg;
3718 *baddr = segs->ds_addr;
3719}

--- 69 unchanged lines hidden (view full) ---

3789 *
3790 * Unless we need to further restrict the allocation, we rely
3791 * on the restrictions of the parent dmat, hence the common
3792 * use of MAXADDR and MAXSIZE.
3793 */
3794
3795 /* DMA tag for our hardware scb structures */
3796 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3789static void
3790ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3791{
3792 bus_addr_t *baddr;
3793
3794 baddr = (bus_addr_t *)arg;
3795 *baddr = segs->ds_addr;
3796}

--- 69 unchanged lines hidden (view full) ---

3866 *
3867 * Unless we need to further restrict the allocation, we rely
3868 * on the restrictions of the parent dmat, hence the common
3869 * use of MAXADDR and MAXSIZE.
3870 */
3871
3872 /* DMA tag for our hardware scb structures */
3873 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3797 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
3874 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
3875 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3798 /*highaddr*/BUS_SPACE_MAXADDR,
3799 /*filter*/NULL, /*filterarg*/NULL,
3800 AHC_SCB_MAX * sizeof(struct hardware_scb),
3801 /*nsegments*/1,
3802 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3803 /*flags*/0, &scb_data->hscb_dmat) != 0) {
3804 goto error_exit;
3805 }
3806
3807 scb_data->init_level++;
3808
3876 /*highaddr*/BUS_SPACE_MAXADDR,
3877 /*filter*/NULL, /*filterarg*/NULL,
3878 AHC_SCB_MAX * sizeof(struct hardware_scb),
3879 /*nsegments*/1,
3880 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3881 /*flags*/0, &scb_data->hscb_dmat) != 0) {
3882 goto error_exit;
3883 }
3884
3885 scb_data->init_level++;
3886
3809 /* Allocation for our ccbs */
3887 /* Allocation for our hscbs */
3810 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
3811 (void **)&scb_data->hscbs,
3812 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
3813 goto error_exit;
3814 }
3815
3816 scb_data->init_level++;
3817
3818 /* And permanently map them */
3819 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
3820 scb_data->hscbs,
3821 AHC_SCB_MAX * sizeof(struct hardware_scb),
3822 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
3823
3824 scb_data->init_level++;
3825
3826 /* DMA tag for our sense buffers */
3827 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3888 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
3889 (void **)&scb_data->hscbs,
3890 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
3891 goto error_exit;
3892 }
3893
3894 scb_data->init_level++;
3895
3896 /* And permanently map them */
3897 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
3898 scb_data->hscbs,
3899 AHC_SCB_MAX * sizeof(struct hardware_scb),
3900 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
3901
3902 scb_data->init_level++;
3903
3904 /* DMA tag for our sense buffers */
3905 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3828 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
3906 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
3907 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3829 /*highaddr*/BUS_SPACE_MAXADDR,
3830 /*filter*/NULL, /*filterarg*/NULL,
3831 AHC_SCB_MAX * sizeof(struct scsi_sense_data),
3832 /*nsegments*/1,
3833 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3834 /*flags*/0, &scb_data->sense_dmat) != 0) {
3835 goto error_exit;
3836 }

--- 14 unchanged lines hidden (view full) ---

3851 scb_data->sense,
3852 AHC_SCB_MAX * sizeof(struct scsi_sense_data),
3853 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
3854
3855 scb_data->init_level++;
3856
3857 /* DMA tag for our S/G structures. We allocate in page sized chunks */
3858 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3908 /*highaddr*/BUS_SPACE_MAXADDR,
3909 /*filter*/NULL, /*filterarg*/NULL,
3910 AHC_SCB_MAX * sizeof(struct scsi_sense_data),
3911 /*nsegments*/1,
3912 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3913 /*flags*/0, &scb_data->sense_dmat) != 0) {
3914 goto error_exit;
3915 }

--- 14 unchanged lines hidden (view full) ---

3930 scb_data->sense,
3931 AHC_SCB_MAX * sizeof(struct scsi_sense_data),
3932 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
3933
3934 scb_data->init_level++;
3935
3936 /* DMA tag for our S/G structures. We allocate in page sized chunks */
3937 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3859 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
3938 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
3939 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3860 /*highaddr*/BUS_SPACE_MAXADDR,
3861 /*filter*/NULL, /*filterarg*/NULL,
3862 PAGE_SIZE, /*nsegments*/1,
3863 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3864 /*flags*/0, &scb_data->sg_dmat) != 0) {
3865 goto error_exit;
3866 }
3867

--- 126 unchanged lines hidden (view full) ---

3994#ifndef __linux__
3995 int error;
3996#endif
3997 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
3998 M_DEVBUF, M_NOWAIT);
3999 if (pdata == NULL)
4000 break;
4001 next_scb->platform_data = pdata;
3940 /*highaddr*/BUS_SPACE_MAXADDR,
3941 /*filter*/NULL, /*filterarg*/NULL,
3942 PAGE_SIZE, /*nsegments*/1,
3943 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3944 /*flags*/0, &scb_data->sg_dmat) != 0) {
3945 goto error_exit;
3946 }
3947

--- 126 unchanged lines hidden (view full) ---

4074#ifndef __linux__
4075 int error;
4076#endif
4077 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4078 M_DEVBUF, M_NOWAIT);
4079 if (pdata == NULL)
4080 break;
4081 next_scb->platform_data = pdata;
4082 next_scb->sg_map = sg_map;
4002 next_scb->sg_list = segs;
4003 /*
4004 * The sequencer always starts with the second entry.
4005 * The first entry is embedded in the scb.
4006 */
4007 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4008 next_scb->ahc_softc = ahc;
4009 next_scb->flags = SCB_FREE;

--- 111 unchanged lines hidden (view full) ---

4121 * Only allow target mode features if this unit has them enabled.
4122 */
4123 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4124 ahc->features &= ~AHC_TARGETMODE;
4125
4126#ifndef __linux__
4127 /* DMA tag for mapping buffers into device visible space. */
4128 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4083 next_scb->sg_list = segs;
4084 /*
4085 * The sequencer always starts with the second entry.
4086 * The first entry is embedded in the scb.
4087 */
4088 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4089 next_scb->ahc_softc = ahc;
4090 next_scb->flags = SCB_FREE;

--- 111 unchanged lines hidden (view full) ---

4202 * Only allow target mode features if this unit has them enabled.
4203 */
4204 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4205 ahc->features &= ~AHC_TARGETMODE;
4206
4207#ifndef __linux__
4208 /* DMA tag for mapping buffers into device visible space. */
4209 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4129 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
4210 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4211 /*lowaddr*/BUS_SPACE_MAXADDR,
4130 /*highaddr*/BUS_SPACE_MAXADDR,
4131 /*filter*/NULL, /*filterarg*/NULL,
4132 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG,
4133 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4134 /*flags*/BUS_DMA_ALLOCNOW,
4135 &ahc->buffer_dmat) != 0) {
4136 return (ENOMEM);
4137 }

--- 10 unchanged lines hidden (view full) ---

4148 * provide space for the incoming target command fifo and an extra
4149 * byte to deal with a dma bug in some chip versions.
4150 */
4151 driver_data_size = 2 * 256 * sizeof(uint8_t);
4152 if ((ahc->features & AHC_TARGETMODE) != 0)
4153 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4154 + /*DMA WideOdd Bug Buffer*/1;
4155 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4212 /*highaddr*/BUS_SPACE_MAXADDR,
4213 /*filter*/NULL, /*filterarg*/NULL,
4214 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG,
4215 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4216 /*flags*/BUS_DMA_ALLOCNOW,
4217 &ahc->buffer_dmat) != 0) {
4218 return (ENOMEM);
4219 }

--- 10 unchanged lines hidden (view full) ---

4230 * provide space for the incoming target command fifo and an extra
4231 * byte to deal with a dma bug in some chip versions.
4232 */
4233 driver_data_size = 2 * 256 * sizeof(uint8_t);
4234 if ((ahc->features & AHC_TARGETMODE) != 0)
4235 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4236 + /*DMA WideOdd Bug Buffer*/1;
4237 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4156 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
4238 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4239 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4157 /*highaddr*/BUS_SPACE_MAXADDR,
4158 /*filter*/NULL, /*filterarg*/NULL,
4159 driver_data_size,
4160 /*nsegments*/1,
4161 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4162 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4163 return (ENOMEM);
4164 }

--- 17 unchanged lines hidden (view full) ---

4182 if ((ahc->features & AHC_TARGETMODE) != 0) {
4183 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4184 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4185 ahc->dma_bug_buf = ahc->shared_data_busaddr
4186 + driver_data_size - 1;
4187 /* All target command blocks start out invalid. */
4188 for (i = 0; i < AHC_TMODE_CMDS; i++)
4189 ahc->targetcmds[i].cmd_valid = 0;
4240 /*highaddr*/BUS_SPACE_MAXADDR,
4241 /*filter*/NULL, /*filterarg*/NULL,
4242 driver_data_size,
4243 /*nsegments*/1,
4244 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4245 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4246 return (ENOMEM);
4247 }

--- 17 unchanged lines hidden (view full) ---

4265 if ((ahc->features & AHC_TARGETMODE) != 0) {
4266 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4267 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4268 ahc->dma_bug_buf = ahc->shared_data_busaddr
4269 + driver_data_size - 1;
4270 /* All target command blocks start out invalid. */
4271 for (i = 0; i < AHC_TMODE_CMDS; i++)
4272 ahc->targetcmds[i].cmd_valid = 0;
4273 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4190 ahc->tqinfifonext = 1;
4191 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4192 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4193 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4194 }
4195 ahc->qinfifo = &ahc->qoutfifo[256];
4196
4197 ahc->init_level++;

--- 228 unchanged lines hidden (view full) ---

4426 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4427 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4428 }
4429 }
4430
4431 /* All of our queues are empty */
4432 for (i = 0; i < 256; i++)
4433 ahc->qoutfifo[i] = SCB_LIST_NULL;
4274 ahc->tqinfifonext = 1;
4275 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4276 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4277 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4278 }
4279 ahc->qinfifo = &ahc->qoutfifo[256];
4280
4281 ahc->init_level++;

--- 228 unchanged lines hidden (view full) ---

4510 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4511 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4512 }
4513 }
4514
4515 /* All of our queues are empty */
4516 for (i = 0; i < 256; i++)
4517 ahc->qoutfifo[i] = SCB_LIST_NULL;
4518 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4434
4435 for (i = 0; i < 256; i++)
4436 ahc->qinfifo[i] = SCB_LIST_NULL;
4437
4438 if ((ahc->features & AHC_MULTI_TID) != 0) {
4439 ahc_outb(ahc, TARGID, 0);
4440 ahc_outb(ahc, TARGID + 1, 0);
4441 }

--- 449 unchanged lines hidden (view full) ---

4891 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4892 }
4893}
4894
4895static void
4896ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
4897 struct scb *scb)
4898{
4519
4520 for (i = 0; i < 256; i++)
4521 ahc->qinfifo[i] = SCB_LIST_NULL;
4522
4523 if ((ahc->features & AHC_MULTI_TID) != 0) {
4524 ahc_outb(ahc, TARGID, 0);
4525 ahc_outb(ahc, TARGID + 1, 0);
4526 }

--- 449 unchanged lines hidden (view full) ---

4976 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4977 }
4978}
4979
4980static void
4981ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
4982 struct scb *scb)
4983{
4899 if (prev_scb == NULL)
4984 if (prev_scb == NULL) {
4900 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
4985 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
4901 else
4986 } else {
4902 prev_scb->hscb->next = scb->hscb->tag;
4987 prev_scb->hscb->next = scb->hscb->tag;
4988 ahc_sync_scb(ahc, prev_scb,
4989 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
4990 }
4903 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
4904 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
4991 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
4992 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
4993 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
4905}
4906
4907static int
4908ahc_qinfifo_count(struct ahc_softc *ahc)
4909{
4910 u_int8_t qinpos;
4911 u_int8_t diff;
4912

--- 30 unchanged lines hidden (view full) ---

4943 ahc_outb(ahc, SNSCB_QOFF, qinstart);
4944 } else
4945 qinstart = ahc_inb(ahc, QINPOS);
4946 qinpos = qinstart;
4947 next = ahc_inb(ahc, NEXT_QUEUED_SCB);
4948 found = 0;
4949 prev_scb = NULL;
4950
4994}
4995
4996static int
4997ahc_qinfifo_count(struct ahc_softc *ahc)
4998{
4999 u_int8_t qinpos;
5000 u_int8_t diff;
5001

--- 30 unchanged lines hidden (view full) ---

5032 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5033 } else
5034 qinstart = ahc_inb(ahc, QINPOS);
5035 qinpos = qinstart;
5036 next = ahc_inb(ahc, NEXT_QUEUED_SCB);
5037 found = 0;
5038 prev_scb = NULL;
5039
5040 if (bootverbose)
5041 printf("qinpos = %d, qintail = %d\n", qinpos, qintail);
5042
4951 if (action == SEARCH_COMPLETE) {
4952 /*
4953 * Don't attempt to run any queued untagged transactions
4954 * until we are done with the abort process.
4955 */
4956 ahc_freeze_untagged_queues(ahc);
4957 }
4958
4959 /*
4960 * Start with an empty queue. Entries that are not chosen
4961 * for removal will be re-added to the queue as we go.
4962 */
4963 ahc->qinfifonext = qinpos;
4964 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4965
4966 while (qinpos != qintail) {
4967 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5043 if (action == SEARCH_COMPLETE) {
5044 /*
5045 * Don't attempt to run any queued untagged transactions
5046 * until we are done with the abort process.
5047 */
5048 ahc_freeze_untagged_queues(ahc);
5049 }
5050
5051 /*
5052 * Start with an empty queue. Entries that are not chosen
5053 * for removal will be re-added to the queue as we go.
5054 */
5055 ahc->qinfifonext = qinpos;
5056 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5057
5058 while (qinpos != qintail) {
5059 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5060 if (scb == NULL) {
5061 printf("qinpos = %d, SCB index = %d\n",
5062 qinpos, ahc->qinfifo[qinpos]);
5063 panic("Loop 1\n");
5064 }
5065
4968 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
4969 /*
4970 * We found an scb that needs to be acted on.
4971 */
4972 found++;
4973 switch (action) {
4974 case SEARCH_COMPLETE:
4975 {

--- 45 unchanged lines hidden (view full) ---

5021 * SCB to dma). If we have removed any entries, swap
5022 * the first element in the queue with the next HSCB
5023 * so the sequencer will notice that NEXT_QUEUED_SCB
5024 * has changed during its dma attempt and will retry
5025 * the DMA.
5026 */
5027 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5028
5066 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5067 /*
5068 * We found an scb that needs to be acted on.
5069 */
5070 found++;
5071 switch (action) {
5072 case SEARCH_COMPLETE:
5073 {

--- 45 unchanged lines hidden (view full) ---

5119 * SCB to dma). If we have removed any entries, swap
5120 * the first element in the queue with the next HSCB
5121 * so the sequencer will notice that NEXT_QUEUED_SCB
5122 * has changed during its dma attempt and will retry
5123 * the DMA.
5124 */
5125 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5126
5127 if (scb == NULL) {
5128 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5129 found, qinstart, ahc->qinfifonext);
5130 panic("First/Second Qinfifo fixup\n");
5131 }
5029 /*
5030 * ahc_swap_with_next_hscb forces our next pointer to
5031 * point to the reserved SCB for future commands. Save
5032 * and restore our original next pointer to maintain
5033 * queue integrity.
5034 */
5035 next = scb->hscb->next;
5036 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;

--- 25 unchanged lines hidden (view full) ---

5062 if (scb_index >= ahc->scb_data->numscbs) {
5063 printf("Waiting List inconsistency. "
5064 "SCB index == %d, yet numscbs == %d.",
5065 scb_index, ahc->scb_data->numscbs);
5066 ahc_dump_card_state(ahc);
5067 panic("for safety");
5068 }
5069 scb = ahc_lookup_scb(ahc, scb_index);
5132 /*
5133 * ahc_swap_with_next_hscb forces our next pointer to
5134 * point to the reserved SCB for future commands. Save
5135 * and restore our original next pointer to maintain
5136 * queue integrity.
5137 */
5138 next = scb->hscb->next;
5139 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;

--- 25 unchanged lines hidden (view full) ---

5165 if (scb_index >= ahc->scb_data->numscbs) {
5166 printf("Waiting List inconsistency. "
5167 "SCB index == %d, yet numscbs == %d.",
5168 scb_index, ahc->scb_data->numscbs);
5169 ahc_dump_card_state(ahc);
5170 panic("for safety");
5171 }
5172 scb = ahc_lookup_scb(ahc, scb_index);
5173 if (scb == NULL) {
5174 printf("scb_index = %d, next = %d\n",
5175 scb_index, next);
5176 panic("Waiting List traversal\n");
5177 }
5070 if (ahc_match_scb(ahc, scb, target, channel,
5071 lun, SCB_LIST_NULL, role)) {
5072 /*
5073 * We found an scb that needs to be acted on.
5074 */
5075 found++;
5076 switch (action) {
5077 case SEARCH_COMPLETE:

--- 407 unchanged lines hidden (view full) ---

5485}
5486
5487int
5488ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5489{
5490 struct ahc_devinfo devinfo;
5491 u_int initiator, target, max_scsiid;
5492 u_int sblkctl;
5178 if (ahc_match_scb(ahc, scb, target, channel,
5179 lun, SCB_LIST_NULL, role)) {
5180 /*
5181 * We found an scb that needs to be acted on.
5182 */
5183 found++;
5184 switch (action) {
5185 case SEARCH_COMPLETE:

--- 407 unchanged lines hidden (view full) ---

5593}
5594
5595int
5596ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5597{
5598 struct ahc_devinfo devinfo;
5599 u_int initiator, target, max_scsiid;
5600 u_int sblkctl;
5601 u_int scsiseq;
5602 u_int simode1;
5493 int found;
5494 int restart_needed;
5495 char cur_channel;
5496
5497 ahc->pending_device = NULL;
5498
5499 ahc_compile_devinfo(&devinfo,
5500 CAM_TARGET_WILDCARD,

--- 20 unchanged lines hidden (view full) ---

5521 /*
5522 * Reset the bus if we are initiating this reset
5523 */
5524 sblkctl = ahc_inb(ahc, SBLKCTL);
5525 cur_channel = 'A';
5526 if ((ahc->features & AHC_TWIN) != 0
5527 && ((sblkctl & SELBUSB) != 0))
5528 cur_channel = 'B';
5603 int found;
5604 int restart_needed;
5605 char cur_channel;
5606
5607 ahc->pending_device = NULL;
5608
5609 ahc_compile_devinfo(&devinfo,
5610 CAM_TARGET_WILDCARD,

--- 20 unchanged lines hidden (view full) ---

5631 /*
5632 * Reset the bus if we are initiating this reset
5633 */
5634 sblkctl = ahc_inb(ahc, SBLKCTL);
5635 cur_channel = 'A';
5636 if ((ahc->features & AHC_TWIN) != 0
5637 && ((sblkctl & SELBUSB) != 0))
5638 cur_channel = 'B';
5639 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5529 if (cur_channel != channel) {
5530 /* Case 1: Command for another bus is active
5531 * Stealthily reset the other bus without
5532 * upsetting the current bus.
5533 */
5534 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5640 if (cur_channel != channel) {
5641 /* Case 1: Command for another bus is active
5642 * Stealthily reset the other bus without
5643 * upsetting the current bus.
5644 */
5645 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5535 ahc_outb(ahc, SIMODE1,
5536 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
5537 ahc_outb(ahc, SCSISEQ,
5538 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
5646 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5647 ahc_outb(ahc, SIMODE1, simode1);
5539 if (initiate_reset)
5540 ahc_reset_current_bus(ahc);
5541 ahc_clear_intstat(ahc);
5648 if (initiate_reset)
5649 ahc_reset_current_bus(ahc);
5650 ahc_clear_intstat(ahc);
5651#if AHC_TARGET_MODE
5652 /*
5653 * Bus resets clear ENSELI, so we cannot
5654 * defer re-enabling bus reset interrupts
5655 * if we are in target mode.
5656 */
5657 if ((ahc->flags & AHC_TARGETROLE) != 0)
5658 ahc_outb(ahc, SIMODE1, simode1 | ENSCSIRST);
5659#endif
5660 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5542 ahc_outb(ahc, SBLKCTL, sblkctl);
5543 restart_needed = FALSE;
5544 } else {
5545 /* Case 2: A command from this bus is active or we're idle */
5546 ahc_clear_msg_state(ahc);
5661 ahc_outb(ahc, SBLKCTL, sblkctl);
5662 restart_needed = FALSE;
5663 } else {
5664 /* Case 2: A command from this bus is active or we're idle */
5665 ahc_clear_msg_state(ahc);
5547 ahc_outb(ahc, SIMODE1,
5548 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
5549 ahc_outb(ahc, SCSISEQ,
5550 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
5666 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5667 ahc_outb(ahc, SIMODE1, simode1);
5551 if (initiate_reset)
5552 ahc_reset_current_bus(ahc);
5553 ahc_clear_intstat(ahc);
5668 if (initiate_reset)
5669 ahc_reset_current_bus(ahc);
5670 ahc_clear_intstat(ahc);
5671#if AHC_TARGET_MODE
5672 /*
5673 * Bus resets clear ENSELI, so we cannot
5674 * defer re-enabling bus reset interrupts
5675 * if we are in target mode.
5676 */
5677 if ((ahc->flags & AHC_TARGETROLE) != 0)
5678 ahc_outb(ahc, SIMODE1, simode1 | ENSCSIRST);
5679#endif
5680 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5554 restart_needed = TRUE;
5555 }
5556
5557 /*
5558 * Clean up all the state information for the
5559 * pending transactions on this bus.
5560 */
5561 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,

--- 135 unchanged lines hidden (view full) ---

5697 }
5698 }
5699 if ((scb->flags & SCB_SENSE) == 0)
5700 ahc_set_residual(scb, resid);
5701 else
5702 ahc_set_sense_residual(scb, resid);
5703
5704#ifdef AHC_DEBUG
5681 restart_needed = TRUE;
5682 }
5683
5684 /*
5685 * Clean up all the state information for the
5686 * pending transactions on this bus.
5687 */
5688 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,

--- 135 unchanged lines hidden (view full) ---

5824 }
5825 }
5826 if ((scb->flags & SCB_SENSE) == 0)
5827 ahc_set_residual(scb, resid);
5828 else
5829 ahc_set_sense_residual(scb, resid);
5830
5831#ifdef AHC_DEBUG
5705 if (ahc_debug & AHC_SHOWMISC) {
5832 if ((ahc_debug & AHC_SHOWMISC) != 0) {
5706 ahc_print_path(ahc, scb);
5707 printf("Handled Residual of %d bytes\n", resid);
5708 }
5709#endif
5710}
5711
5712/******************************* Target Mode **********************************/
5713#ifdef AHC_TARGET_MODE

--- 438 unchanged lines hidden (view full) ---

6152 i = 0;
6153 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6154 ahc_outb(ahc, SCBPTR, scb_index);
6155 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6156 scb_index = ahc_inb(ahc, SCB_NEXT);
6157 }
6158 printf("\n");
6159
5833 ahc_print_path(ahc, scb);
5834 printf("Handled Residual of %d bytes\n", resid);
5835 }
5836#endif
5837}
5838
5839/******************************* Target Mode **********************************/
5840#ifdef AHC_TARGET_MODE

--- 438 unchanged lines hidden (view full) ---

6279 i = 0;
6280 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6281 ahc_outb(ahc, SCBPTR, scb_index);
6282 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6283 scb_index = ahc_inb(ahc, SCB_NEXT);
6284 }
6285 printf("\n");
6286
6287 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6160 printf("QOUTFIFO entries: ");
6161 qoutpos = ahc->qoutfifonext;
6162 i = 0;
6163 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6164 printf("%d ", ahc->qoutfifo[qoutpos]);
6165 qoutpos++;
6166 }
6167 printf("\n");

--- 456 unchanged lines hidden (view full) ---

6624 /*
6625 * If the card supports auto-access pause,
6626 * we can access the card directly regardless
6627 * of whether it is paused or not.
6628 */
6629 if ((ahc->features & AHC_AUTOPAUSE) != 0)
6630 paused = TRUE;
6631
6288 printf("QOUTFIFO entries: ");
6289 qoutpos = ahc->qoutfifonext;
6290 i = 0;
6291 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6292 printf("%d ", ahc->qoutfifo[qoutpos]);
6293 qoutpos++;
6294 }
6295 printf("\n");

--- 456 unchanged lines hidden (view full) ---

6752 /*
6753 * If the card supports auto-access pause,
6754 * we can access the card directly regardless
6755 * of whether it is paused or not.
6756 */
6757 if ((ahc->features & AHC_AUTOPAUSE) != 0)
6758 paused = TRUE;
6759
6760 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
6632 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
6633
6634 /*
6635 * Only advance through the queue if we
6636 * have the resources to process the command.
6637 */
6638 if (ahc_handle_target_cmd(ahc, cmd) != 0)
6639 break;
6640
6761 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
6762
6763 /*
6764 * Only advance through the queue if we
6765 * have the resources to process the command.
6766 */
6767 if (ahc_handle_target_cmd(ahc, cmd) != 0)
6768 break;
6769
6641 ahc->tqinfifonext++;
6642 cmd->cmd_valid = 0;
6770 cmd->cmd_valid = 0;
6771 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
6772 ahc->shared_data_dmamap,
6773 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
6774 sizeof(struct target_cmd),
6775 BUS_DMASYNC_PREREAD);
6776 ahc->tqinfifonext++;
6643
6644 /*
6645 * Lazily update our position in the target mode incoming
6646 * command queue as seen by the sequencer.
6647 */
6648 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
6649 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
6650 u_int hs_mailbox;

--- 129 unchanged lines hidden --- 		6777
6778 /*
6779 * Lazily update our position in the target mode incoming
6780 * command queue as seen by the sequencer.
6781 */
6782 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
6783 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
6784 u_int hs_mailbox;

--- 129 unchanged lines hidden ---