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aic7xxx.c (72325) aic7xxx.c (72811)
1/*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
1/*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/src/aic7xxx/aic7xxx.c#28 $
31 * $Id: //depot/src/aic7xxx/aic7xxx.c#30 $
32 *
32 *
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 72325 2001-02-10 18:04:27Z gibbs $
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 72811 2001-02-21 20:50:36Z gibbs $
34 */
35
36#ifdef __linux__
37#include "aic7xxx_linux.h"
38#include "aic7xxx_inline.h"
39#include "aicasm/aicasm_insformat.h"
40#endif
41

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882 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
883 else
884 status0 = 0;
885 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
886 if (status == 0 && status0 == 0) {
887 if ((ahc->features & AHC_TWIN) != 0) {
888 /* Try the other channel */
889 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
34 */
35
36#ifdef __linux__
37#include "aic7xxx_linux.h"
38#include "aic7xxx_inline.h"
39#include "aicasm/aicasm_insformat.h"
40#endif
41

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882 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
883 else
884 status0 = 0;
885 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
886 if (status == 0 && status0 == 0) {
887 if ((ahc->features & AHC_TWIN) != 0) {
888 /* Try the other channel */
889 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
890 status = ahc_inb(ahc, SSTAT1);
891 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
890 status = ahc_inb(ahc, SSTAT1)
891 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
892 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
893 }
894 if (status == 0) {
895 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
896 ahc_outb(ahc, CLRINT, CLRSCSIINT);
897 unpause_sequencer(ahc);
898 return;
899 }

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923 * a bus reset anyway, asserting the reset line
924 * ourselves is safe.
925 */
926 ahc_reset_channel(ahc, intr_channel,
927 /*Initiate Reset*/now_lvd == 0);
928 } else if ((status & SCSIRSTI) != 0) {
929 printf("%s: Someone reset channel %c\n",
930 ahc_name(ahc), intr_channel);
892 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
893 }
894 if (status == 0) {
895 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
896 ahc_outb(ahc, CLRINT, CLRSCSIINT);
897 unpause_sequencer(ahc);
898 return;
899 }

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923 * a bus reset anyway, asserting the reset line
924 * ourselves is safe.
925 */
926 ahc_reset_channel(ahc, intr_channel,
927 /*Initiate Reset*/now_lvd == 0);
928 } else if ((status & SCSIRSTI) != 0) {
929 printf("%s: Someone reset channel %c\n",
930 ahc_name(ahc), intr_channel);
931 if (intr_channel != cur_channel)
932 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
931 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
932 } else if ((status & SCSIPERR) != 0) {
933 /*
934 * Determine the bus phase and queue an appropriate message.
935 * SCSIPERR is latched true as soon as a parity error
936 * occurs. If the sequencer acked the transfer that
937 * caused the parity error and the currently presented
938 * transfer on the bus has correct parity, SCSIPERR will

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1699
1700 if (syncrate == NULL) {
1701 period = 0;
1702 offset = 0;
1703 }
1704
1705 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1706 devinfo->target, &tstate);
933 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
934 } else if ((status & SCSIPERR) != 0) {
935 /*
936 * Determine the bus phase and queue an appropriate message.
937 * SCSIPERR is latched true as soon as a parity error
938 * occurs. If the sequencer acked the transfer that
939 * caused the parity error and the currently presented
940 * transfer on the bus has correct parity, SCSIPERR will

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1701
1702 if (syncrate == NULL) {
1703 period = 0;
1704 offset = 0;
1705 }
1706
1707 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1708 devinfo->target, &tstate);
1709
1710 if ((type & AHC_TRANS_USER) != 0) {
1711 tinfo->user.period = period;
1712 tinfo->user.offset = offset;
1713 tinfo->user.ppr_options = ppr_options;
1714 }
1715
1716 if ((type & AHC_TRANS_GOAL) != 0) {
1717 tinfo->goal.period = period;
1718 tinfo->goal.offset = offset;
1719 tinfo->goal.ppr_options = ppr_options;
1720 }
1721
1707 old_period = tinfo->current.period;
1708 old_offset = tinfo->current.offset;
1709 old_ppr = tinfo->current.ppr_options;
1710
1711 if ((type & AHC_TRANS_CUR) != 0
1712 && (old_period != period
1713 || old_offset != offset
1714 || old_ppr != ppr_options)) {

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1777 } else {
1778 printf("%s: target %d using "
1779 "asynchronous transfers\n",
1780 ahc_name(ahc), devinfo->target);
1781 }
1782 }
1783 }
1784
1722 old_period = tinfo->current.period;
1723 old_offset = tinfo->current.offset;
1724 old_ppr = tinfo->current.ppr_options;
1725
1726 if ((type & AHC_TRANS_CUR) != 0
1727 && (old_period != period
1728 || old_offset != offset
1729 || old_ppr != ppr_options)) {

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1792 } else {
1793 printf("%s: target %d using "
1794 "asynchronous transfers\n",
1795 ahc_name(ahc), devinfo->target);
1796 }
1797 }
1798 }
1799
1785 if ((type & AHC_TRANS_GOAL) != 0) {
1786 tinfo->goal.period = period;
1787 tinfo->goal.offset = offset;
1788 tinfo->goal.ppr_options = ppr_options;
1789 }
1790
1791 if ((type & AHC_TRANS_USER) != 0) {
1792 tinfo->user.period = period;
1793 tinfo->user.offset = offset;
1794 tinfo->user.ppr_options = ppr_options;
1795 }
1796
1797 ahc_update_target_msg_request(ahc, devinfo, tinfo,
1798 /*force*/FALSE,
1799 paused);
1800}
1801
1802/*
1803 * Update the user/goal/current tables of wide negotiation
1804 * parameters as well as, in the case of a current or active update,

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1813{
1814 struct ahc_initiator_tinfo *tinfo;
1815 struct tmode_tstate *tstate;
1816 u_int oldwidth;
1817 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1818
1819 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1820 devinfo->target, &tstate);
1800 ahc_update_target_msg_request(ahc, devinfo, tinfo,
1801 /*force*/FALSE,
1802 paused);
1803}
1804
1805/*
1806 * Update the user/goal/current tables of wide negotiation
1807 * parameters as well as, in the case of a current or active update,

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1816{
1817 struct ahc_initiator_tinfo *tinfo;
1818 struct tmode_tstate *tstate;
1819 u_int oldwidth;
1820 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1821
1822 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1823 devinfo->target, &tstate);
1821 oldwidth = tinfo->current.width;
1822
1824
1825 if ((type & AHC_TRANS_USER) != 0)
1826 tinfo->user.width = width;
1827
1828 if ((type & AHC_TRANS_GOAL) != 0)
1829 tinfo->goal.width = width;
1830
1831 oldwidth = tinfo->current.width;
1823 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
1824 u_int scsirate;
1825
1826 scsirate = tinfo->scsirate;
1827 scsirate &= ~WIDEXFER;
1828 if (width == MSG_EXT_WDTR_BUS_16_BIT)
1829 scsirate |= WIDEXFER;
1830

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1838 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1839 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
1840 if (bootverbose) {
1841 printf("%s: target %d using %dbit transfers\n",
1842 ahc_name(ahc), devinfo->target,
1843 8 * (0x01 << width));
1844 }
1845 }
1832 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
1833 u_int scsirate;
1834
1835 scsirate = tinfo->scsirate;
1836 scsirate &= ~WIDEXFER;
1837 if (width == MSG_EXT_WDTR_BUS_16_BIT)
1838 scsirate |= WIDEXFER;
1839

--- 7 unchanged lines hidden (view full) ---

1847 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1848 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
1849 if (bootverbose) {
1850 printf("%s: target %d using %dbit transfers\n",
1851 ahc_name(ahc), devinfo->target,
1852 8 * (0x01 << width));
1853 }
1854 }
1846 if ((type & AHC_TRANS_GOAL) != 0)
1847 tinfo->goal.width = width;
1848 if ((type & AHC_TRANS_USER) != 0)
1849 tinfo->user.width = width;
1850
1851 ahc_update_target_msg_request(ahc, devinfo, tinfo,
1852 /*force*/FALSE, paused);
1853}
1854
1855/*
1856 * Update the current state of tagged queuing for a given target.
1857 */

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3058
3059 /*
3060 * This transaction is now at the head of
3061 * the untagged queue for this target.
3062 */
3063 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3064 struct scb_tailq *untagged_q;
3065
1855
1856 ahc_update_target_msg_request(ahc, devinfo, tinfo,
1857 /*force*/FALSE, paused);
1858}
1859
1860/*
1861 * Update the current state of tagged queuing for a given target.
1862 */

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3063
3064 /*
3065 * This transaction is now at the head of
3066 * the untagged queue for this target.
3067 */
3068 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3069 struct scb_tailq *untagged_q;
3070
3066 untagged_q = &(ahc->untagged_queues[devinfo->target]);
3071 untagged_q =
3072 &(ahc->untagged_queues[devinfo->target_offset]);
3067 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3068 scb->flags |= SCB_UNTAGGEDQ;
3069 }
3070 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3071 scb->hscb->tag);
3072
3073 /*
3074 * Requeue all tagged commands for this target

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5989 uint8_t saved_scbptr;
5990
5991 saved_scbptr = ahc_inb(ahc, SCBPTR);
5992
5993 printf("%s: Dumping Card State at SEQADDR 0x%x\n",
5994 ahc_name(ahc),
5995 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
5996
3073 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3074 scb->flags |= SCB_UNTAGGEDQ;
3075 }
3076 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3077 scb->hscb->tag);
3078
3079 /*
3080 * Requeue all tagged commands for this target

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5995 uint8_t saved_scbptr;
5996
5997 saved_scbptr = ahc_inb(ahc, SCBPTR);
5998
5999 printf("%s: Dumping Card State at SEQADDR 0x%x\n",
6000 ahc_name(ahc),
6001 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6002
6003 printf("SCSISEQ = 0x%x, SBLKCTL = 0x%x, SSTAT0 0x%x\n",
6004 ahc_inb(ahc, SCSISEQ), ahc_inb(ahc, SBLKCTL),
6005 ahc_inb(ahc, SSTAT0));
5997 printf("SCB count = %d\n", ahc->scb_data->numscbs);
5998 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
5999 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6000 /* QINFIFO */
6001 printf("QINFIFO entries: ");
6002 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6003 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6004 ahc_outb(ahc, SNSCB_QOFF, qinpos);

--- 648 unchanged lines hidden --- 		6006 printf("SCB count = %d\n", ahc->scb_data->numscbs);
6007 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6008 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6009 /* QINFIFO */
6010 printf("QINFIFO entries: ");
6011 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6012 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6013 ahc_outb(ahc, SNSCB_QOFF, qinpos);

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