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agp_i810.c (162690) agp_i810.c (171433)
1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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26 */
27
28/*
29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 */
27
28/*
29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/agp/agp_i810.c 162690 2006-09-27 06:38:54Z anholt $");
34__FBSDID("$FreeBSD: head/sys/dev/agp/agp_i810.c 171433 2007-07-13 16:28:12Z anholt $");
35
36#include "opt_bus.h"
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/module.h>

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53#include <vm/vm.h>
54#include <vm/vm_object.h>
55#include <vm/vm_page.h>
56#include <vm/vm_pageout.h>
57#include <vm/pmap.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
35
36#include "opt_bus.h"
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/module.h>

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53#include <vm/vm.h>
54#include <vm/vm_object.h>
55#include <vm/vm_page.h>
56#include <vm/vm_pageout.h>
57#include <vm/pmap.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
61#include <machine/md_var.h>
61#include <sys/rman.h>
62
63MALLOC_DECLARE(M_AGP);
64
62#include <sys/rman.h>
63
64MALLOC_DECLARE(M_AGP);
65
65#define READ1(off) bus_space_read_1(sc->bst, sc->bsh, off)
66#define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off)
67#define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v)
68#define WRITEGTT(off,v) bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v)
66enum {
67 CHIP_I810, /* i810/i815 */
68 CHIP_I830, /* 830M/845G */
69 CHIP_I855, /* 852GM/855GM/865G */
70 CHIP_I915, /* 915G/915GM */
71 CHIP_I965, /* G965 */
72 CHIP_G33, /* G33/Q33/Q35 */
73};
69
74
70#define CHIP_I810 0 /* i810/i815 */
71#define CHIP_I830 1 /* 830M/845G */
72#define CHIP_I855 2 /* 852GM/855GM/865G */
73#define CHIP_I915 3 /* 915G/915GM */
75/* The i810 through i855 have the registers at BAR 1, and the GATT gets
76 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
77 * start of the stolen memory, and should only be accessed by the OS through
78 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
79 * is registers, second 512KB is GATT.
80 */
81static struct resource_spec agp_i810_res_spec[] = {
82 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
83 { -1, 0 }
84};
74
85
86static struct resource_spec agp_i915_res_spec[] = {
87 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
88 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
89 { -1, 0 }
90};
91
92static struct resource_spec agp_i965_res_spec[] = {
93 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
94 { -1, 0 }
95};
96
75struct agp_i810_softc {
76 struct agp_softc agp;
77 u_int32_t initial_aperture; /* aperture size at startup */
78 struct agp_gatt *gatt;
79 int chiptype; /* i810-like or i830 */
80 u_int32_t dcache_size; /* i810 only */
81 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
82 device_t bdev; /* bridge device */
83
97struct agp_i810_softc {
98 struct agp_softc agp;
99 u_int32_t initial_aperture; /* aperture size at startup */
100 struct agp_gatt *gatt;
101 int chiptype; /* i810-like or i830 */
102 u_int32_t dcache_size; /* i810 only */
103 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
104 device_t bdev; /* bridge device */
105
84 struct resource *regs; /* memory mapped GC registers */
85 bus_space_tag_t bst; /* bus_space tag */
86 bus_space_handle_t bsh; /* bus_space handle */
87
88 struct resource *gtt; /* memory mapped GATT entries */
89 bus_space_tag_t gtt_bst; /* bus_space tag */
90 bus_space_handle_t gtt_bsh; /* bus_space handle */
91
92 struct resource *gm; /* unmapped (but allocated) aperture */
93
94 void *argb_cursor; /* contigmalloc area for ARGB cursor */
106 void *argb_cursor; /* contigmalloc area for ARGB cursor */
107
108 struct resource_spec * sc_res_spec;
109 struct resource *sc_res[2];
95};
96
97/* For adding new devices, devid is the id of the graphics controller
98 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
99 * second head should never be added. The bridge_offset is the offset to
100 * subtract from devid to get the id of the hostb that the device is on.
101 */
102static const struct agp_i810_match {

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122 {0x25828086, CHIP_I915, 0x00020000,
123 "Intel 82915G (915G GMCH) SVGA controller"},
124 {0x25928086, CHIP_I915, 0x00020000,
125 "Intel 82915GM (915GM GMCH) SVGA controller"},
126 {0x27728086, CHIP_I915, 0x00020000,
127 "Intel 82945G (945G GMCH) SVGA controller"},
128 {0x27A28086, CHIP_I915, 0x00020000,
129 "Intel 82945GM (945GM GMCH) SVGA controller"},
110};
111
112/* For adding new devices, devid is the id of the graphics controller
113 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
114 * second head should never be added. The bridge_offset is the offset to
115 * subtract from devid to get the id of the hostb that the device is on.
116 */
117static const struct agp_i810_match {

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137 {0x25828086, CHIP_I915, 0x00020000,
138 "Intel 82915G (915G GMCH) SVGA controller"},
139 {0x25928086, CHIP_I915, 0x00020000,
140 "Intel 82915GM (915GM GMCH) SVGA controller"},
141 {0x27728086, CHIP_I915, 0x00020000,
142 "Intel 82945G (945G GMCH) SVGA controller"},
143 {0x27A28086, CHIP_I915, 0x00020000,
144 "Intel 82945GM (945GM GMCH) SVGA controller"},
145 {0x27A28086, CHIP_I915, 0x00020000,
146 "Intel 945GME SVGA controller"},
147 {0x29728086, CHIP_I965, 0x00020000,
148 "Intel 946GZ SVGA controller"},
149 {0x29828086, CHIP_I965, 0x00020000,
150 "Intel G965 SVGA controller"},
151 {0x29928086, CHIP_I965, 0x00020000,
152 "Intel Q965 SVGA controller"},
153 {0x29a28086, CHIP_I965, 0x00020000,
154 "Intel G965 SVGA controller"},
155/*
156 {0x29b28086, CHIP_G33, 0x00020000,
157 "Intel Q35 SVGA controller"},
158 {0x29c28086, CHIP_G33, 0x00020000,
159 "Intel G33 SVGA controller"},
160 {0x29d28086, CHIP_G33, 0x00020000,
161 "Intel Q33 SVGA controller"},
162*/
163 {0x2a028086, CHIP_I965, 0x00020000,
164 "Intel GM965 SVGA controller"},
165 {0x2a128086, CHIP_I965, 0x00020000,
166 "Intel GME965 SVGA controller"},
130 {0, 0, 0, NULL}
131};
132
133static const struct agp_i810_match*
134agp_i810_match(device_t dev)
135{
136 int i, devid;
137

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189 device_add_child(parent, "agp", -1);
190}
191
192static int
193agp_i810_probe(device_t dev)
194{
195 device_t bdev;
196 const struct agp_i810_match *match;
167 {0, 0, 0, NULL}
168};
169
170static const struct agp_i810_match*
171agp_i810_match(device_t dev)
172{
173 int i, devid;
174

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226 device_add_child(parent, "agp", -1);
227}
228
229static int
230agp_i810_probe(device_t dev)
231{
232 device_t bdev;
233 const struct agp_i810_match *match;
234 u_int8_t smram;
235 int gcc1, deven;
197
198 if (resource_disabled("agp", device_get_unit(dev)))
199 return (ENXIO);
200 match = agp_i810_match(dev);
201 if (match == NULL)
202 return ENXIO;
203
204 bdev = agp_i810_find_bridge(dev);
205 if (!bdev) {
206 if (bootverbose)
207 printf("I810: can't find bridge device\n");
208 return ENXIO;
209 }
210
211 /*
212 * checking whether internal graphics device has been activated.
213 */
236
237 if (resource_disabled("agp", device_get_unit(dev)))
238 return (ENXIO);
239 match = agp_i810_match(dev);
240 if (match == NULL)
241 return ENXIO;
242
243 bdev = agp_i810_find_bridge(dev);
244 if (!bdev) {
245 if (bootverbose)
246 printf("I810: can't find bridge device\n");
247 return ENXIO;
248 }
249
250 /*
251 * checking whether internal graphics device has been activated.
252 */
214 if (match->chiptype == CHIP_I810) {
215 u_int8_t smram;
216
253 switch (match->chiptype) {
254 case CHIP_I810:
217 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
255 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
218 if ((smram & AGP_I810_SMRAM_GMS)
219 == AGP_I810_SMRAM_GMS_DISABLED) {
256 if ((smram & AGP_I810_SMRAM_GMS) ==
257 AGP_I810_SMRAM_GMS_DISABLED) {
220 if (bootverbose)
221 printf("I810: disabled, not probing\n");
222 return ENXIO;
223 }
258 if (bootverbose)
259 printf("I810: disabled, not probing\n");
260 return ENXIO;
261 }
224 } else if (match->chiptype == CHIP_I830 ||
225 match->chiptype == CHIP_I855) {
226 unsigned int gcc1;
227
262 break;
263 case CHIP_I830:
264 case CHIP_I855:
228 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
229 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
230 AGP_I830_GCC1_DEV2_DISABLED) {
231 if (bootverbose)
232 printf("I830: disabled, not probing\n");
233 return ENXIO;
234 }
265 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
266 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
267 AGP_I830_GCC1_DEV2_DISABLED) {
268 if (bootverbose)
269 printf("I830: disabled, not probing\n");
270 return ENXIO;
271 }
235 } else if (match->chiptype == CHIP_I915) {
236 unsigned int gcc1;
237
238 gcc1 = pci_read_config(bdev, AGP_I915_DEVEN, 4);
239 if ((gcc1 & AGP_I915_DEVEN_D2F0) ==
272 break;
273 case CHIP_I915:
274 case CHIP_I965:
275 case CHIP_G33:
276 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
277 if ((deven & AGP_I915_DEVEN_D2F0) ==
240 AGP_I915_DEVEN_D2F0_DISABLED) {
241 if (bootverbose)
242 printf("I915: disabled, not probing\n");
243 return ENXIO;
244 }
278 AGP_I915_DEVEN_D2F0_DISABLED) {
279 if (bootverbose)
280 printf("I915: disabled, not probing\n");
281 return ENXIO;
282 }
283 break;
245 }
246
247 if (match->devid == 0x35828086) {
248 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
249 case AGP_I855_GME:
250 device_set_desc(dev,
251 "Intel 82855GME (855GME GMCH) SVGA controller");
252 break;

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269 }
270 } else {
271 device_set_desc(dev, match->name);
272 }
273
274 return BUS_PROBE_DEFAULT;
275}
276
284 }
285
286 if (match->devid == 0x35828086) {
287 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
288 case AGP_I855_GME:
289 device_set_desc(dev,
290 "Intel 82855GME (855GME GMCH) SVGA controller");
291 break;

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308 }
309 } else {
310 device_set_desc(dev, match->name);
311 }
312
313 return BUS_PROBE_DEFAULT;
314}
315
316static void
317agp_i810_dump_regs(device_t dev)
318{
319 struct agp_i810_softc *sc = device_get_softc(dev);
320
321 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
322 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
323
324 switch (sc->chiptype) {
325 case CHIP_I810:
326 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
327 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
328 break;
329 case CHIP_I830:
330 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
331 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
332 break;
333 case CHIP_I855:
334 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
335 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
336 break;
337 case CHIP_I915:
338 case CHIP_I965:
339 case CHIP_G33:
340 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
341 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
342 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
343 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
344 break;
345 }
346 device_printf(dev, "Aperture resource size: %d bytes\n",
347 AGP_GET_APERTURE(dev));
348}
349
277static int
278agp_i810_attach(device_t dev)
279{
280 struct agp_i810_softc *sc = device_get_softc(dev);
281 struct agp_gatt *gatt;
282 const struct agp_i810_match *match;
350static int
351agp_i810_attach(device_t dev)
352{
353 struct agp_i810_softc *sc = device_get_softc(dev);
354 struct agp_gatt *gatt;
355 const struct agp_i810_match *match;
283 int error, rid;
356 int error;
284
285 sc->bdev = agp_i810_find_bridge(dev);
286 if (!sc->bdev)
287 return ENOENT;
288
357
358 sc->bdev = agp_i810_find_bridge(dev);
359 if (!sc->bdev)
360 return ENOENT;
361
362 match = agp_i810_match(dev);
363 sc->chiptype = match->chiptype;
364
365 switch (sc->chiptype) {
366 case CHIP_I810:
367 case CHIP_I830:
368 case CHIP_I855:
369 sc->sc_res_spec = agp_i810_res_spec;
370 agp_set_aperture_resource(dev, AGP_APBASE);
371 break;
372 case CHIP_I915:
373 case CHIP_G33:
374 sc->sc_res_spec = agp_i915_res_spec;
375 agp_set_aperture_resource(dev, AGP_I915_GMADR);
376 break;
377 case CHIP_I965:
378 sc->sc_res_spec = agp_i965_res_spec;
379 agp_set_aperture_resource(dev, AGP_I915_GMADR);
380 break;
381 }
382
289 error = agp_generic_attach(dev);
290 if (error)
291 return error;
292
383 error = agp_generic_attach(dev);
384 if (error)
385 return error;
386
293 match = agp_i810_match(dev);
294 sc->chiptype = match->chiptype;
387 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
388 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
389 {
390 device_printf(dev, "agp_i810.c does not support physical "
391 "memory above 4GB.\n");
392 return ENOENT;
393 }
295
394
296 /* Same for i810 and i830 */
297 if (sc->chiptype == CHIP_I915)
298 rid = AGP_I915_MMADR;
299 else
300 rid = AGP_I810_MMADR;
301
302 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
303 RF_ACTIVE);
304 if (!sc->regs) {
395 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
305 agp_generic_detach(dev);
306 return ENODEV;
307 }
396 agp_generic_detach(dev);
397 return ENODEV;
398 }
308 sc->bst = rman_get_bustag(sc->regs);
309 sc->bsh = rman_get_bushandle(sc->regs);
310
399
311 if (sc->chiptype == CHIP_I915) {
312 rid = AGP_I915_GTTADR;
313 sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
314 RF_ACTIVE);
315 if (!sc->gtt) {
316 bus_release_resource(dev, SYS_RES_MEMORY,
317 AGP_I915_MMADR, sc->regs);
318 agp_generic_detach(dev);
319 return ENODEV;
320 }
321 sc->gtt_bst = rman_get_bustag(sc->gtt);
322 sc->gtt_bsh = rman_get_bushandle(sc->gtt);
323
324 /* While agp_generic_attach allocates the AGP_APBASE resource
325 * to try to reserve the aperture, on the 915 the aperture
326 * isn't in PCIR_BAR(0), it's in PCIR_BAR(2), so it allocated
327 * the registers that we just mapped anyway. So, allocate the
328 * aperture here, which also gives us easy access to it for the
329 * agp_i810_get_aperture().
330 */
331 rid = AGP_I915_GMADR;
332 sc->gm = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0);
333 if (sc->gm == NULL) {
334 bus_release_resource(dev, SYS_RES_MEMORY,
335 AGP_I915_MMADR, sc->regs);
336 bus_release_resource(dev, SYS_RES_MEMORY,
337 AGP_I915_GTTADR, sc->regs);
338 agp_generic_detach(dev);
339 return ENODEV;
340 }
341 }
342
343 sc->initial_aperture = AGP_GET_APERTURE(dev);
344
345 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
346 if (!gatt) {
400 sc->initial_aperture = AGP_GET_APERTURE(dev);
401
402 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
403 if (!gatt) {
404 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
347 agp_generic_detach(dev);
348 return ENOMEM;
349 }
350 sc->gatt = gatt;
351
352 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
353
354 if ( sc->chiptype == CHIP_I810 ) {
355 /* Some i810s have on-chip memory called dcache */
405 agp_generic_detach(dev);
406 return ENOMEM;
407 }
408 sc->gatt = gatt;
409
410 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
411
412 if ( sc->chiptype == CHIP_I810 ) {
413 /* Some i810s have on-chip memory called dcache */
356 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
414 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
415 AGP_I810_DRT_POPULATED)
357 sc->dcache_size = 4 * 1024 * 1024;
358 else
359 sc->dcache_size = 0;
360
361 /* According to the specs the gatt on the i810 must be 64k */
362 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
363 0, ~0, PAGE_SIZE, 0);
364 if (!gatt->ag_virtual) {
365 if (bootverbose)
366 device_printf(dev, "contiguous allocation failed\n");
416 sc->dcache_size = 4 * 1024 * 1024;
417 else
418 sc->dcache_size = 0;
419
420 /* According to the specs the gatt on the i810 must be 64k */
421 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
422 0, ~0, PAGE_SIZE, 0);
423 if (!gatt->ag_virtual) {
424 if (bootverbose)
425 device_printf(dev, "contiguous allocation failed\n");
426 bus_release_resources(dev, sc->sc_res_spec,
427 sc->sc_res);
367 free(gatt, M_AGP);
368 agp_generic_detach(dev);
369 return ENOMEM;
370 }
371 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
372
373 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
374 agp_flush_cache();
375 /* Install the GATT. */
428 free(gatt, M_AGP);
429 agp_generic_detach(dev);
430 return ENOMEM;
431 }
432 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
433
434 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
435 agp_flush_cache();
436 /* Install the GATT. */
376 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1);
437 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
438 gatt->ag_physical | 1);
377 } else if ( sc->chiptype == CHIP_I830 ) {
378 /* The i830 automatically initializes the 128k gatt on boot. */
379 unsigned int gcc1, pgtblctl;
380
381 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
382 switch (gcc1 & AGP_I830_GCC1_GMS) {
383 case AGP_I830_GCC1_GMS_STOLEN_512:
384 sc->stolen = (512 - 132) * 1024 / 4096;
385 break;
386 case AGP_I830_GCC1_GMS_STOLEN_1024:
387 sc->stolen = (1024 - 132) * 1024 / 4096;
388 break;
389 case AGP_I830_GCC1_GMS_STOLEN_8192:
390 sc->stolen = (8192 - 132) * 1024 / 4096;
391 break;
392 default:
393 sc->stolen = 0;
394 device_printf(dev, "unknown memory configuration, disabling\n");
439 } else if ( sc->chiptype == CHIP_I830 ) {
440 /* The i830 automatically initializes the 128k gatt on boot. */
441 unsigned int gcc1, pgtblctl;
442
443 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
444 switch (gcc1 & AGP_I830_GCC1_GMS) {
445 case AGP_I830_GCC1_GMS_STOLEN_512:
446 sc->stolen = (512 - 132) * 1024 / 4096;
447 break;
448 case AGP_I830_GCC1_GMS_STOLEN_1024:
449 sc->stolen = (1024 - 132) * 1024 / 4096;
450 break;
451 case AGP_I830_GCC1_GMS_STOLEN_8192:
452 sc->stolen = (8192 - 132) * 1024 / 4096;
453 break;
454 default:
455 sc->stolen = 0;
456 device_printf(dev, "unknown memory configuration, disabling\n");
457 bus_release_resources(dev, sc->sc_res_spec,
458 sc->sc_res);
459 free(gatt, M_AGP);
395 agp_generic_detach(dev);
396 return EINVAL;
397 }
460 agp_generic_detach(dev);
461 return EINVAL;
462 }
398 if (sc->stolen > 0)
399 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
400 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
463 if (sc->stolen > 0) {
464 device_printf(dev, "detected %dk stolen memory\n",
465 sc->stolen * 4);
466 }
467 device_printf(dev, "aperture size is %dM\n",
468 sc->initial_aperture / 1024 / 1024);
401
402 /* GATT address is already in there, make sure it's enabled */
469
470 /* GATT address is already in there, make sure it's enabled */
403 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
471 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
404 pgtblctl |= 1;
472 pgtblctl |= 1;
405 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
473 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
406
407 gatt->ag_physical = pgtblctl & ~1;
474
475 gatt->ag_physical = pgtblctl & ~1;
408 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) { /* CHIP_I855 */
409 unsigned int gcc1, pgtblctl, stolen;
476 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
477 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) {
478 unsigned int gcc1, pgtblctl, stolen, gtt_size;
410
411 /* Stolen memory is set up at the beginning of the aperture by
479
480 /* Stolen memory is set up at the beginning of the aperture by
412 * the BIOS, consisting of the GATT followed by 4kb for the BIOS
413 * display.
481 * the BIOS, consisting of the GATT followed by 4kb for the
482 * BIOS display.
414 */
483 */
415 if (sc->chiptype == CHIP_I855)
416 stolen = 132;
417 else
418 stolen = 260;
419
420 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
421 switch (gcc1 & AGP_I855_GCC1_GMS) {
422 case AGP_I855_GCC1_GMS_STOLEN_1M:
423 sc->stolen = (1024 - stolen) * 1024 / 4096;
484 switch (sc->chiptype) {
485 case CHIP_I855:
486 gtt_size = 128;
487 break;
488 case CHIP_I915:
489 gtt_size = 256;
490 break;
491 case CHIP_I965:
492 case CHIP_G33:
493 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
494 AGP_I810_PGTBL_SIZE_MASK) {
495 case AGP_I810_PGTBL_SIZE_128KB:
496 gtt_size = 128;
424 break;
497 break;
425 case AGP_I855_GCC1_GMS_STOLEN_4M:
426 sc->stolen = (4096 - stolen) * 1024 / 4096;
498 case AGP_I810_PGTBL_SIZE_256KB:
499 gtt_size = 256;
427 break;
500 break;
428 case AGP_I855_GCC1_GMS_STOLEN_8M:
429 sc->stolen = (8192 - stolen) * 1024 / 4096;
501 case AGP_I810_PGTBL_SIZE_512KB:
502 gtt_size = 512;
430 break;
503 break;
431 case AGP_I855_GCC1_GMS_STOLEN_16M:
432 sc->stolen = (16384 - stolen) * 1024 / 4096;
433 break;
434 case AGP_I855_GCC1_GMS_STOLEN_32M:
435 sc->stolen = (32768 - stolen) * 1024 / 4096;
436 break;
437 case AGP_I915_GCC1_GMS_STOLEN_48M:
438 sc->stolen = (49152 - stolen) * 1024 / 4096;
439 break;
440 case AGP_I915_GCC1_GMS_STOLEN_64M:
441 sc->stolen = (65536 - stolen) * 1024 / 4096;
442 break;
443 default:
504 default:
444 sc->stolen = 0;
445 device_printf(dev, "unknown memory configuration, disabling\n");
505 device_printf(dev, "Bad PGTBL size\n");
506 bus_release_resources(dev, sc->sc_res_spec,
507 sc->sc_res);
508 free(gatt, M_AGP);
446 agp_generic_detach(dev);
447 return EINVAL;
509 agp_generic_detach(dev);
510 return EINVAL;
511 }
512 break;
513 default:
514 device_printf(dev, "Bad chiptype\n");
515 bus_release_resources(dev, sc->sc_res_spec,
516 sc->sc_res);
517 free(gatt, M_AGP);
518 agp_generic_detach(dev);
519 return EINVAL;
448 }
520 }
521
522 /* GCC1 is called MGGC on i915+ */
523 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
524 switch (gcc1 & AGP_I855_GCC1_GMS) {
525 case AGP_I855_GCC1_GMS_STOLEN_1M:
526 stolen = 1024;
527 break;
528 case AGP_I855_GCC1_GMS_STOLEN_4M:
529 stolen = 4096;
530 break;
531 case AGP_I855_GCC1_GMS_STOLEN_8M:
532 stolen = 8192;
533 break;
534 case AGP_I855_GCC1_GMS_STOLEN_16M:
535 stolen = 16384;
536 break;
537 case AGP_I855_GCC1_GMS_STOLEN_32M:
538 stolen = 32768;
539 break;
540 case AGP_I915_GCC1_GMS_STOLEN_48M:
541 stolen = 49152;
542 break;
543 case AGP_I915_GCC1_GMS_STOLEN_64M:
544 stolen = 65536;
545 break;
546 case AGP_G33_GCC1_GMS_STOLEN_128M:
547 stolen = 128 * 1024;
548 break;
549 case AGP_G33_GCC1_GMS_STOLEN_256M:
550 stolen = 256 * 1024;
551 break;
552 default:
553 device_printf(dev, "unknown memory configuration, "
554 "disabling\n");
555 bus_release_resources(dev, sc->sc_res_spec,
556 sc->sc_res);
557 free(gatt, M_AGP);
558 agp_generic_detach(dev);
559 return EINVAL;
560 }
561 sc->stolen = (stolen - gtt_size - 4) * 1024 / 4096;
449 if (sc->stolen > 0)
450 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
451 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
452
453 /* GATT address is already in there, make sure it's enabled */
562 if (sc->stolen > 0)
563 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
564 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
565
566 /* GATT address is already in there, make sure it's enabled */
454 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
567 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
455 pgtblctl |= 1;
568 pgtblctl |= 1;
456 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
569 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
457
458 gatt->ag_physical = pgtblctl & ~1;
459 }
460
570
571 gatt->ag_physical = pgtblctl & ~1;
572 }
573
574 if (0)
575 agp_i810_dump_regs(dev);
576
461 return 0;
462}
463
464static int
465agp_i810_detach(device_t dev)
466{
467 struct agp_i810_softc *sc = device_get_softc(dev);
468 int error;
469
470 error = agp_generic_detach(dev);
471 if (error)
472 return error;
473
474 /* Clear the GATT base. */
475 if ( sc->chiptype == CHIP_I810 ) {
577 return 0;
578}
579
580static int
581agp_i810_detach(device_t dev)
582{
583 struct agp_i810_softc *sc = device_get_softc(dev);
584 int error;
585
586 error = agp_generic_detach(dev);
587 if (error)
588 return error;
589
590 /* Clear the GATT base. */
591 if ( sc->chiptype == CHIP_I810 ) {
476 WRITE4(AGP_I810_PGTBL_CTL, 0);
592 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
477 } else {
478 unsigned int pgtblctl;
593 } else {
594 unsigned int pgtblctl;
479 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
595 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
480 pgtblctl &= ~1;
596 pgtblctl &= ~1;
481 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
597 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
482 }
483
484 /* Put the aperture back the way it started. */
485 AGP_SET_APERTURE(dev, sc->initial_aperture);
486
487 if ( sc->chiptype == CHIP_I810 ) {
488 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
489 }
490 free(sc->gatt, M_AGP);
491
598 }
599
600 /* Put the aperture back the way it started. */
601 AGP_SET_APERTURE(dev, sc->initial_aperture);
602
603 if ( sc->chiptype == CHIP_I810 ) {
604 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
605 }
606 free(sc->gatt, M_AGP);
607
492 if (sc->chiptype == CHIP_I915) {
493 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GMADR,
494 sc->gm);
495 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GTTADR,
496 sc->gtt);
497 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR,
498 sc->regs);
499 } else {
500 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR,
501 sc->regs);
502 }
608 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
503
504 return 0;
505}
506
609
610 return 0;
611}
612
507static u_int32_t
508agp_i810_get_aperture(device_t dev)
509{
510 struct agp_i810_softc *sc = device_get_softc(dev);
511 uint32_t temp;
512 u_int16_t miscc;
513
514 switch (sc->chiptype) {
515 case CHIP_I810:
516 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
517 if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
518 return 32 * 1024 * 1024;
519 else
520 return 64 * 1024 * 1024;
521 case CHIP_I830:
522 temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
523 if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
524 return 64 * 1024 * 1024;
525 else
526 return 128 * 1024 * 1024;
527 case CHIP_I855:
528 return 128 * 1024 * 1024;
529 case CHIP_I915:
530 /* The documentation states that AGP_I915_MSAC should have bit
531 * 1 set if the aperture is 128MB instead of 256. However,
532 * that bit appears to not get set, so we instead use the
533 * aperture resource size, which should always be correct.
534 */
535 return rman_get_size(sc->gm);
536 }
537
538 return 0;
539}
540
613/**
614 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
615 * while returning failure on later chipsets when an actual change is
616 * requested.
617 *
618 * This whole function is likely bogus, as the kernel would probably need to
619 * reconfigure the placement of the AGP aperture if a larger size is requested,
620 * which doesn't happen currently.
621 */
541static int
542agp_i810_set_aperture(device_t dev, u_int32_t aperture)
543{
544 struct agp_i810_softc *sc = device_get_softc(dev);
545 u_int16_t miscc, gcc1;
622static int
623agp_i810_set_aperture(device_t dev, u_int32_t aperture)
624{
625 struct agp_i810_softc *sc = device_get_softc(dev);
626 u_int16_t miscc, gcc1;
546 u_int32_t temp;
547
548 switch (sc->chiptype) {
549 case CHIP_I810:
550 /*
551 * Double check for sanity.
552 */
553 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
554 device_printf(dev, "bad aperture size %d\n", aperture);

--- 20 unchanged lines hidden (view full) ---

575 if (aperture == 64 * 1024 * 1024)
576 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
577 else
578 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
579
580 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
581 break;
582 case CHIP_I855:
627
628 switch (sc->chiptype) {
629 case CHIP_I810:
630 /*
631 * Double check for sanity.
632 */
633 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
634 device_printf(dev, "bad aperture size %d\n", aperture);

--- 20 unchanged lines hidden (view full) ---

655 if (aperture == 64 * 1024 * 1024)
656 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
657 else
658 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
659
660 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
661 break;
662 case CHIP_I855:
583 if (aperture != 128 * 1024 * 1024) {
584 device_printf(dev, "bad aperture size %d\n", aperture);
585 return EINVAL;
586 }
587 break;
588 case CHIP_I915:
663 case CHIP_I915:
589 temp = pci_read_config(dev, AGP_I915_MSAC, 1);
590 temp &= ~AGP_I915_MSAC_GMASIZE;
664 case CHIP_I965:
665 case CHIP_G33:
666 return agp_generic_set_aperture(dev, aperture);
667 }
591
668
592 switch (aperture) {
593 case 128 * 1024 * 1024:
594 temp |= AGP_I915_MSAC_GMASIZE_128;
595 break;
596 case 256 * 1024 * 1024:
597 temp |= AGP_I915_MSAC_GMASIZE_256;
598 break;
599 default:
600 device_printf(dev, "bad aperture size %d\n", aperture);
601 return EINVAL;
602 }
669 return 0;
670}
603
671
604 pci_write_config(dev, AGP_I915_MSAC, temp, 1);
605 break;
672/**
673 * Writes a GTT entry mapping the page at the given offset from the beginning
674 * of the aperture to the given physical address.
675 */
676static void
677agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
678 int enabled)
679{
680 struct agp_i810_softc *sc = device_get_softc(dev);
681 u_int32_t pte;
682
683 pte = (u_int32_t)physical | 1;
684 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) {
685 pte |= (physical & 0x0000000f00000000ull) >> 28;
686 } else {
687 /* If we do actually have memory above 4GB on an older system,
688 * crash cleanly rather than scribble on system memory,
689 * so we know we need to fix it.
690 */
691 KASSERT((pte & 0x0000000f00000000ull) == 0,
692 (">4GB physical address in agp"));
606 }
607
693 }
694
608 return 0;
695 switch (sc->chiptype) {
696 case CHIP_I810:
697 case CHIP_I830:
698 case CHIP_I855:
699 bus_write_4(sc->sc_res[0],
700 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
701 break;
702 case CHIP_I915:
703 case CHIP_G33:
704 bus_write_4(sc->sc_res[1],
705 (offset >> AGP_PAGE_SHIFT) * 4, pte);
706 break;
707 case CHIP_I965:
708 bus_write_4(sc->sc_res[0],
709 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
710 break;
711 }
609}
610
611static int
612agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
613{
614 struct agp_i810_softc *sc = device_get_softc(dev);
615
616 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
617 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
618 return EINVAL;
619 }
620
621 if ( sc->chiptype != CHIP_I810 ) {
622 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
623 device_printf(dev, "trying to bind into stolen memory");
624 return EINVAL;
625 }
626 }
627
712}
713
714static int
715agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
716{
717 struct agp_i810_softc *sc = device_get_softc(dev);
718
719 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
720 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
721 return EINVAL;
722 }
723
724 if ( sc->chiptype != CHIP_I810 ) {
725 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
726 device_printf(dev, "trying to bind into stolen memory");
727 return EINVAL;
728 }
729 }
730
628 if (sc->chiptype == CHIP_I915) {
629 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, physical | 1);
630 } else {
631 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1);
632 }
731 agp_i810_write_gtt_entry(dev, offset, physical, 1);
633
634 return 0;
635}
636
637static int
638agp_i810_unbind_page(device_t dev, int offset)
639{
640 struct agp_i810_softc *sc = device_get_softc(dev);
641
642 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
643 return EINVAL;
644
645 if ( sc->chiptype != CHIP_I810 ) {
646 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
647 device_printf(dev, "trying to unbind from stolen memory");
648 return EINVAL;
649 }
650 }
651
732
733 return 0;
734}
735
736static int
737agp_i810_unbind_page(device_t dev, int offset)
738{
739 struct agp_i810_softc *sc = device_get_softc(dev);
740
741 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
742 return EINVAL;
743
744 if ( sc->chiptype != CHIP_I810 ) {
745 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
746 device_printf(dev, "trying to unbind from stolen memory");
747 return EINVAL;
748 }
749 }
750
652 if (sc->chiptype == CHIP_I915) {
653 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, 0);
654 } else {
655 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0);
656 }
657
751 agp_i810_write_gtt_entry(dev, offset, 0, 0);
752
658 return 0;
659}
660
661/*
662 * Writing via memory mapped registers already flushes all TLBs.
663 */
664static void
665agp_i810_flush_tlb(device_t dev)

--- 141 unchanged lines hidden (view full) ---

807 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
808 mtx_lock(&sc->agp.as_lock);
809 if (mem->am_is_bound) {
810 mtx_unlock(&sc->agp.as_lock);
811 return EINVAL;
812 }
813 /* The memory's already wired down, just stick it in the GTT. */
814 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
753 return 0;
754}
755
756/*
757 * Writing via memory mapped registers already flushes all TLBs.
758 */
759static void
760agp_i810_flush_tlb(device_t dev)

--- 141 unchanged lines hidden (view full) ---

902 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
903 mtx_lock(&sc->agp.as_lock);
904 if (mem->am_is_bound) {
905 mtx_unlock(&sc->agp.as_lock);
906 return EINVAL;
907 }
908 /* The memory's already wired down, just stick it in the GTT. */
909 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
815 u_int32_t physical = mem->am_physical + i;
816
817 if (sc->chiptype == CHIP_I915) {
818 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4,
819 physical | 1);
820 } else {
821 WRITE4(AGP_I810_GTT +
822 ((offset + i) >> AGP_PAGE_SHIFT) * 4,
823 physical | 1);
824 }
910 agp_i810_write_gtt_entry(dev, offset + i,
911 mem->am_physical + i, 1);
825 }
826 agp_flush_cache();
827 mem->am_offset = offset;
828 mem->am_is_bound = 1;
829 mtx_unlock(&sc->agp.as_lock);
830 return 0;
831 }
832
833 if (mem->am_type != 1)
834 return agp_generic_bind_memory(dev, mem, offset);
835
836 if ( sc->chiptype != CHIP_I810 )
837 return EINVAL;
838
839 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
912 }
913 agp_flush_cache();
914 mem->am_offset = offset;
915 mem->am_is_bound = 1;
916 mtx_unlock(&sc->agp.as_lock);
917 return 0;
918 }
919
920 if (mem->am_type != 1)
921 return agp_generic_bind_memory(dev, mem, offset);
922
923 if ( sc->chiptype != CHIP_I810 )
924 return EINVAL;
925
926 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
840 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4,
841 i | 3);
927 bus_write_4(sc->sc_res[0],
928 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
842 }
843
844 return 0;
845}
846
847static int
848agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
849{
850 struct agp_i810_softc *sc = device_get_softc(dev);
851 vm_offset_t i;
852
853 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
854 mtx_lock(&sc->agp.as_lock);
855 if (!mem->am_is_bound) {
856 mtx_unlock(&sc->agp.as_lock);
857 return EINVAL;
858 }
859
860 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
929 }
930
931 return 0;
932}
933
934static int
935agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
936{
937 struct agp_i810_softc *sc = device_get_softc(dev);
938 vm_offset_t i;
939
940 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
941 mtx_lock(&sc->agp.as_lock);
942 if (!mem->am_is_bound) {
943 mtx_unlock(&sc->agp.as_lock);
944 return EINVAL;
945 }
946
947 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
861 vm_offset_t offset = mem->am_offset;
862
863 if (sc->chiptype == CHIP_I915) {
864 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4,
865 0);
866 } else {
867 WRITE4(AGP_I810_GTT +
868 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 0);
869 }
948 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
949 0, 0);
870 }
871 agp_flush_cache();
872 mem->am_is_bound = 0;
873 mtx_unlock(&sc->agp.as_lock);
874 return 0;
875 }
876
877 if (mem->am_type != 1)
878 return agp_generic_unbind_memory(dev, mem);
879
880 if ( sc->chiptype != CHIP_I810 )
881 return EINVAL;
882
950 }
951 agp_flush_cache();
952 mem->am_is_bound = 0;
953 mtx_unlock(&sc->agp.as_lock);
954 return 0;
955 }
956
957 if (mem->am_type != 1)
958 return agp_generic_unbind_memory(dev, mem);
959
960 if ( sc->chiptype != CHIP_I810 )
961 return EINVAL;
962
883 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
884 WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
963 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
964 bus_write_4(sc->sc_res[0],
965 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
966 }
885
886 return 0;
887}
888
889static device_method_t agp_i810_methods[] = {
890 /* Device interface */
891 DEVMETHOD(device_identify, agp_i810_identify),
892 DEVMETHOD(device_probe, agp_i810_probe),
893 DEVMETHOD(device_attach, agp_i810_attach),
894 DEVMETHOD(device_detach, agp_i810_detach),
895
896 /* AGP interface */
967
968 return 0;
969}
970
971static device_method_t agp_i810_methods[] = {
972 /* Device interface */
973 DEVMETHOD(device_identify, agp_i810_identify),
974 DEVMETHOD(device_probe, agp_i810_probe),
975 DEVMETHOD(device_attach, agp_i810_attach),
976 DEVMETHOD(device_detach, agp_i810_detach),
977
978 /* AGP interface */
897 DEVMETHOD(agp_get_aperture, agp_i810_get_aperture),
979 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
898 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
899 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
900 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
901 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
902 DEVMETHOD(agp_enable, agp_i810_enable),
903 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
904 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
905 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),

--- 16 unchanged lines hidden --- 		980 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
981 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
982 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
983 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
984 DEVMETHOD(agp_enable, agp_i810_enable),
985 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
986 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
987 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),

--- 16 unchanged lines hidden ---