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cvmx-pip.h (210286) cvmx-pip.h (215990)
1/***********************license start***************
1/***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
3 * reserved.
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
3 * reserved.
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4 *
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10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
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12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
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24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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36 *
37 ***********************license end**************************************/
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
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17
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
21 * permission.
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22
23 * This Software, including technical data, may be subject to U.S. export control
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25 * regulations, and may be subject to export or import regulations in other
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40
27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
41
42
39
40
43
44/**
45 * @file
46 *
47 * Interface to the hardware Packet Input Processing unit.
48 *
41/**
42 * @file
43 *
44 * Interface to the hardware Packet Input Processing unit.
45 *
49 * <hr>$Revision: 41586 $<hr>
46 * <hr>$Revision: 49504 $<hr>
50 */
51
52
53#ifndef __CVMX_PIP_H__
54#define __CVMX_PIP_H__
55
56#include "cvmx-wqe.h"
57#include "cvmx-fpa.h"
47 */
48
49
50#ifndef __CVMX_PIP_H__
51#define __CVMX_PIP_H__
52
53#include "cvmx-wqe.h"
54#include "cvmx-fpa.h"
55#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
56#include "cvmx-pip-defs.h"
57#else
58#ifndef CVMX_DONT_INCLUDE_CONFIG
59#include "executive-config.h"
60#endif
58#ifndef CVMX_DONT_INCLUDE_CONFIG
59#include "executive-config.h"
60#endif
61#endif
61
62
63
62#ifdef __cplusplus
63extern "C" {
64#endif
65
64#ifdef __cplusplus
65extern "C" {
66#endif
67
66#define CVMX_PIP_NUM_INPUT_PORTS 40
67#define CVMX_PIP_NUM_WATCHERS 4
68#define CVMX_PIP_NUM_INPUT_PORTS 44
68
69
69
70
71
72
73
74
75//
76// Encodes the different error and exception codes
77//
70/*
71 * Encodes the different error and exception codes
72 */
78typedef enum
79{
80 CVMX_PIP_L4_NO_ERR = 0ull,
73typedef enum
74{
75 CVMX_PIP_L4_NO_ERR = 0ull,
81 // 1 = TCP (UDP) packet not long enough to cover TCP (UDP) header
76 /* 1 = TCP (UDP) packet not long enough to cover TCP (UDP) header */
82 CVMX_PIP_L4_MAL_ERR = 1ull,
77 CVMX_PIP_L4_MAL_ERR = 1ull,
83 // 2 = TCP/UDP checksum failure
78 /* 2 = TCP/UDP checksum failure */
84 CVMX_PIP_CHK_ERR = 2ull,
79 CVMX_PIP_CHK_ERR = 2ull,
85 // 3 = TCP/UDP length check (TCP/UDP length does not match IP length)
80 /* 3 = TCP/UDP length check (TCP/UDP length does not match IP length) */
86 CVMX_PIP_L4_LENGTH_ERR = 3ull,
81 CVMX_PIP_L4_LENGTH_ERR = 3ull,
87 // 4 = illegal TCP/UDP port (either source or dest port is zero)
82 /* 4 = illegal TCP/UDP port (either source or dest port is zero) */
88 CVMX_PIP_BAD_PRT_ERR = 4ull,
83 CVMX_PIP_BAD_PRT_ERR = 4ull,
89 // 8 = TCP flags = FIN only
84 /* 8 = TCP flags = FIN only */
90 CVMX_PIP_TCP_FLG8_ERR = 8ull,
85 CVMX_PIP_TCP_FLG8_ERR = 8ull,
91 // 9 = TCP flags = 0
86 /* 9 = TCP flags = 0 */
92 CVMX_PIP_TCP_FLG9_ERR = 9ull,
87 CVMX_PIP_TCP_FLG9_ERR = 9ull,
93 // 10 = TCP flags = FIN+RST+*
88 /* 10 = TCP flags = FIN+RST+* */
94 CVMX_PIP_TCP_FLG10_ERR = 10ull,
89 CVMX_PIP_TCP_FLG10_ERR = 10ull,
95 // 11 = TCP flags = SYN+URG+*
90 /* 11 = TCP flags = SYN+URG+* */
96 CVMX_PIP_TCP_FLG11_ERR = 11ull,
91 CVMX_PIP_TCP_FLG11_ERR = 11ull,
97 // 12 = TCP flags = SYN+RST+*
92 /* 12 = TCP flags = SYN+RST+* */
98 CVMX_PIP_TCP_FLG12_ERR = 12ull,
93 CVMX_PIP_TCP_FLG12_ERR = 12ull,
99 // 13 = TCP flags = SYN+FIN+*
94 /* 13 = TCP flags = SYN+FIN+* */
100 CVMX_PIP_TCP_FLG13_ERR = 13ull
101} cvmx_pip_l4_err_t;
102
103typedef enum
104{
105
106 CVMX_PIP_IP_NO_ERR = 0ull,
95 CVMX_PIP_TCP_FLG13_ERR = 13ull
96} cvmx_pip_l4_err_t;
97
98typedef enum
99{
100
101 CVMX_PIP_IP_NO_ERR = 0ull,
107 // 1 = not IPv4 or IPv6
102 /* 1 = not IPv4 or IPv6 */
108 CVMX_PIP_NOT_IP = 1ull,
103 CVMX_PIP_NOT_IP = 1ull,
109 // 2 = IPv4 header checksum violation
104 /* 2 = IPv4 header checksum violation */
110 CVMX_PIP_IPV4_HDR_CHK = 2ull,
105 CVMX_PIP_IPV4_HDR_CHK = 2ull,
111 // 3 = malformed (packet not long enough to cover IP hdr)
106 /* 3 = malformed (packet not long enough to cover IP hdr) */
112 CVMX_PIP_IP_MAL_HDR = 3ull,
107 CVMX_PIP_IP_MAL_HDR = 3ull,
113 // 4 = malformed (packet not long enough to cover len in IP hdr)
108 /* 4 = malformed (packet not long enough to cover len in IP hdr) */
114 CVMX_PIP_IP_MAL_PKT = 4ull,
109 CVMX_PIP_IP_MAL_PKT = 4ull,
115 // 5 = TTL / hop count equal zero
110 /* 5 = TTL / hop count equal zero */
116 CVMX_PIP_TTL_HOP = 5ull,
111 CVMX_PIP_TTL_HOP = 5ull,
117 // 6 = IPv4 options / IPv6 early extension headers
112 /* 6 = IPv4 options / IPv6 early extension headers */
118 CVMX_PIP_OPTS = 6ull
119} cvmx_pip_ip_exc_t;
120
121
122/**
123 * NOTES
124 * late collision (data received before collision)
125 * late collisions cannot be detected by the receiver
126 * they would appear as JAM bits which would appear as bad FCS
127 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
128 */
129typedef enum
130{
131 /**
132 * No error
133 */
134 CVMX_PIP_RX_NO_ERR = 0ull,
135
113 CVMX_PIP_OPTS = 6ull
114} cvmx_pip_ip_exc_t;
115
116
117/**
118 * NOTES
119 * late collision (data received before collision)
120 * late collisions cannot be detected by the receiver
121 * they would appear as JAM bits which would appear as bad FCS
122 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
123 */
124typedef enum
125{
126 /**
127 * No error
128 */
129 CVMX_PIP_RX_NO_ERR = 0ull,
130
136 CVMX_PIP_PARTIAL_ERR = 1ull, // RGM+SPI 1 = partially received packet (buffering/bandwidth not adequate)
137 CVMX_PIP_JABBER_ERR = 2ull, // RGM+SPI 2 = receive packet too large and truncated
138 CVMX_PIP_OVER_FCS_ERR = 3ull, // RGM 3 = max frame error (pkt len > max frame len) (with FCS error)
139 CVMX_PIP_OVER_ERR = 4ull, // RGM+SPI 4 = max frame error (pkt len > max frame len)
140 CVMX_PIP_ALIGN_ERR = 5ull, // RGM 5 = nibble error (data not byte multiple - 100M and 10M only)
141 CVMX_PIP_UNDER_FCS_ERR = 6ull, // RGM 6 = min frame error (pkt len < min frame len) (with FCS error)
142 CVMX_PIP_GMX_FCS_ERR = 7ull, // RGM 7 = FCS error
143 CVMX_PIP_UNDER_ERR = 8ull, // RGM+SPI 8 = min frame error (pkt len < min frame len)
144 CVMX_PIP_EXTEND_ERR = 9ull, // RGM 9 = Frame carrier extend error
145 CVMX_PIP_LENGTH_ERR = 10ull, // RGM 10 = length mismatch (len did not match len in L2 length/type)
146 CVMX_PIP_DAT_ERR = 11ull, // RGM 11 = Frame error (some or all data bits marked err)
147 CVMX_PIP_DIP_ERR = 11ull, // SPI 11 = DIP4 error
148 CVMX_PIP_SKIP_ERR = 12ull, // RGM 12 = packet was not large enough to pass the skipper - no inspection could occur
149 CVMX_PIP_NIBBLE_ERR = 13ull, // RGM 13 = studder error (data not repeated - 100M and 10M only)
150 CVMX_PIP_PIP_FCS = 16L, // RGM+SPI 16 = FCS error
151 CVMX_PIP_PIP_SKIP_ERR = 17L, // RGM+SPI+PCI 17 = packet was not large enough to pass the skipper - no inspection could occur
152 CVMX_PIP_PIP_L2_MAL_HDR= 18L // RGM+SPI+PCI 18 = malformed l2 (packet not long enough to cover L2 hdr)
153 // NOTES
154 // xx = late collision (data received before collision)
155 // late collisions cannot be detected by the receiver
156 // they would appear as JAM bits which would appear as bad FCS
157 // or carrier extend error which is CVMX_PIP_EXTEND_ERR
158
159
160
131 CVMX_PIP_PARTIAL_ERR = 1ull, /* RGM+SPI 1 = partially received packet (buffering/bandwidth not adequate) */
132 CVMX_PIP_JABBER_ERR = 2ull, /* RGM+SPI 2 = receive packet too large and truncated */
133 CVMX_PIP_OVER_FCS_ERR = 3ull, /* RGM 3 = max frame error (pkt len > max frame len) (with FCS error) */
134 CVMX_PIP_OVER_ERR = 4ull, /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
135 CVMX_PIP_ALIGN_ERR = 5ull, /* RGM 5 = nibble error (data not byte multiple - 100M and 10M only) */
136 CVMX_PIP_UNDER_FCS_ERR = 6ull, /* RGM 6 = min frame error (pkt len < min frame len) (with FCS error) */
137 CVMX_PIP_GMX_FCS_ERR = 7ull, /* RGM 7 = FCS error */
138 CVMX_PIP_UNDER_ERR = 8ull, /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
139 CVMX_PIP_EXTEND_ERR = 9ull, /* RGM 9 = Frame carrier extend error */
140 CVMX_PIP_TERMINATE_ERR = 9ull, /* XAUI 9 = Packet was terminated with an idle cycle */
141 CVMX_PIP_LENGTH_ERR = 10ull, /* RGM 10 = length mismatch (len did not match len in L2 length/type) */
142 CVMX_PIP_DAT_ERR = 11ull, /* RGM 11 = Frame error (some or all data bits marked err) */
143 CVMX_PIP_DIP_ERR = 11ull, /* SPI 11 = DIP4 error */
144 CVMX_PIP_SKIP_ERR = 12ull, /* RGM 12 = packet was not large enough to pass the skipper - no inspection could occur */
145 CVMX_PIP_NIBBLE_ERR = 13ull, /* RGM 13 = studder error (data not repeated - 100M and 10M only) */
146 CVMX_PIP_PIP_FCS = 16L, /* RGM+SPI 16 = FCS error */
147 CVMX_PIP_PIP_SKIP_ERR = 17L, /* RGM+SPI+PCI 17 = packet was not large enough to pass the skipper - no inspection could occur */
148 CVMX_PIP_PIP_L2_MAL_HDR= 18L, /* RGM+SPI+PCI 18 = malformed l2 (packet not long enough to cover L2 hdr) */
149 CVMX_PIP_PUNY_ERR = 47L /* SGMII 47 = PUNY error (packet was 4B or less when FCS stripping is enabled) */
150 /* NOTES
151 * xx = late collision (data received before collision)
152 * late collisions cannot be detected by the receiver
153 * they would appear as JAM bits which would appear as bad FCS
154 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
155 */
161} cvmx_pip_rcv_err_t;
162
163/**
164 * This defines the err_code field errors in the work Q entry
165 */
166typedef union
167{
168 cvmx_pip_l4_err_t l4_err;

--- 48 unchanged lines hidden (view full) ---

217 struct
218 {
219 uint64_t rawfull : 1; /**< Documented as R - Set if the Packet is RAWFULL. If set,
220 this header must be the full 8 bytes */
221 uint64_t reserved0 : 5; /**< Must be zero */
222 cvmx_pip_port_parse_mode_t parse_mode : 2; /**< PIP parse mode for this packet */
223 uint64_t reserved1 : 1; /**< Must be zero */
224 uint64_t skip_len : 7; /**< Skip amount, including this header, to the beginning of the packet */
156} cvmx_pip_rcv_err_t;
157
158/**
159 * This defines the err_code field errors in the work Q entry
160 */
161typedef union
162{
163 cvmx_pip_l4_err_t l4_err;

--- 48 unchanged lines hidden (view full) ---

212 struct
213 {
214 uint64_t rawfull : 1; /**< Documented as R - Set if the Packet is RAWFULL. If set,
215 this header must be the full 8 bytes */
216 uint64_t reserved0 : 5; /**< Must be zero */
217 cvmx_pip_port_parse_mode_t parse_mode : 2; /**< PIP parse mode for this packet */
218 uint64_t reserved1 : 1; /**< Must be zero */
219 uint64_t skip_len : 7; /**< Skip amount, including this header, to the beginning of the packet */
225 uint64_t reserved2 : 6; /**< Must be zero */
220 uint64_t reserved2 : 2; /**< Must be zero */
221 uint64_t nqos : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
222 When set to 1, NQOS prevents PIP from directly using
223 PKT_INST_HDR[QOS] for the QOS value in WQE.
224 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NQOS */
225 uint64_t ngrp : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
226 When set to 1, NGPR prevents PIP from directly using
227 PKT_INST_HDR[GPR] for the GPR value in WQE.
228 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NGRP */
229 uint64_t ntt : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
230 When set to 1, NTT prevents PIP from directly using
231 PKT_INST_HDR[TT] for the TT value in WQE.
232 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTT */
233 uint64_t ntag : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
234 When set to 1, NTAG prevents PIP from directly using
235 PKT_INST_HDR[TAG] for the TAG value in WQE.
236 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTAG */
226 uint64_t qos : 3; /**< POW input queue for this packet */
227 uint64_t grp : 4; /**< POW input group for this packet */
228 uint64_t rs : 1; /**< Flag to store this packet in the work queue entry, if possible */
229 cvmx_pow_tag_type_t tag_type : 2; /**< POW input tag type */
230 uint64_t tag : 32; /**< POW input tag */
231 } s;
232} cvmx_pip_pkt_inst_hdr_t;
233
237 uint64_t qos : 3; /**< POW input queue for this packet */
238 uint64_t grp : 4; /**< POW input group for this packet */
239 uint64_t rs : 1; /**< Flag to store this packet in the work queue entry, if possible */
240 cvmx_pow_tag_type_t tag_type : 2; /**< POW input tag type */
241 uint64_t tag : 32; /**< POW input tag */
242 } s;
243} cvmx_pip_pkt_inst_hdr_t;
244
234/* CSR typedefs have been moved to cvmx-csr-*.h */
245/* CSR typedefs have been moved to cvmx-pip-defs.h */
235
236/**
237 * Configure an ethernet input port
238 *
239 * @param port_num Port number to configure
240 * @param port_cfg Port hardware configuration
241 * @param port_tag_cfg
242 * Port POW tagging configuration
243 */
244static inline void cvmx_pip_config_port(uint64_t port_num,
246
247/**
248 * Configure an ethernet input port
249 *
250 * @param port_num Port number to configure
251 * @param port_cfg Port hardware configuration
252 * @param port_tag_cfg
253 * Port POW tagging configuration
254 */
255static inline void cvmx_pip_config_port(uint64_t port_num,
245 cvmx_pip_port_cfg_t port_cfg,
246 cvmx_pip_port_tag_cfg_t port_tag_cfg)
256 cvmx_pip_prt_cfgx_t port_cfg,
257 cvmx_pip_prt_tagx_t port_tag_cfg)
247{
248 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
249 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
250}
251
252
253/**
254 * @deprecated This function is a thin wrapper around the Pass1 version

--- 10 unchanged lines hidden (view full) ---

265 * @param match_value
266 * Value the watcher will match against
267 * @param qos QoS queue for packets matching this watcher
268 */
269static inline void cvmx_pip_config_watcher(uint64_t watcher,
270 cvmx_pip_qos_watch_types match_type,
271 uint64_t match_value, uint64_t qos)
272{
258{
259 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
260 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
261}
262
263
264/**
265 * @deprecated This function is a thin wrapper around the Pass1 version

--- 10 unchanged lines hidden (view full) ---

276 * @param match_value
277 * Value the watcher will match against
278 * @param qos QoS queue for packets matching this watcher
279 */
280static inline void cvmx_pip_config_watcher(uint64_t watcher,
281 cvmx_pip_qos_watch_types match_type,
282 uint64_t match_value, uint64_t qos)
283{
273 cvmx_pip_port_watcher_cfg_t watcher_config;
284 cvmx_pip_qos_watchx_t watcher_config;
274
275 watcher_config.u64 = 0;
276 watcher_config.s.match_type = match_type;
277 watcher_config.s.match_value = match_value;
278 watcher_config.s.qos = qos;
279
280 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
281}

--- 53 unchanged lines hidden (view full) ---

335 cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
336 cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
337 cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
338
339 pip_stat_ctl.u64 = 0;
340 pip_stat_ctl.s.rdclr = clear;
341 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
342
285
286 watcher_config.u64 = 0;
287 watcher_config.s.match_type = match_type;
288 watcher_config.s.match_value = match_value;
289 watcher_config.s.qos = qos;
290
291 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
292}

--- 53 unchanged lines hidden (view full) ---

346 cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
347 cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
348 cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
349
350 pip_stat_ctl.u64 = 0;
351 pip_stat_ctl.s.rdclr = clear;
352 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
353
343 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
344 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
345 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
346 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
347 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
348 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
349 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
350 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
351 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
352 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
354 if (port_num >= 40)
355 {
356 stat0.u64 = cvmx_read_csr(CVMX_PIP_XSTAT0_PRTX(port_num));
357 stat1.u64 = cvmx_read_csr(CVMX_PIP_XSTAT1_PRTX(port_num));
358 stat2.u64 = cvmx_read_csr(CVMX_PIP_XSTAT2_PRTX(port_num));
359 stat3.u64 = cvmx_read_csr(CVMX_PIP_XSTAT3_PRTX(port_num));
360 stat4.u64 = cvmx_read_csr(CVMX_PIP_XSTAT4_PRTX(port_num));
361 stat5.u64 = cvmx_read_csr(CVMX_PIP_XSTAT5_PRTX(port_num));
362 stat6.u64 = cvmx_read_csr(CVMX_PIP_XSTAT6_PRTX(port_num));
363 stat7.u64 = cvmx_read_csr(CVMX_PIP_XSTAT7_PRTX(port_num));
364 stat8.u64 = cvmx_read_csr(CVMX_PIP_XSTAT8_PRTX(port_num));
365 stat9.u64 = cvmx_read_csr(CVMX_PIP_XSTAT9_PRTX(port_num));
366 }
367 else
368 {
369 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
370 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
371 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
372 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
373 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
374 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
375 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
376 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
377 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
378 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
379 }
353 pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
354 pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
355 pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
356
357 status->dropped_octets = stat0.s.drp_octs;
358 status->dropped_packets = stat0.s.drp_pkts;
359 status->octets = stat1.s.octs;
360 status->pci_raw_packets = stat2.s.raw;

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372 status->runt_packets = stat8.s.undersz;
373 status->runt_crc_packets = stat8.s.frag;
374 status->oversize_packets = stat9.s.oversz;
375 status->oversize_crc_packets = stat9.s.jabber;
376 status->inb_packets = pip_stat_inb_pktsx.s.pkts;
377 status->inb_octets = pip_stat_inb_octsx.s.octs;
378 status->inb_errors = pip_stat_inb_errsx.s.errs;
379
380 pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
381 pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
382 pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
383
384 status->dropped_octets = stat0.s.drp_octs;
385 status->dropped_packets = stat0.s.drp_pkts;
386 status->octets = stat1.s.octs;
387 status->pci_raw_packets = stat2.s.raw;

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399 status->runt_packets = stat8.s.undersz;
400 status->runt_crc_packets = stat8.s.frag;
401 status->oversize_packets = stat9.s.oversz;
402 status->oversize_crc_packets = stat9.s.jabber;
403 status->inb_packets = pip_stat_inb_pktsx.s.pkts;
404 status->inb_octets = pip_stat_inb_octsx.s.octs;
405 status->inb_errors = pip_stat_inb_errsx.s.errs;
406
380 if (cvmx_octeon_is_pass1())
381 {
382 /* Kludge to fix Octeon Pass 1 errata - Drop counts don't work */
383 if (status->inb_packets > status->packets)
384 status->dropped_packets = status->inb_packets - status->packets;
385 else
386 status->dropped_packets = 0;
387 if (status->inb_octets - status->inb_packets*4 > status->octets)
388 status->dropped_octets = status->inb_octets - status->inb_packets*4 - status->octets;
389 else
390 status->dropped_octets = 0;
391 }
392}
393
394
395/**
396 * Configure the hardware CRC engine
397 *
398 * @param interface Interface to configure (0 or 1)
399 * @param invert_result

--- 76 unchanged lines hidden --- 		407}
408
409
410/**
411 * Configure the hardware CRC engine
412 *
413 * @param interface Interface to configure (0 or 1)
414 * @param invert_result

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